| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1639695638 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1429884947 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3827350503 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1890404814 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3862064413 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2896852827 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1855421064 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1463837608 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2714902716 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1968478684 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3631467474 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4266481544 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1431844291 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1914457106 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.712605117 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1988980087 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2245028102 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.571687216 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3813906653 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.423574805 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2852514640 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3291170695 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4019100112 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4287763049 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2999534835 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4242912290 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3940921730 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2530861570 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3196770699 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1073035849 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3010681287 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1966348220 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2820496669 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3409187773 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2956480442 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1985856480 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1926875948 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4010509587 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.300059136 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3235489161 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3063316367 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2353149245 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.735571578 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2444995466 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1003390918 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1449509063 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.10421029 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2477758058 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1936206780 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3069434315 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1741230692 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.413724419 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1292092539 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.726035207 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4178189726 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1736960543 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.34945025 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.867989628 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1633953079 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1436313523 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1694811516 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1684066936 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1500083963 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.922562985 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.551230522 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3891229492 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1182718664 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.885703881 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.559286783 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2645800448 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4075134652 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1346751192 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1625018947 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.678150327 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2796191038 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3985376449 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3138099818 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.404579095 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2937017700 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1491466721 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.457770545 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3422027111 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2558038499 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.164576136 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1917003254 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.212626241 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1252249197 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.309662884 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.152291042 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3485807478 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4193150480 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3258431874 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2008404576 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1983540824 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2318387272 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.683824117 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1987597929 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3644362404 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.669477510 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3251250633 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3756556534 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.24310838 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2345782175 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1726510849 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.974506130 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2019259566 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.106782805 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.900124621 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3108289462 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4085411703 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.115215424 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4214300551 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.18599547 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2586883345 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1647638613 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3798559677 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4111010999 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2214218661 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1077561597 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.474631277 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2240772144 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2919725514 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3827034177 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3385906171 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.924826720 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3264985639 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2467488201 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1611494309 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3466548858 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3958340087 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.684391380 |
| /workspace/coverage/default/0.sram_ctrl_bijection.501557668 |
| /workspace/coverage/default/0.sram_ctrl_executable.3102852186 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.4084085387 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2742239364 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1674844817 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.309062205 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.670501555 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3730015996 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2303159598 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.2677870482 |
| /workspace/coverage/default/0.sram_ctrl_regwen.2214115141 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2487188654 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3788448468 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2140708364 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4123635461 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3937748171 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2004085550 |
| /workspace/coverage/default/1.sram_ctrl_executable.3789501697 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3960690583 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2706791792 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2131691254 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2499894727 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.548796684 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3238653658 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.256726239 |
| /workspace/coverage/default/1.sram_ctrl_regwen.174313453 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3415810023 |
| /workspace/coverage/default/1.sram_ctrl_smoke.253613778 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.4207619266 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.902551720 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1921314934 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3308302620 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2476275675 |
| /workspace/coverage/default/10.sram_ctrl_bijection.886362355 |
| /workspace/coverage/default/10.sram_ctrl_executable.3831208427 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.4264729520 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3987209397 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.467323609 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2757269987 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.390752767 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1448320672 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1926637608 |
| /workspace/coverage/default/10.sram_ctrl_smoke.3065587100 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.938273717 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3195583625 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1951351903 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2232682435 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.3358025692 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1739971020 |
| /workspace/coverage/default/11.sram_ctrl_executable.4088293313 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.966467676 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.428591768 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.720746272 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2897030128 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3103974986 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3741140775 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2657457243 |
| /workspace/coverage/default/11.sram_ctrl_regwen.3411875323 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2865799760 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.918983167 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.799820153 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1190326506 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.966337071 |
| /workspace/coverage/default/12.sram_ctrl_bijection.1893839325 |
| /workspace/coverage/default/12.sram_ctrl_executable.317348384 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.218239762 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.4203543311 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.4155524160 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.1223299940 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1507463764 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1376322298 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.986931884 |
| /workspace/coverage/default/12.sram_ctrl_regwen.955212577 |
| /workspace/coverage/default/12.sram_ctrl_smoke.435068222 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1907236406 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4152225585 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2574867252 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3058904818 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.2993560509 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3472917309 |
| /workspace/coverage/default/13.sram_ctrl_executable.3861710402 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.1199551430 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1649461472 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1534511876 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.36728817 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1306163091 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.3980412252 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3450799516 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1593392717 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2163017110 |
| /workspace/coverage/default/13.sram_ctrl_smoke.819076140 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.1555630845 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3714951300 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.4200044709 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3415808170 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3218821839 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1274759349 |
| /workspace/coverage/default/14.sram_ctrl_executable.1360930108 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.459398518 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.1944386560 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4065873024 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3044044957 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.891127431 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.397708509 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.403540224 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2019002136 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1171727631 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1604655620 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.3597027962 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1958438795 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1372000359 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3187577118 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.2635935123 |
| /workspace/coverage/default/15.sram_ctrl_bijection.502668552 |
| /workspace/coverage/default/15.sram_ctrl_executable.459976202 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.774423471 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.3866294724 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1507315268 |
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| /workspace/coverage/default/47.sram_ctrl_max_throughput.99237668 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.743635633 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1528431784 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.2859394229 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2494665235 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3159859880 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.203616824 |
| /workspace/coverage/default/47.sram_ctrl_regwen.2884449597 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1689691694 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.733973472 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.770199899 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2947499007 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1449561867 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2769894218 |
| /workspace/coverage/default/48.sram_ctrl_executable.3651264682 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2485900094 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2788791241 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1804833737 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2408728240 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.3072866258 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.4132758900 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.625754837 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2880044268 |
| /workspace/coverage/default/48.sram_ctrl_regwen.4210099862 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1146585720 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3888440282 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1124993069 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1279924135 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1554488621 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1647792354 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1125284323 |
| /workspace/coverage/default/49.sram_ctrl_executable.3307975894 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.426808133 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.3295225771 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3728992246 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3611914860 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3369058885 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3837224169 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4153759297 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.3156617093 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1247251611 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3193296509 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3051178876 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1864759666 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.84506520 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1279835738 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3578837406 |
| /workspace/coverage/default/5.sram_ctrl_executable.4278124566 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3960509567 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1229431723 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1889634073 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2921838092 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.696052316 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2914760165 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2893726968 |
| /workspace/coverage/default/5.sram_ctrl_regwen.966287299 |
| /workspace/coverage/default/5.sram_ctrl_smoke.794398465 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2408154475 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.87343907 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.427981489 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.425584135 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3754601569 |
| /workspace/coverage/default/6.sram_ctrl_executable.3774129575 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1204501947 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2217500692 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.4189394076 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3635948881 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.4288090800 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.75599621 |
| /workspace/coverage/default/6.sram_ctrl_regwen.1735570266 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2724136520 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1760438513 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.284818575 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.480419491 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.22569319 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.3354375711 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1127196658 |
| /workspace/coverage/default/7.sram_ctrl_executable.4017816804 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.795328356 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3077824801 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.4189169594 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3116813578 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1852155845 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.235484366 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3038622708 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.858735719 |
| /workspace/coverage/default/7.sram_ctrl_regwen.1713589586 |
| /workspace/coverage/default/7.sram_ctrl_smoke.2938966137 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.802178342 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3165330781 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1863303697 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2019506412 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3864702535 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2902575652 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1771339515 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.663892415 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.92519001 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.3364306502 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2331806477 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3241134191 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1419343731 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3313847822 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1859572601 |
| /workspace/coverage/default/8.sram_ctrl_smoke.799454872 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1243700347 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.521292846 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1953222867 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.560908060 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.304996835 |
| /workspace/coverage/default/9.sram_ctrl_bijection.393692745 |
| /workspace/coverage/default/9.sram_ctrl_executable.3808031106 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.1359664896 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.1339343877 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2577907470 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.1623891589 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3791819953 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3636945599 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.60544580 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1539007604 |
| /workspace/coverage/default/9.sram_ctrl_smoke.299795902 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.1769760707 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3482769051 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1261336648 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3725281541 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/19.sram_ctrl_executable.2594734115 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 01:10:26 PM PST 24 |
12354511699 ps |
| T2 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.173218332 |
|
|
Mar 05 12:56:46 PM PST 24 |
Mar 05 01:02:34 PM PST 24 |
51930760211 ps |
| T3 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2623222663 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:58:28 PM PST 24 |
249769558 ps |
| T4 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.168266100 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 01:00:49 PM PST 24 |
17455583271 ps |
| T5 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3484265810 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:09 PM PST 24 |
849212281 ps |
| T8 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.203616824 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 12:58:20 PM PST 24 |
28551672 ps |
| T9 |
/workspace/coverage/default/5.sram_ctrl_regwen.966287299 |
|
|
Mar 05 12:53:13 PM PST 24 |
Mar 05 01:08:18 PM PST 24 |
47312731615 ps |
| T10 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4132758900 |
|
|
Mar 05 12:58:28 PM PST 24 |
Mar 05 12:59:24 PM PST 24 |
2139802536 ps |
| T11 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2233320867 |
|
|
Mar 05 12:58:06 PM PST 24 |
Mar 05 12:58:07 PM PST 24 |
26285248 ps |
| T12 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2988237683 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 12:58:02 PM PST 24 |
1493083025 ps |
| T13 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.238327181 |
|
|
Mar 05 12:55:53 PM PST 24 |
Mar 05 12:57:52 PM PST 24 |
247633734 ps |
| T14 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1770823014 |
|
|
Mar 05 12:55:52 PM PST 24 |
Mar 05 12:56:11 PM PST 24 |
155791952 ps |
| T6 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1199551430 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 12:54:14 PM PST 24 |
774478263 ps |
| T15 |
/workspace/coverage/default/29.sram_ctrl_smoke.3286666275 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 12:55:53 PM PST 24 |
149816597 ps |
| T77 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2331806477 |
|
|
Mar 05 12:53:31 PM PST 24 |
Mar 05 01:15:46 PM PST 24 |
18990764833 ps |
| T24 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3984872191 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:54:54 PM PST 24 |
58979413 ps |
| T16 |
/workspace/coverage/default/18.sram_ctrl_stress_all.4240638474 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 02:11:38 PM PST 24 |
183602375726 ps |
| T62 |
/workspace/coverage/default/25.sram_ctrl_regwen.3411068821 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 01:16:28 PM PST 24 |
14570446578 ps |
| T27 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2969312881 |
|
|
Mar 05 12:56:10 PM PST 24 |
Mar 05 01:48:53 PM PST 24 |
18325214601 ps |
| T152 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.966467676 |
|
|
Mar 05 12:53:57 PM PST 24 |
Mar 05 12:54:17 PM PST 24 |
438521510 ps |
| T75 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.793750638 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 01:13:36 PM PST 24 |
8137801594 ps |
| T109 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.4283948044 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:55:41 PM PST 24 |
229730081 ps |
| T33 |
/workspace/coverage/default/21.sram_ctrl_smoke.1568649875 |
|
|
Mar 05 12:55:01 PM PST 24 |
Mar 05 12:55:04 PM PST 24 |
264430313 ps |
| T76 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3194136089 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:59:10 PM PST 24 |
4365427582 ps |
| T25 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2421107400 |
|
|
Mar 05 12:57:43 PM PST 24 |
Mar 05 12:57:44 PM PST 24 |
15106526 ps |
| T147 |
/workspace/coverage/default/6.sram_ctrl_executable.3774129575 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:53:48 PM PST 24 |
442241159 ps |
| T148 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2416666631 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:59:11 PM PST 24 |
272253045 ps |
| T28 |
/workspace/coverage/default/29.sram_ctrl_regwen.1132411547 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 01:06:21 PM PST 24 |
3028697586 ps |
| T7 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1052430506 |
|
|
Mar 05 12:56:43 PM PST 24 |
Mar 05 12:57:04 PM PST 24 |
2123152101 ps |
| T101 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.873272488 |
|
|
Mar 05 12:56:12 PM PST 24 |
Mar 05 12:59:19 PM PST 24 |
2609412302 ps |
| T102 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.4283831004 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 01:02:04 PM PST 24 |
14173198725 ps |
| T34 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3191940566 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 12:59:38 PM PST 24 |
2927401018 ps |
| T35 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1093161885 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 12:56:39 PM PST 24 |
2534747388 ps |
| T21 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1611283486 |
|
|
Mar 05 12:58:10 PM PST 24 |
Mar 05 12:59:27 PM PST 24 |
1451777353 ps |
| T56 |
/workspace/coverage/default/31.sram_ctrl_smoke.2354649773 |
|
|
Mar 05 12:56:10 PM PST 24 |
Mar 05 12:56:26 PM PST 24 |
3127334459 ps |
| T26 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1279835738 |
|
|
Mar 05 12:53:20 PM PST 24 |
Mar 05 12:53:22 PM PST 24 |
33929281 ps |
| T57 |
/workspace/coverage/default/12.sram_ctrl_regwen.955212577 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 01:09:43 PM PST 24 |
19906171765 ps |
| T58 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3157155702 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 01:22:10 PM PST 24 |
98601351213 ps |
| T59 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3943901407 |
|
|
Mar 05 12:56:10 PM PST 24 |
Mar 05 12:56:16 PM PST 24 |
462281400 ps |
| T37 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2640885179 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:56:56 PM PST 24 |
93343304 ps |
| T60 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3833000122 |
|
|
Mar 05 12:52:47 PM PST 24 |
Mar 05 12:52:58 PM PST 24 |
229369704 ps |
| T61 |
/workspace/coverage/default/44.sram_ctrl_bijection.3203527021 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 12:58:49 PM PST 24 |
23562716754 ps |
| T63 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3947022881 |
|
|
Mar 05 12:53:00 PM PST 24 |
Mar 05 12:53:12 PM PST 24 |
1506482497 ps |
| T145 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2756030795 |
|
|
Mar 05 12:54:45 PM PST 24 |
Mar 05 12:55:11 PM PST 24 |
355433297 ps |
| T146 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2566972502 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 12:55:01 PM PST 24 |
515191744 ps |
| T22 |
/workspace/coverage/default/36.sram_ctrl_executable.3875273405 |
|
|
Mar 05 12:56:56 PM PST 24 |
Mar 05 12:57:07 PM PST 24 |
1205041997 ps |
| T153 |
/workspace/coverage/default/27.sram_ctrl_smoke.2167675204 |
|
|
Mar 05 12:55:46 PM PST 24 |
Mar 05 12:56:00 PM PST 24 |
925685000 ps |
| T154 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4085617349 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:55:27 PM PST 24 |
215562251 ps |
| T103 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3987173007 |
|
|
Mar 05 12:58:01 PM PST 24 |
Mar 05 01:03:26 PM PST 24 |
17678968858 ps |
| T64 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.287496152 |
|
|
Mar 05 12:53:59 PM PST 24 |
Mar 05 12:54:12 PM PST 24 |
2932623846 ps |
| T104 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1354354585 |
|
|
Mar 05 12:55:52 PM PST 24 |
Mar 05 12:59:31 PM PST 24 |
3142243489 ps |
| T155 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.4288341215 |
|
|
Mar 05 12:56:44 PM PST 24 |
Mar 05 12:56:46 PM PST 24 |
111633285 ps |
| T142 |
/workspace/coverage/default/6.sram_ctrl_regwen.1735570266 |
|
|
Mar 05 12:53:21 PM PST 24 |
Mar 05 12:57:46 PM PST 24 |
2995697065 ps |
| T156 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1259250072 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:59:10 PM PST 24 |
494680594 ps |
| T82 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2779068973 |
|
|
Mar 05 12:56:37 PM PST 24 |
Mar 05 12:56:42 PM PST 24 |
204970707 ps |
| T157 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.483721095 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 01:00:59 PM PST 24 |
14203570531 ps |
| T141 |
/workspace/coverage/default/26.sram_ctrl_executable.3570346911 |
|
|
Mar 05 12:55:35 PM PST 24 |
Mar 05 12:57:58 PM PST 24 |
1911639013 ps |
| T150 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1365223753 |
|
|
Mar 05 12:55:05 PM PST 24 |
Mar 05 12:56:25 PM PST 24 |
2986191477 ps |
| T158 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.479571382 |
|
|
Mar 05 12:53:04 PM PST 24 |
Mar 05 12:53:08 PM PST 24 |
81465746 ps |
| T36 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3221293923 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 01:00:46 PM PST 24 |
465830950 ps |
| T159 |
/workspace/coverage/default/40.sram_ctrl_bijection.1956520251 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 12:58:06 PM PST 24 |
1946719809 ps |
| T160 |
/workspace/coverage/default/9.sram_ctrl_alert_test.304996835 |
|
|
Mar 05 12:53:44 PM PST 24 |
Mar 05 12:53:44 PM PST 24 |
12684589 ps |
| T83 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2217500692 |
|
|
Mar 05 12:53:21 PM PST 24 |
Mar 05 12:53:26 PM PST 24 |
160336976 ps |
| T149 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.891127431 |
|
|
Mar 05 12:54:22 PM PST 24 |
Mar 05 01:17:22 PM PST 24 |
21044434127 ps |
| T161 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2584131533 |
|
|
Mar 05 12:57:59 PM PST 24 |
Mar 05 12:58:00 PM PST 24 |
28601617 ps |
| T29 |
/workspace/coverage/default/35.sram_ctrl_regwen.4131845512 |
|
|
Mar 05 12:56:46 PM PST 24 |
Mar 05 01:06:42 PM PST 24 |
2567151391 ps |
| T162 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3186930351 |
|
|
Mar 05 12:57:29 PM PST 24 |
Mar 05 12:58:16 PM PST 24 |
227085857 ps |
| T151 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1140118695 |
|
|
Mar 05 12:58:07 PM PST 24 |
Mar 05 12:59:21 PM PST 24 |
2153749988 ps |
| T163 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2413230451 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:59:13 PM PST 24 |
666267043 ps |
| T164 |
/workspace/coverage/default/44.sram_ctrl_partial_access.981047010 |
|
|
Mar 05 12:58:04 PM PST 24 |
Mar 05 12:58:20 PM PST 24 |
293238742 ps |
| T165 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4123635461 |
|
|
Mar 05 12:52:35 PM PST 24 |
Mar 05 12:57:30 PM PST 24 |
25762581512 ps |
| T144 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2936304774 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 01:10:01 PM PST 24 |
4592763504 ps |
| T166 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1907223976 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 01:07:35 PM PST 24 |
2495682821 ps |
| T167 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.667355128 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 12:58:28 PM PST 24 |
153050771 ps |
| T168 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1419343731 |
|
|
Mar 05 12:53:32 PM PST 24 |
Mar 05 12:55:46 PM PST 24 |
11287931109 ps |
| T169 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1041541486 |
|
|
Mar 05 12:55:26 PM PST 24 |
Mar 05 12:57:01 PM PST 24 |
1589214994 ps |
| T30 |
/workspace/coverage/default/36.sram_ctrl_regwen.4029310484 |
|
|
Mar 05 12:56:53 PM PST 24 |
Mar 05 01:09:57 PM PST 24 |
4672442990 ps |
| T170 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3957803135 |
|
|
Mar 05 12:53:06 PM PST 24 |
Mar 05 12:53:32 PM PST 24 |
261679490 ps |
| T171 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.761716690 |
|
|
Mar 05 12:54:46 PM PST 24 |
Mar 05 12:54:47 PM PST 24 |
97633237 ps |
| T172 |
/workspace/coverage/default/22.sram_ctrl_bijection.1145541864 |
|
|
Mar 05 12:55:11 PM PST 24 |
Mar 05 12:55:39 PM PST 24 |
451118740 ps |
| T126 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2485900094 |
|
|
Mar 05 12:58:28 PM PST 24 |
Mar 05 12:58:35 PM PST 24 |
497841679 ps |
| T173 |
/workspace/coverage/default/13.sram_ctrl_smoke.819076140 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 12:54:08 PM PST 24 |
77639995 ps |
| T174 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.208865326 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 01:00:51 PM PST 24 |
3431907781 ps |
| T175 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.427981489 |
|
|
Mar 05 12:53:13 PM PST 24 |
Mar 05 12:54:24 PM PST 24 |
544484333 ps |
| T139 |
/workspace/coverage/default/7.sram_ctrl_regwen.1713589586 |
|
|
Mar 05 12:53:33 PM PST 24 |
Mar 05 01:03:29 PM PST 24 |
2058983151 ps |
| T143 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2986146387 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 12:56:29 PM PST 24 |
696228550 ps |
| T140 |
/workspace/coverage/default/2.sram_ctrl_regwen.2711840435 |
|
|
Mar 05 12:52:56 PM PST 24 |
Mar 05 12:59:03 PM PST 24 |
5051693009 ps |
| T49 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.579462565 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 01:00:53 PM PST 24 |
2099192261 ps |
| T176 |
/workspace/coverage/default/49.sram_ctrl_regwen.1247251611 |
|
|
Mar 05 12:58:43 PM PST 24 |
Mar 05 01:03:32 PM PST 24 |
10308678330 ps |
| T177 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.211826931 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 12:58:05 PM PST 24 |
1925960144 ps |
| T23 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2131776163 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 01:21:13 PM PST 24 |
16898465537 ps |
| T178 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3622429637 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 12:52:50 PM PST 24 |
165238689 ps |
| T179 |
/workspace/coverage/default/26.sram_ctrl_bijection.2360481324 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:56:00 PM PST 24 |
1573875871 ps |
| T180 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3530684475 |
|
|
Mar 05 12:58:02 PM PST 24 |
Mar 05 12:58:11 PM PST 24 |
1760221382 ps |
| T181 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.320402956 |
|
|
Mar 05 12:55:59 PM PST 24 |
Mar 05 01:01:57 PM PST 24 |
10110405476 ps |
| T182 |
/workspace/coverage/default/25.sram_ctrl_smoke.3682594178 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:55:46 PM PST 24 |
266304666 ps |
| T50 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.521292846 |
|
|
Mar 05 12:53:39 PM PST 24 |
Mar 05 12:54:02 PM PST 24 |
2027104009 ps |
| T118 |
/workspace/coverage/default/32.sram_ctrl_executable.2217442463 |
|
|
Mar 05 12:56:19 PM PST 24 |
Mar 05 01:14:20 PM PST 24 |
4400897934 ps |
| T119 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3979200864 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 01:01:10 PM PST 24 |
15522633940 ps |
| T120 |
/workspace/coverage/default/47.sram_ctrl_alert_test.247160353 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 12:58:20 PM PST 24 |
16569240 ps |
| T121 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3741140775 |
|
|
Mar 05 12:53:58 PM PST 24 |
Mar 05 12:59:46 PM PST 24 |
15933708399 ps |
| T122 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2608677306 |
|
|
Mar 05 12:56:34 PM PST 24 |
Mar 05 12:56:46 PM PST 24 |
644541152 ps |
| T123 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1080135434 |
|
|
Mar 05 12:58:09 PM PST 24 |
Mar 05 01:05:05 PM PST 24 |
36795859652 ps |
| T124 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2612251180 |
|
|
Mar 05 12:55:21 PM PST 24 |
Mar 05 01:00:00 PM PST 24 |
41523565518 ps |
| T84 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1539431561 |
|
|
Mar 05 12:58:05 PM PST 24 |
Mar 05 12:58:10 PM PST 24 |
568827287 ps |
| T125 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3072866258 |
|
|
Mar 05 12:58:17 PM PST 24 |
Mar 05 01:04:32 PM PST 24 |
14828468059 ps |
| T183 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.480419491 |
|
|
Mar 05 12:53:21 PM PST 24 |
Mar 05 12:58:35 PM PST 24 |
3342010544 ps |
| T184 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2694835104 |
|
|
Mar 05 12:57:16 PM PST 24 |
Mar 05 12:57:22 PM PST 24 |
567096094 ps |
| T185 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2047564146 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 12:55:24 PM PST 24 |
227285356 ps |
| T186 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.799820153 |
|
|
Mar 05 12:54:02 PM PST 24 |
Mar 05 12:59:47 PM PST 24 |
7312866206 ps |
| T187 |
/workspace/coverage/default/33.sram_ctrl_smoke.1035558875 |
|
|
Mar 05 12:56:29 PM PST 24 |
Mar 05 12:56:33 PM PST 24 |
172833675 ps |
| T188 |
/workspace/coverage/default/42.sram_ctrl_smoke.1867293080 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:57:57 PM PST 24 |
112612707 ps |
| T189 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1602023024 |
|
|
Mar 05 12:57:14 PM PST 24 |
Mar 05 12:57:19 PM PST 24 |
769107905 ps |
| T190 |
/workspace/coverage/default/24.sram_ctrl_smoke.3252462915 |
|
|
Mar 05 12:55:27 PM PST 24 |
Mar 05 12:55:39 PM PST 24 |
579732929 ps |
| T51 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3104058088 |
|
|
Mar 05 12:55:43 PM PST 24 |
Mar 05 12:56:12 PM PST 24 |
2493516967 ps |
| T191 |
/workspace/coverage/default/23.sram_ctrl_executable.270356738 |
|
|
Mar 05 12:55:22 PM PST 24 |
Mar 05 01:05:22 PM PST 24 |
69452807272 ps |
| T192 |
/workspace/coverage/default/25.sram_ctrl_partial_access.4209341546 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:56:01 PM PST 24 |
526503802 ps |
| T193 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3315355186 |
|
|
Mar 05 12:57:07 PM PST 24 |
Mar 05 12:59:17 PM PST 24 |
1518184780 ps |
| T194 |
/workspace/coverage/default/12.sram_ctrl_smoke.435068222 |
|
|
Mar 05 12:53:56 PM PST 24 |
Mar 05 12:54:27 PM PST 24 |
1525480118 ps |
| T195 |
/workspace/coverage/default/33.sram_ctrl_executable.2843720693 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 01:07:00 PM PST 24 |
9501632820 ps |
| T85 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4065873024 |
|
|
Mar 05 12:54:16 PM PST 24 |
Mar 05 12:54:20 PM PST 24 |
123400960 ps |
| T86 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.92519001 |
|
|
Mar 05 12:53:43 PM PST 24 |
Mar 05 12:53:46 PM PST 24 |
92988120 ps |
| T196 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.3364306502 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:53:46 PM PST 24 |
238261048 ps |
| T197 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1555630845 |
|
|
Mar 05 12:54:18 PM PST 24 |
Mar 05 02:06:49 PM PST 24 |
238368641493 ps |
| T198 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2352773433 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 01:10:52 PM PST 24 |
3306255381 ps |
| T199 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3725281541 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:53:42 PM PST 24 |
133527558 ps |
| T200 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1339343877 |
|
|
Mar 05 12:53:40 PM PST 24 |
Mar 05 12:54:05 PM PST 24 |
90168883 ps |
| T201 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1022654522 |
|
|
Mar 05 12:55:11 PM PST 24 |
Mar 05 12:58:05 PM PST 24 |
3830543998 ps |
| T202 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3888440282 |
|
|
Mar 05 12:58:30 PM PST 24 |
Mar 05 01:12:28 PM PST 24 |
192204236606 ps |
| T52 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.361375324 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 01:01:39 PM PST 24 |
20498058071 ps |
| T203 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2303159598 |
|
|
Mar 05 12:52:35 PM PST 24 |
Mar 05 12:58:03 PM PST 24 |
15660069364 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3428770078 |
|
|
Mar 05 12:52:56 PM PST 24 |
Mar 05 01:40:51 PM PST 24 |
75949066608 ps |
| T204 |
/workspace/coverage/default/40.sram_ctrl_executable.2530486496 |
|
|
Mar 05 12:57:44 PM PST 24 |
Mar 05 01:07:13 PM PST 24 |
51192016382 ps |
| T205 |
/workspace/coverage/default/19.sram_ctrl_smoke.2322357569 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 12:55:08 PM PST 24 |
3611973642 ps |
| T206 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1204501947 |
|
|
Mar 05 12:53:19 PM PST 24 |
Mar 05 12:53:46 PM PST 24 |
94611184 ps |
| T207 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1646428630 |
|
|
Mar 05 12:56:47 PM PST 24 |
Mar 05 12:56:49 PM PST 24 |
82939104 ps |
| T208 |
/workspace/coverage/default/18.sram_ctrl_bijection.635147526 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 12:56:10 PM PST 24 |
9975747894 ps |
| T209 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.4170491811 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:57:04 PM PST 24 |
78483263 ps |
| T210 |
/workspace/coverage/default/28.sram_ctrl_smoke.2349340012 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 12:57:34 PM PST 24 |
2382131099 ps |
| T53 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2033919398 |
|
|
Mar 05 12:56:09 PM PST 24 |
Mar 05 12:56:44 PM PST 24 |
5027080695 ps |
| T211 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.706406121 |
|
|
Mar 05 12:58:05 PM PST 24 |
Mar 05 01:12:03 PM PST 24 |
71325959715 ps |
| T212 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2897030128 |
|
|
Mar 05 12:53:47 PM PST 24 |
Mar 05 01:05:23 PM PST 24 |
11664993522 ps |
| T213 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2234672036 |
|
|
Mar 05 12:55:44 PM PST 24 |
Mar 05 12:55:45 PM PST 24 |
30073359 ps |
| T214 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.278711695 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 01:00:31 PM PST 24 |
3294937115 ps |
| T215 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3282446651 |
|
|
Mar 05 12:57:44 PM PST 24 |
Mar 05 12:59:22 PM PST 24 |
2065557893 ps |
| T87 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2259434822 |
|
|
Mar 05 12:57:29 PM PST 24 |
Mar 05 12:57:34 PM PST 24 |
594720985 ps |
| T216 |
/workspace/coverage/default/1.sram_ctrl_regwen.174313453 |
|
|
Mar 05 12:52:51 PM PST 24 |
Mar 05 12:55:53 PM PST 24 |
14461980936 ps |
| T217 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1515177083 |
|
|
Mar 05 12:56:57 PM PST 24 |
Mar 05 01:01:08 PM PST 24 |
5584915193 ps |
| T32 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3878525558 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:17 PM PST 24 |
996802366 ps |
| T218 |
/workspace/coverage/default/12.sram_ctrl_alert_test.966337071 |
|
|
Mar 05 12:54:07 PM PST 24 |
Mar 05 12:54:08 PM PST 24 |
12694012 ps |
| T219 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3163662614 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 12:57:06 PM PST 24 |
7451843377 ps |
| T220 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2779268289 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 12:55:03 PM PST 24 |
141354358 ps |
| T88 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3885281296 |
|
|
Mar 05 12:55:17 PM PST 24 |
Mar 05 12:55:22 PM PST 24 |
386885907 ps |
| T221 |
/workspace/coverage/default/21.sram_ctrl_regwen.2842823667 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 01:03:11 PM PST 24 |
37004975426 ps |
| T222 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.598630936 |
|
|
Mar 05 12:55:14 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
29734014 ps |
| T223 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.997531214 |
|
|
Mar 05 12:56:09 PM PST 24 |
Mar 05 12:58:05 PM PST 24 |
136472548 ps |
| T54 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2061263887 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 12:58:31 PM PST 24 |
5311216127 ps |
| T224 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2470844649 |
|
|
Mar 05 12:54:27 PM PST 24 |
Mar 05 12:54:29 PM PST 24 |
44031014 ps |
| T225 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2019002136 |
|
|
Mar 05 12:54:19 PM PST 24 |
Mar 05 12:54:20 PM PST 24 |
30073066 ps |
| T226 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1907236406 |
|
|
Mar 05 12:54:07 PM PST 24 |
Mar 05 01:25:13 PM PST 24 |
20328003290 ps |
| T227 |
/workspace/coverage/default/27.sram_ctrl_regwen.2945830449 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 01:12:48 PM PST 24 |
45290582948 ps |
| T228 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3077824801 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:53:46 PM PST 24 |
88862009 ps |
| T229 |
/workspace/coverage/default/7.sram_ctrl_smoke.2938966137 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:55:40 PM PST 24 |
1293890215 ps |
| T89 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2955500493 |
|
|
Mar 05 12:56:24 PM PST 24 |
Mar 05 12:56:29 PM PST 24 |
251312039 ps |
| T230 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.74962063 |
|
|
Mar 05 12:56:16 PM PST 24 |
Mar 05 12:59:49 PM PST 24 |
3061455874 ps |
| T231 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.4181680714 |
|
|
Mar 05 12:54:43 PM PST 24 |
Mar 05 01:09:24 PM PST 24 |
11044670860 ps |
| T232 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1649461472 |
|
|
Mar 05 12:54:08 PM PST 24 |
Mar 05 12:55:31 PM PST 24 |
1228211065 ps |
| T233 |
/workspace/coverage/default/23.sram_ctrl_bijection.855397783 |
|
|
Mar 05 12:55:18 PM PST 24 |
Mar 05 12:55:41 PM PST 24 |
1401876030 ps |
| T234 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3339427419 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:57:32 PM PST 24 |
382483230 ps |
| T55 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2317779275 |
|
|
Mar 05 12:52:39 PM PST 24 |
Mar 05 01:02:33 PM PST 24 |
10718171132 ps |
| T235 |
/workspace/coverage/default/19.sram_ctrl_regwen.1995127779 |
|
|
Mar 05 12:54:55 PM PST 24 |
Mar 05 01:07:35 PM PST 24 |
22852698516 ps |
| T236 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3238653658 |
|
|
Mar 05 12:52:41 PM PST 24 |
Mar 05 12:54:57 PM PST 24 |
783717697 ps |
| T237 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1797076634 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 12:59:30 PM PST 24 |
249122379 ps |
| T238 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.4189394076 |
|
|
Mar 05 12:53:21 PM PST 24 |
Mar 05 12:53:29 PM PST 24 |
626983124 ps |
| T239 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1975221353 |
|
|
Mar 05 12:55:53 PM PST 24 |
Mar 05 12:56:01 PM PST 24 |
154431937 ps |
| T240 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1279924135 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 01:02:01 PM PST 24 |
9977860532 ps |
| T241 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2194739593 |
|
|
Mar 05 12:56:18 PM PST 24 |
Mar 05 01:04:03 PM PST 24 |
2712925558 ps |
| T242 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3067244718 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 12:52:49 PM PST 24 |
12222639 ps |
| T243 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3247038581 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:56:00 PM PST 24 |
95318454 ps |
| T244 |
/workspace/coverage/default/32.sram_ctrl_bijection.538974434 |
|
|
Mar 05 12:56:20 PM PST 24 |
Mar 05 12:57:37 PM PST 24 |
7377993507 ps |
| T245 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.10018517 |
|
|
Mar 05 12:55:25 PM PST 24 |
Mar 05 12:56:21 PM PST 24 |
1040983781 ps |
| T246 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1304322552 |
|
|
Mar 05 12:57:54 PM PST 24 |
Mar 05 12:57:55 PM PST 24 |
160425350 ps |
| T247 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.341356385 |
|
|
Mar 05 12:55:52 PM PST 24 |
Mar 05 12:57:52 PM PST 24 |
160421883 ps |
| T248 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.742542060 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:59:38 PM PST 24 |
752284964 ps |
| T249 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3313847822 |
|
|
Mar 05 12:53:44 PM PST 24 |
Mar 05 12:53:45 PM PST 24 |
36273213 ps |
| T250 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3796657921 |
|
|
Mar 05 12:58:02 PM PST 24 |
Mar 05 12:58:37 PM PST 24 |
3007898855 ps |
| T251 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3592746875 |
|
|
Mar 05 12:58:14 PM PST 24 |
Mar 05 12:58:15 PM PST 24 |
54703190 ps |
| T90 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.428591768 |
|
|
Mar 05 12:53:57 PM PST 24 |
Mar 05 12:54:02 PM PST 24 |
577173672 ps |
| T252 |
/workspace/coverage/default/39.sram_ctrl_executable.3175510816 |
|
|
Mar 05 12:57:16 PM PST 24 |
Mar 05 12:58:51 PM PST 24 |
2007546675 ps |
| T110 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2149420129 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:56:29 PM PST 24 |
3451195019 ps |
| T253 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3902009968 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 12:52:52 PM PST 24 |
93358500 ps |
| T254 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1604828632 |
|
|
Mar 05 12:57:58 PM PST 24 |
Mar 05 01:03:37 PM PST 24 |
23268187393 ps |
| T255 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1812541324 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:56:57 PM PST 24 |
164597320 ps |
| T256 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1277883997 |
|
|
Mar 05 12:56:18 PM PST 24 |
Mar 05 12:56:19 PM PST 24 |
27504202 ps |
| T257 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.4215747843 |
|
|
Mar 05 12:57:02 PM PST 24 |
Mar 05 12:59:53 PM PST 24 |
3693420674 ps |
| T258 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3058904818 |
|
|
Mar 05 12:53:58 PM PST 24 |
Mar 05 12:54:07 PM PST 24 |
67197359 ps |
| T259 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.459398518 |
|
|
Mar 05 12:54:21 PM PST 24 |
Mar 05 12:54:29 PM PST 24 |
488231341 ps |
| T260 |
/workspace/coverage/default/30.sram_ctrl_bijection.214266172 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:56:52 PM PST 24 |
2581423941 ps |
| T261 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.780751881 |
|
|
Mar 05 12:55:39 PM PST 24 |
Mar 05 12:55:40 PM PST 24 |
79275899 ps |
| T262 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2703055706 |
|
|
Mar 05 12:56:26 PM PST 24 |
Mar 05 12:56:31 PM PST 24 |
348229803 ps |
| T263 |
/workspace/coverage/default/37.sram_ctrl_bijection.2154456531 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:57:29 PM PST 24 |
2300591587 ps |
| T264 |
/workspace/coverage/default/3.sram_ctrl_regwen.726251353 |
|
|
Mar 05 12:53:00 PM PST 24 |
Mar 05 01:05:05 PM PST 24 |
3508195878 ps |
| T265 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2757269987 |
|
|
Mar 05 12:53:48 PM PST 24 |
Mar 05 12:54:46 PM PST 24 |
544943593 ps |
| T266 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3636945599 |
|
|
Mar 05 12:53:44 PM PST 24 |
Mar 05 01:01:25 PM PST 24 |
13485712457 ps |
| T267 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.231275294 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 01:14:35 PM PST 24 |
6179110858 ps |
| T268 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3178984748 |
|
|
Mar 05 12:57:17 PM PST 24 |
Mar 05 12:57:17 PM PST 24 |
23662389 ps |
| T269 |
/workspace/coverage/default/36.sram_ctrl_stress_all.4248312424 |
|
|
Mar 05 12:56:54 PM PST 24 |
Mar 05 02:01:35 PM PST 24 |
84047071720 ps |
| T270 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2499894727 |
|
|
Mar 05 12:52:47 PM PST 24 |
Mar 05 12:52:57 PM PST 24 |
2869111636 ps |
| T271 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1921314934 |
|
|
Mar 05 12:52:41 PM PST 24 |
Mar 05 12:55:56 PM PST 24 |
2188856344 ps |
| T272 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3951541268 |
|
|
Mar 05 12:52:58 PM PST 24 |
Mar 05 01:00:38 PM PST 24 |
8933049903 ps |
| T273 |
/workspace/coverage/default/2.sram_ctrl_bijection.1126225454 |
|
|
Mar 05 12:52:46 PM PST 24 |
Mar 05 12:53:06 PM PST 24 |
932601405 ps |
| T274 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1713697015 |
|
|
Mar 05 12:57:14 PM PST 24 |
Mar 05 12:57:15 PM PST 24 |
147171501 ps |
| T275 |
/workspace/coverage/default/9.sram_ctrl_executable.3808031106 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 01:01:57 PM PST 24 |
9761196740 ps |
| T18 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.4136524272 |
|
|
Mar 05 12:53:00 PM PST 24 |
Mar 05 12:53:01 PM PST 24 |
685350215 ps |
| T40 |
/workspace/coverage/default/45.sram_ctrl_regwen.522076289 |
|
|
Mar 05 12:58:06 PM PST 24 |
Mar 05 01:13:49 PM PST 24 |
12276372976 ps |
| T41 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2987909151 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 12:58:26 PM PST 24 |
8879998857 ps |
| T42 |
/workspace/coverage/default/24.sram_ctrl_partial_access.95456421 |
|
|
Mar 05 12:55:24 PM PST 24 |
Mar 05 12:55:26 PM PST 24 |
601224983 ps |
| T43 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.724559993 |
|
|
Mar 05 12:57:15 PM PST 24 |
Mar 05 12:57:16 PM PST 24 |
27693928 ps |
| T44 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2721001742 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 12:58:08 PM PST 24 |
269937967 ps |
| T45 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3599477642 |
|
|
Mar 05 12:56:03 PM PST 24 |
Mar 05 12:56:04 PM PST 24 |
29747332 ps |
| T46 |
/workspace/coverage/default/46.sram_ctrl_partial_access.948308084 |
|
|
Mar 05 12:58:13 PM PST 24 |
Mar 05 12:58:18 PM PST 24 |
122528691 ps |
| T47 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3859570588 |
|
|
Mar 05 12:55:01 PM PST 24 |
Mar 05 12:56:23 PM PST 24 |
177213038 ps |
| T48 |
/workspace/coverage/default/9.sram_ctrl_smoke.299795902 |
|
|
Mar 05 12:53:43 PM PST 24 |
Mar 05 12:53:46 PM PST 24 |
57938726 ps |
| T276 |
/workspace/coverage/default/35.sram_ctrl_executable.3313569697 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 01:00:56 PM PST 24 |
19121012007 ps |
| T277 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3937748171 |
|
|
Mar 05 12:52:41 PM PST 24 |
Mar 05 12:53:22 PM PST 24 |
133040290 ps |
| T111 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3482769051 |
|
|
Mar 05 12:53:40 PM PST 24 |
Mar 05 12:54:42 PM PST 24 |
1353410930 ps |
| T278 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2711026376 |
|
|
Mar 05 12:58:13 PM PST 24 |
Mar 05 12:58:14 PM PST 24 |
55352195 ps |
| T279 |
/workspace/coverage/default/40.sram_ctrl_regwen.1485861164 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 01:15:30 PM PST 24 |
9873278535 ps |
| T280 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2657457243 |
|
|
Mar 05 12:54:00 PM PST 24 |
Mar 05 12:54:01 PM PST 24 |
130965790 ps |
| T281 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4148009215 |
|
|
Mar 05 12:54:57 PM PST 24 |
Mar 05 12:55:01 PM PST 24 |
170194225 ps |
| T282 |
/workspace/coverage/default/29.sram_ctrl_executable.3907415251 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 01:09:09 PM PST 24 |
25079789780 ps |
| T283 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.3747715728 |
|
|
Mar 05 12:56:37 PM PST 24 |
Mar 05 12:58:25 PM PST 24 |
2157125858 ps |
| T284 |
/workspace/coverage/default/7.sram_ctrl_bijection.1127196658 |
|
|
Mar 05 12:53:32 PM PST 24 |
Mar 05 12:53:55 PM PST 24 |
712062610 ps |
| T285 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2595698582 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 01:11:11 PM PST 24 |
15076936310 ps |
| T286 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3768877793 |
|
|
Mar 05 12:57:29 PM PST 24 |
Mar 05 01:46:54 PM PST 24 |
60312789971 ps |
| T287 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2635385146 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 01:00:00 PM PST 24 |
148999855 ps |
| T288 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3837224169 |
|
|
Mar 05 12:58:42 PM PST 24 |
Mar 05 12:58:54 PM PST 24 |
376070488 ps |
| T289 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2635935123 |
|
|
Mar 05 12:54:26 PM PST 24 |
Mar 05 12:54:27 PM PST 24 |
13285914 ps |
| T290 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4149951933 |
|
|
Mar 05 12:58:04 PM PST 24 |
Mar 05 01:10:33 PM PST 24 |
7643107796 ps |
| T291 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.62273695 |
|
|
Mar 05 12:52:47 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
17454141723 ps |
| T292 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3220341285 |
|
|
Mar 05 12:54:56 PM PST 24 |
Mar 05 01:01:27 PM PST 24 |
7803286612 ps |
| T293 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1306163091 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 01:08:57 PM PST 24 |
19158485020 ps |
| T294 |
/workspace/coverage/default/6.sram_ctrl_bijection.3754601569 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:54:16 PM PST 24 |
7083990660 ps |
| T295 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3241134191 |
|
|
Mar 05 12:53:30 PM PST 24 |
Mar 05 12:54:29 PM PST 24 |
5602322515 ps |
| T296 |
/workspace/coverage/default/48.sram_ctrl_bijection.2769894218 |
|
|
Mar 05 12:58:24 PM PST 24 |
Mar 05 12:59:05 PM PST 24 |
2565182432 ps |
| T297 |
/workspace/coverage/default/40.sram_ctrl_smoke.4058244646 |
|
|
Mar 05 12:57:43 PM PST 24 |
Mar 05 12:57:52 PM PST 24 |
597957874 ps |
| T298 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3767790283 |
|
|
Mar 05 12:52:47 PM PST 24 |
Mar 05 12:54:14 PM PST 24 |
133408198 ps |
| T299 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3548680072 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:56:50 PM PST 24 |
153667384 ps |
| T300 |
/workspace/coverage/default/10.sram_ctrl_smoke.3065587100 |
|
|
Mar 05 12:53:49 PM PST 24 |
Mar 05 12:54:04 PM PST 24 |
260220495 ps |
| T301 |
/workspace/coverage/default/6.sram_ctrl_partial_access.4288090800 |
|
|
Mar 05 12:53:26 PM PST 24 |
Mar 05 12:55:35 PM PST 24 |
2523106749 ps |