Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	35141279	1			T1	71027		T2	34828		T3	8725
triple_byte_access	2202361	1			T1	1426		T2	31510		T4	34776
halfword_access	3305824	1			T1	2157		T2	46726		T4	52534
byte_access	4417067	1			T1	2929		T2	62450		T4	70524
zero_access	1113345	1			T1	694		T2	15439		T4	17530

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23036987

1

T1

39137

T2

95964

T3

4336

auto[1]

23142889

1

T1

39096

T2

94989

T3

4389

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	17519040	1			T1	35514		T2	17573		T3	4336
auto[0]	triple_byte_access	1099760	1			T1	709		T2	15742		T4	17366
auto[0]	halfword_access	1650067	1			T1	1063		T2	23555		T4	26458
auto[0]	byte_access	2207048	1			T1	1476		T2	31391		T4	35577
auto[0]	zero_access	561072	1			T1	375		T2	7703		T4	8684
auto[1]	word_access	17622239	1			T1	35513		T2	17255		T3	4389
auto[1]	triple_byte_access	1102601	1			T1	717		T2	15768		T4	17410
auto[1]	halfword_access	1655757	1			T1	1094		T2	23171		T4	26076
auto[1]	byte_access	2210019	1			T1	1453		T2	31059		T4	34947
auto[1]	zero_access	552273	1			T1	319		T2	7736		T4	8846