| T125 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1614269018 |
|
|
Mar 07 01:22:44 PM PST 24 |
Mar 07 01:24:42 PM PST 24 |
130830463 ps |
| T126 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1731753172 |
|
|
Mar 07 01:25:37 PM PST 24 |
Mar 07 01:43:53 PM PST 24 |
30026704529 ps |
| T312 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.314570800 |
|
|
Mar 07 01:26:12 PM PST 24 |
Mar 07 01:31:19 PM PST 24 |
3174305090 ps |
| T313 |
/workspace/coverage/default/1.sram_ctrl_bijection.3537385324 |
|
|
Mar 07 01:22:13 PM PST 24 |
Mar 07 01:22:46 PM PST 24 |
1049706424 ps |
| T109 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1886826840 |
|
|
Mar 07 01:27:12 PM PST 24 |
Mar 07 01:27:45 PM PST 24 |
2616028005 ps |
| T314 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3114154250 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:22:31 PM PST 24 |
196903945 ps |
| T315 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.4151944280 |
|
|
Mar 07 01:25:31 PM PST 24 |
Mar 07 01:25:32 PM PST 24 |
47981205 ps |
| T316 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1945917272 |
|
|
Mar 07 01:27:20 PM PST 24 |
Mar 07 02:09:32 PM PST 24 |
100640930943 ps |
| T317 |
/workspace/coverage/default/14.sram_ctrl_alert_test.4004923261 |
|
|
Mar 07 01:23:08 PM PST 24 |
Mar 07 01:23:09 PM PST 24 |
15933510 ps |
| T318 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.315887705 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:24:05 PM PST 24 |
2732717932 ps |
| T319 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3260836090 |
|
|
Mar 07 01:27:21 PM PST 24 |
Mar 07 01:39:46 PM PST 24 |
14489690674 ps |
| T320 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1068035029 |
|
|
Mar 07 01:22:55 PM PST 24 |
Mar 07 01:23:52 PM PST 24 |
3202279851 ps |
| T321 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1488431890 |
|
|
Mar 07 01:22:20 PM PST 24 |
Mar 07 01:22:21 PM PST 24 |
30481697 ps |
| T322 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.515724892 |
|
|
Mar 07 01:22:43 PM PST 24 |
Mar 07 01:28:51 PM PST 24 |
14511400235 ps |
| T323 |
/workspace/coverage/default/19.sram_ctrl_executable.4256185422 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:43:25 PM PST 24 |
82926154705 ps |
| T324 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.330000436 |
|
|
Mar 07 01:23:42 PM PST 24 |
Mar 07 01:26:32 PM PST 24 |
2396419378 ps |
| T325 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2578396382 |
|
|
Mar 07 01:23:53 PM PST 24 |
Mar 07 01:23:57 PM PST 24 |
63290453 ps |
| T326 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3357713734 |
|
|
Mar 07 01:25:54 PM PST 24 |
Mar 07 01:25:55 PM PST 24 |
28962095 ps |
| T327 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.203482371 |
|
|
Mar 07 01:25:00 PM PST 24 |
Mar 07 01:53:36 PM PST 24 |
19059518869 ps |
| T328 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4229863988 |
|
|
Mar 07 01:22:31 PM PST 24 |
Mar 07 01:22:36 PM PST 24 |
415738745 ps |
| T329 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2906789425 |
|
|
Mar 07 01:22:19 PM PST 24 |
Mar 07 01:22:20 PM PST 24 |
14096416 ps |
| T330 |
/workspace/coverage/default/37.sram_ctrl_alert_test.546212245 |
|
|
Mar 07 01:25:47 PM PST 24 |
Mar 07 01:25:47 PM PST 24 |
11539969 ps |
| T331 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1049561277 |
|
|
Mar 07 01:27:39 PM PST 24 |
Mar 07 01:31:18 PM PST 24 |
14734787328 ps |
| T332 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4068043655 |
|
|
Mar 07 01:22:42 PM PST 24 |
Mar 07 01:29:25 PM PST 24 |
1036880007 ps |
| T333 |
/workspace/coverage/default/13.sram_ctrl_smoke.2210505552 |
|
|
Mar 07 01:23:01 PM PST 24 |
Mar 07 01:23:16 PM PST 24 |
1797213498 ps |
| T334 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1803179547 |
|
|
Mar 07 01:25:08 PM PST 24 |
Mar 07 01:25:12 PM PST 24 |
149126720 ps |
| T335 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3408530314 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:22:33 PM PST 24 |
2665531860 ps |
| T336 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.853661582 |
|
|
Mar 07 01:24:37 PM PST 24 |
Mar 07 01:24:49 PM PST 24 |
69325712 ps |
| T337 |
/workspace/coverage/default/49.sram_ctrl_smoke.1908811550 |
|
|
Mar 07 01:27:37 PM PST 24 |
Mar 07 01:29:36 PM PST 24 |
1582159457 ps |
| T338 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1041949645 |
|
|
Mar 07 01:22:29 PM PST 24 |
Mar 07 01:39:24 PM PST 24 |
9478901798 ps |
| T339 |
/workspace/coverage/default/22.sram_ctrl_regwen.3613580318 |
|
|
Mar 07 01:23:53 PM PST 24 |
Mar 07 01:26:04 PM PST 24 |
4550112709 ps |
| T340 |
/workspace/coverage/default/18.sram_ctrl_partial_access.246039282 |
|
|
Mar 07 01:23:28 PM PST 24 |
Mar 07 01:24:19 PM PST 24 |
144459058 ps |
| T341 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3405648156 |
|
|
Mar 07 01:22:46 PM PST 24 |
Mar 07 01:22:56 PM PST 24 |
232554057 ps |
| T342 |
/workspace/coverage/default/42.sram_ctrl_executable.2333920350 |
|
|
Mar 07 01:26:29 PM PST 24 |
Mar 07 01:36:59 PM PST 24 |
7648158614 ps |
| T343 |
/workspace/coverage/default/48.sram_ctrl_executable.2403144369 |
|
|
Mar 07 01:27:40 PM PST 24 |
Mar 07 01:29:11 PM PST 24 |
485497421 ps |
| T344 |
/workspace/coverage/default/8.sram_ctrl_partial_access.105955045 |
|
|
Mar 07 01:22:41 PM PST 24 |
Mar 07 01:24:18 PM PST 24 |
1787446892 ps |
| T345 |
/workspace/coverage/default/18.sram_ctrl_smoke.3970624136 |
|
|
Mar 07 01:23:28 PM PST 24 |
Mar 07 01:24:43 PM PST 24 |
2506913525 ps |
| T346 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3526541593 |
|
|
Mar 07 01:25:17 PM PST 24 |
Mar 07 01:25:18 PM PST 24 |
18342402 ps |
| T347 |
/workspace/coverage/default/19.sram_ctrl_bijection.2213168336 |
|
|
Mar 07 01:23:38 PM PST 24 |
Mar 07 01:24:06 PM PST 24 |
5482053268 ps |
| T348 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.4048440997 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:31:16 PM PST 24 |
1278430331 ps |
| T349 |
/workspace/coverage/default/24.sram_ctrl_regwen.2719457781 |
|
|
Mar 07 01:24:06 PM PST 24 |
Mar 07 01:42:07 PM PST 24 |
3016464511 ps |
| T350 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3649060261 |
|
|
Mar 07 01:22:08 PM PST 24 |
Mar 07 01:41:09 PM PST 24 |
3917564291 ps |
| T351 |
/workspace/coverage/default/3.sram_ctrl_bijection.3876192088 |
|
|
Mar 07 01:22:20 PM PST 24 |
Mar 07 01:23:14 PM PST 24 |
12637667444 ps |
| T352 |
/workspace/coverage/default/23.sram_ctrl_alert_test.850097090 |
|
|
Mar 07 01:24:07 PM PST 24 |
Mar 07 01:24:08 PM PST 24 |
15231827 ps |
| T353 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1472609676 |
|
|
Mar 07 01:24:04 PM PST 24 |
Mar 07 01:26:41 PM PST 24 |
5760186543 ps |
| T354 |
/workspace/coverage/default/17.sram_ctrl_regwen.1494529620 |
|
|
Mar 07 01:23:29 PM PST 24 |
Mar 07 01:28:56 PM PST 24 |
5085975735 ps |
| T355 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.912755611 |
|
|
Mar 07 01:25:16 PM PST 24 |
Mar 07 01:25:30 PM PST 24 |
69983812 ps |
| T356 |
/workspace/coverage/default/45.sram_ctrl_regwen.1188155366 |
|
|
Mar 07 01:27:07 PM PST 24 |
Mar 07 01:52:35 PM PST 24 |
15964047134 ps |
| T357 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1037927344 |
|
|
Mar 07 01:23:02 PM PST 24 |
Mar 07 01:25:09 PM PST 24 |
202047539 ps |
| T358 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3148476681 |
|
|
Mar 07 01:23:28 PM PST 24 |
Mar 07 01:23:36 PM PST 24 |
643925990 ps |
| T359 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3471884937 |
|
|
Mar 07 01:22:46 PM PST 24 |
Mar 07 01:22:47 PM PST 24 |
14388323 ps |
| T360 |
/workspace/coverage/default/13.sram_ctrl_regwen.2506291102 |
|
|
Mar 07 01:23:02 PM PST 24 |
Mar 07 01:58:43 PM PST 24 |
29575953906 ps |
| T361 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3640584399 |
|
|
Mar 07 01:23:03 PM PST 24 |
Mar 07 01:31:04 PM PST 24 |
10098774520 ps |
| T362 |
/workspace/coverage/default/10.sram_ctrl_executable.669367480 |
|
|
Mar 07 01:22:52 PM PST 24 |
Mar 07 01:30:32 PM PST 24 |
1118867829 ps |
| T363 |
/workspace/coverage/default/36.sram_ctrl_smoke.334371665 |
|
|
Mar 07 01:25:29 PM PST 24 |
Mar 07 01:25:40 PM PST 24 |
269773111 ps |
| T364 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.206862091 |
|
|
Mar 07 01:22:44 PM PST 24 |
Mar 07 01:22:56 PM PST 24 |
578148862 ps |
| T365 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3748784849 |
|
|
Mar 07 01:22:17 PM PST 24 |
Mar 07 01:22:21 PM PST 24 |
118522910 ps |
| T366 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2915927499 |
|
|
Mar 07 01:26:39 PM PST 24 |
Mar 07 01:26:42 PM PST 24 |
46984111 ps |
| T367 |
/workspace/coverage/default/1.sram_ctrl_alert_test.624223085 |
|
|
Mar 07 01:22:18 PM PST 24 |
Mar 07 01:22:19 PM PST 24 |
63266249 ps |
| T368 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1368626500 |
|
|
Mar 07 01:27:37 PM PST 24 |
Mar 07 01:28:56 PM PST 24 |
519811453 ps |
| T369 |
/workspace/coverage/default/43.sram_ctrl_partial_access.848526103 |
|
|
Mar 07 01:26:39 PM PST 24 |
Mar 07 01:26:48 PM PST 24 |
1000505399 ps |
| T370 |
/workspace/coverage/default/48.sram_ctrl_alert_test.371332559 |
|
|
Mar 07 01:27:37 PM PST 24 |
Mar 07 01:27:38 PM PST 24 |
13166132 ps |
| T371 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4064099641 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:27:25 PM PST 24 |
691798708 ps |
| T372 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.4282428868 |
|
|
Mar 07 01:27:29 PM PST 24 |
Mar 07 01:27:34 PM PST 24 |
295696543 ps |
| T373 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1039417207 |
|
|
Mar 07 01:24:35 PM PST 24 |
Mar 07 01:27:29 PM PST 24 |
1817428464 ps |
| T374 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.940689866 |
|
|
Mar 07 01:23:27 PM PST 24 |
Mar 07 01:28:00 PM PST 24 |
3884676060 ps |
| T375 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3581749226 |
|
|
Mar 07 01:26:04 PM PST 24 |
Mar 07 01:27:30 PM PST 24 |
551077030 ps |
| T376 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2271760034 |
|
|
Mar 07 01:22:25 PM PST 24 |
Mar 07 01:33:36 PM PST 24 |
46564233628 ps |
| T377 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1495038409 |
|
|
Mar 07 01:22:11 PM PST 24 |
Mar 07 01:22:12 PM PST 24 |
43189692 ps |
| T378 |
/workspace/coverage/default/47.sram_ctrl_stress_all.646135594 |
|
|
Mar 07 01:27:28 PM PST 24 |
Mar 07 02:07:20 PM PST 24 |
11640456945 ps |
| T379 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.52662420 |
|
|
Mar 07 01:23:18 PM PST 24 |
Mar 07 01:23:21 PM PST 24 |
86202786 ps |
| T380 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3499242309 |
|
|
Mar 07 01:22:40 PM PST 24 |
Mar 07 01:22:50 PM PST 24 |
893385673 ps |
| T381 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2242846634 |
|
|
Mar 07 01:22:55 PM PST 24 |
Mar 07 01:28:03 PM PST 24 |
3505032189 ps |
| T382 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3731217143 |
|
|
Mar 07 01:26:40 PM PST 24 |
Mar 07 01:26:44 PM PST 24 |
67330273 ps |
| T383 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2129524020 |
|
|
Mar 07 01:27:38 PM PST 24 |
Mar 07 01:27:47 PM PST 24 |
301747069 ps |
| T384 |
/workspace/coverage/default/14.sram_ctrl_bijection.1241677029 |
|
|
Mar 07 01:23:05 PM PST 24 |
Mar 07 01:23:34 PM PST 24 |
878685300 ps |
| T385 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.763993691 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:27:29 PM PST 24 |
8936157131 ps |
| T386 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2720504778 |
|
|
Mar 07 01:25:55 PM PST 24 |
Mar 07 01:26:55 PM PST 24 |
128630724 ps |
| T387 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.3446198072 |
|
|
Mar 07 01:25:00 PM PST 24 |
Mar 07 01:25:13 PM PST 24 |
139179999 ps |
| T388 |
/workspace/coverage/default/47.sram_ctrl_executable.3956097792 |
|
|
Mar 07 01:27:29 PM PST 24 |
Mar 07 01:29:33 PM PST 24 |
15035732916 ps |
| T389 |
/workspace/coverage/default/38.sram_ctrl_executable.3440029922 |
|
|
Mar 07 01:25:55 PM PST 24 |
Mar 07 01:33:27 PM PST 24 |
5315569239 ps |
| T390 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.4206599671 |
|
|
Mar 07 01:24:47 PM PST 24 |
Mar 07 01:35:47 PM PST 24 |
9468143095 ps |
| T391 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1824136017 |
|
|
Mar 07 01:22:40 PM PST 24 |
Mar 07 03:16:40 PM PST 24 |
16464224959 ps |
| T392 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3076217686 |
|
|
Mar 07 01:23:29 PM PST 24 |
Mar 07 01:23:35 PM PST 24 |
1380460194 ps |
| T393 |
/workspace/coverage/default/22.sram_ctrl_executable.1053131513 |
|
|
Mar 07 01:23:53 PM PST 24 |
Mar 07 01:50:58 PM PST 24 |
54255499455 ps |
| T394 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2783010971 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:22:31 PM PST 24 |
155380589 ps |
| T395 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2275669236 |
|
|
Mar 07 01:26:32 PM PST 24 |
Mar 07 01:26:38 PM PST 24 |
1402587543 ps |
| T396 |
/workspace/coverage/default/4.sram_ctrl_smoke.1336309853 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:25:43 PM PST 24 |
640761804 ps |
| T397 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.569472654 |
|
|
Mar 07 01:23:24 PM PST 24 |
Mar 07 01:23:43 PM PST 24 |
279924414 ps |
| T398 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2000740007 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:31:39 PM PST 24 |
3348098926 ps |
| T399 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1337596346 |
|
|
Mar 07 01:22:50 PM PST 24 |
Mar 07 01:28:14 PM PST 24 |
4670029984 ps |
| T400 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1506848383 |
|
|
Mar 07 01:22:51 PM PST 24 |
Mar 07 01:23:19 PM PST 24 |
90949173 ps |
| T401 |
/workspace/coverage/default/15.sram_ctrl_regwen.359722505 |
|
|
Mar 07 01:23:09 PM PST 24 |
Mar 07 01:29:55 PM PST 24 |
4520824859 ps |
| T402 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3901269360 |
|
|
Mar 07 01:22:21 PM PST 24 |
Mar 07 01:22:34 PM PST 24 |
7158217951 ps |
| T403 |
/workspace/coverage/default/35.sram_ctrl_regwen.3229487103 |
|
|
Mar 07 01:25:36 PM PST 24 |
Mar 07 01:25:51 PM PST 24 |
3156975052 ps |
| T404 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.4105779429 |
|
|
Mar 07 01:27:49 PM PST 24 |
Mar 07 01:27:53 PM PST 24 |
148664175 ps |
| T405 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3185993668 |
|
|
Mar 07 01:23:15 PM PST 24 |
Mar 07 01:28:36 PM PST 24 |
17708269001 ps |
| T406 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2269511040 |
|
|
Mar 07 01:22:41 PM PST 24 |
Mar 07 01:23:02 PM PST 24 |
174080153 ps |
| T407 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3350340668 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:23:17 PM PST 24 |
338108725 ps |
| T408 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1452080303 |
|
|
Mar 07 01:24:09 PM PST 24 |
Mar 07 01:26:03 PM PST 24 |
588087457 ps |
| T409 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1480459765 |
|
|
Mar 07 01:26:12 PM PST 24 |
Mar 07 02:08:39 PM PST 24 |
80478451825 ps |
| T410 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3270925906 |
|
|
Mar 07 01:22:58 PM PST 24 |
Mar 07 01:22:58 PM PST 24 |
49454106 ps |
| T411 |
/workspace/coverage/default/46.sram_ctrl_partial_access.328282809 |
|
|
Mar 07 01:27:19 PM PST 24 |
Mar 07 01:28:16 PM PST 24 |
163427972 ps |
| T412 |
/workspace/coverage/default/26.sram_ctrl_smoke.3091277473 |
|
|
Mar 07 01:24:16 PM PST 24 |
Mar 07 01:24:19 PM PST 24 |
626090149 ps |
| T413 |
/workspace/coverage/default/40.sram_ctrl_stress_all.4038178382 |
|
|
Mar 07 01:26:23 PM PST 24 |
Mar 07 02:29:46 PM PST 24 |
277255703175 ps |
| T414 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1329201306 |
|
|
Mar 07 01:22:52 PM PST 24 |
Mar 07 01:22:53 PM PST 24 |
22962946 ps |
| T415 |
/workspace/coverage/default/46.sram_ctrl_bijection.1770825634 |
|
|
Mar 07 01:27:20 PM PST 24 |
Mar 07 01:27:49 PM PST 24 |
536964532 ps |
| T416 |
/workspace/coverage/default/43.sram_ctrl_stress_all.504838478 |
|
|
Mar 07 01:26:49 PM PST 24 |
Mar 07 02:01:18 PM PST 24 |
36775263943 ps |
| T417 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2632355474 |
|
|
Mar 07 01:22:18 PM PST 24 |
Mar 07 01:22:34 PM PST 24 |
1180795829 ps |
| T418 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.516250181 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:25:38 PM PST 24 |
2358097658 ps |
| T419 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.4159094517 |
|
|
Mar 07 01:25:58 PM PST 24 |
Mar 07 01:31:33 PM PST 24 |
13051608844 ps |
| T420 |
/workspace/coverage/default/29.sram_ctrl_regwen.3484767886 |
|
|
Mar 07 01:24:47 PM PST 24 |
Mar 07 01:38:53 PM PST 24 |
4028984785 ps |
| T421 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3269196280 |
|
|
Mar 07 01:22:58 PM PST 24 |
Mar 07 01:28:57 PM PST 24 |
3555593799 ps |
| T422 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.634572090 |
|
|
Mar 07 01:25:39 PM PST 24 |
Mar 07 01:25:44 PM PST 24 |
271364762 ps |
| T423 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2360895051 |
|
|
Mar 07 01:23:52 PM PST 24 |
Mar 07 01:26:57 PM PST 24 |
3887112093 ps |
| T424 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3510420037 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:23:50 PM PST 24 |
478562309 ps |
| T425 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2508467048 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:22:28 PM PST 24 |
76240981 ps |
| T426 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1353024006 |
|
|
Mar 07 01:24:16 PM PST 24 |
Mar 07 01:39:57 PM PST 24 |
3129856124 ps |
| T427 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1763694458 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:22:54 PM PST 24 |
92735333 ps |
| T110 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.526411956 |
|
|
Mar 07 01:22:54 PM PST 24 |
Mar 07 01:23:04 PM PST 24 |
1502948331 ps |
| T428 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3735202339 |
|
|
Mar 07 01:22:26 PM PST 24 |
Mar 07 01:23:08 PM PST 24 |
127278502 ps |
| T429 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2623266827 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:22:27 PM PST 24 |
903731687 ps |
| T430 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2110912825 |
|
|
Mar 07 01:24:17 PM PST 24 |
Mar 07 01:52:11 PM PST 24 |
14155054086 ps |
| T431 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1017389317 |
|
|
Mar 07 01:22:55 PM PST 24 |
Mar 07 01:23:01 PM PST 24 |
671633435 ps |
| T432 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1030151230 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:26:55 PM PST 24 |
8818344983 ps |
| T433 |
/workspace/coverage/default/48.sram_ctrl_bijection.1192221555 |
|
|
Mar 07 01:27:29 PM PST 24 |
Mar 07 01:28:40 PM PST 24 |
3187209364 ps |
| T434 |
/workspace/coverage/default/0.sram_ctrl_regwen.99050374 |
|
|
Mar 07 01:22:12 PM PST 24 |
Mar 07 01:44:25 PM PST 24 |
5431687476 ps |
| T435 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3996916240 |
|
|
Mar 07 01:26:05 PM PST 24 |
Mar 07 01:26:16 PM PST 24 |
1876754350 ps |
| T436 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1060971873 |
|
|
Mar 07 01:27:50 PM PST 24 |
Mar 07 01:28:06 PM PST 24 |
2023487597 ps |
| T437 |
/workspace/coverage/default/38.sram_ctrl_partial_access.820375743 |
|
|
Mar 07 01:25:54 PM PST 24 |
Mar 07 01:26:07 PM PST 24 |
250966913 ps |
| T438 |
/workspace/coverage/default/40.sram_ctrl_executable.2851701754 |
|
|
Mar 07 01:26:15 PM PST 24 |
Mar 07 01:40:12 PM PST 24 |
3630086134 ps |
| T439 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.4219373007 |
|
|
Mar 07 01:24:38 PM PST 24 |
Mar 07 01:37:29 PM PST 24 |
12758837512 ps |
| T440 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2311792567 |
|
|
Mar 07 01:24:16 PM PST 24 |
Mar 07 01:30:55 PM PST 24 |
74485581735 ps |
| T441 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2481738789 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:23:58 PM PST 24 |
269155449 ps |
| T442 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2677298869 |
|
|
Mar 07 01:24:06 PM PST 24 |
Mar 07 01:25:38 PM PST 24 |
10277183657 ps |
| T443 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3677452738 |
|
|
Mar 07 01:26:17 PM PST 24 |
Mar 07 01:26:22 PM PST 24 |
306329914 ps |
| T444 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3165684392 |
|
|
Mar 07 01:27:48 PM PST 24 |
Mar 07 01:28:35 PM PST 24 |
403862671 ps |
| T445 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3718221346 |
|
|
Mar 07 01:22:40 PM PST 24 |
Mar 07 01:40:21 PM PST 24 |
8645098386 ps |
| T446 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2710645377 |
|
|
Mar 07 01:27:02 PM PST 24 |
Mar 07 01:27:17 PM PST 24 |
1499456227 ps |
| T447 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1674087780 |
|
|
Mar 07 01:24:05 PM PST 24 |
Mar 07 01:24:05 PM PST 24 |
60815906 ps |
| T448 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2958975728 |
|
|
Mar 07 01:23:04 PM PST 24 |
Mar 07 01:25:39 PM PST 24 |
229584704 ps |
| T449 |
/workspace/coverage/default/34.sram_ctrl_executable.568239767 |
|
|
Mar 07 01:25:30 PM PST 24 |
Mar 07 01:45:57 PM PST 24 |
3303363713 ps |
| T450 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.692151727 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:30:12 PM PST 24 |
15352144653 ps |
| T451 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3560461299 |
|
|
Mar 07 01:23:27 PM PST 24 |
Mar 07 01:23:28 PM PST 24 |
29044917 ps |
| T452 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3378689521 |
|
|
Mar 07 01:23:24 PM PST 24 |
Mar 07 01:27:47 PM PST 24 |
8826699672 ps |
| T453 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1061095291 |
|
|
Mar 07 01:25:11 PM PST 24 |
Mar 07 01:26:21 PM PST 24 |
1155919563 ps |
| T454 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4041350540 |
|
|
Mar 07 01:23:16 PM PST 24 |
Mar 07 01:29:23 PM PST 24 |
26275396925 ps |
| T455 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1646497818 |
|
|
Mar 07 01:25:36 PM PST 24 |
Mar 07 01:25:41 PM PST 24 |
170516069 ps |
| T456 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1808252249 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:22:55 PM PST 24 |
324392386 ps |
| T457 |
/workspace/coverage/default/16.sram_ctrl_bijection.4017946734 |
|
|
Mar 07 01:23:15 PM PST 24 |
Mar 07 01:23:43 PM PST 24 |
3650116687 ps |
| T458 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.515506360 |
|
|
Mar 07 01:25:08 PM PST 24 |
Mar 07 01:25:21 PM PST 24 |
807570070 ps |
| T459 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3239776546 |
|
|
Mar 07 01:23:04 PM PST 24 |
Mar 07 02:25:02 PM PST 24 |
209727455974 ps |
| T111 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3600716676 |
|
|
Mar 07 01:25:36 PM PST 24 |
Mar 07 01:28:02 PM PST 24 |
11732421703 ps |
| T460 |
/workspace/coverage/default/32.sram_ctrl_executable.4072474345 |
|
|
Mar 07 01:25:05 PM PST 24 |
Mar 07 01:51:40 PM PST 24 |
105941823863 ps |
| T461 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1216510803 |
|
|
Mar 07 01:23:40 PM PST 24 |
Mar 07 01:23:41 PM PST 24 |
30770667 ps |
| T462 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.330647376 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:24:36 PM PST 24 |
139928116 ps |
| T463 |
/workspace/coverage/default/42.sram_ctrl_regwen.2282712014 |
|
|
Mar 07 01:26:38 PM PST 24 |
Mar 07 01:39:45 PM PST 24 |
6710944523 ps |
| T464 |
/workspace/coverage/default/43.sram_ctrl_bijection.2619468458 |
|
|
Mar 07 01:26:44 PM PST 24 |
Mar 07 01:27:44 PM PST 24 |
3691343084 ps |
| T465 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.4155985829 |
|
|
Mar 07 01:24:27 PM PST 24 |
Mar 07 01:24:30 PM PST 24 |
275250548 ps |
| T466 |
/workspace/coverage/default/0.sram_ctrl_smoke.1107969568 |
|
|
Mar 07 01:22:08 PM PST 24 |
Mar 07 01:22:13 PM PST 24 |
125568213 ps |
| T467 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.339707917 |
|
|
Mar 07 01:25:19 PM PST 24 |
Mar 07 01:43:15 PM PST 24 |
4799179006 ps |
| T468 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4199148485 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:26:56 PM PST 24 |
785876299 ps |
| T469 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.99072179 |
|
|
Mar 07 01:23:08 PM PST 24 |
Mar 07 01:23:14 PM PST 24 |
1317780909 ps |
| T470 |
/workspace/coverage/default/31.sram_ctrl_regwen.4097890232 |
|
|
Mar 07 01:25:08 PM PST 24 |
Mar 07 01:41:26 PM PST 24 |
43693140903 ps |
| T471 |
/workspace/coverage/default/7.sram_ctrl_alert_test.353477408 |
|
|
Mar 07 01:22:46 PM PST 24 |
Mar 07 01:22:47 PM PST 24 |
43091796 ps |
| T472 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2595425964 |
|
|
Mar 07 01:22:57 PM PST 24 |
Mar 07 01:34:36 PM PST 24 |
8463115473 ps |
| T473 |
/workspace/coverage/default/43.sram_ctrl_executable.923334330 |
|
|
Mar 07 01:26:49 PM PST 24 |
Mar 07 01:41:52 PM PST 24 |
95640938353 ps |
| T474 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.925024976 |
|
|
Mar 07 01:22:43 PM PST 24 |
Mar 07 01:27:23 PM PST 24 |
11659670735 ps |
| T475 |
/workspace/coverage/default/46.sram_ctrl_executable.3257496141 |
|
|
Mar 07 01:27:19 PM PST 24 |
Mar 07 01:37:47 PM PST 24 |
1932568363 ps |
| T476 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3125872617 |
|
|
Mar 07 01:24:38 PM PST 24 |
Mar 07 01:35:12 PM PST 24 |
7052636537 ps |
| T477 |
/workspace/coverage/default/36.sram_ctrl_regwen.2666645074 |
|
|
Mar 07 01:25:37 PM PST 24 |
Mar 07 01:37:32 PM PST 24 |
73043092387 ps |
| T478 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2717668945 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:28:23 PM PST 24 |
1384320345 ps |
| T479 |
/workspace/coverage/default/9.sram_ctrl_alert_test.759592790 |
|
|
Mar 07 01:22:57 PM PST 24 |
Mar 07 01:22:58 PM PST 24 |
12134672 ps |
| T480 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.197297104 |
|
|
Mar 07 01:27:29 PM PST 24 |
Mar 07 01:27:36 PM PST 24 |
368857456 ps |
| T481 |
/workspace/coverage/default/22.sram_ctrl_bijection.137500135 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:24:36 PM PST 24 |
2548246947 ps |
| T482 |
/workspace/coverage/default/45.sram_ctrl_partial_access.946018108 |
|
|
Mar 07 01:27:11 PM PST 24 |
Mar 07 01:27:18 PM PST 24 |
172446486 ps |
| T483 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2417803122 |
|
|
Mar 07 01:24:03 PM PST 24 |
Mar 07 01:53:01 PM PST 24 |
42712362199 ps |
| T484 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.4160506309 |
|
|
Mar 07 01:23:25 PM PST 24 |
Mar 07 01:26:02 PM PST 24 |
7477048469 ps |
| T112 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3603628443 |
|
|
Mar 07 01:23:06 PM PST 24 |
Mar 07 01:24:48 PM PST 24 |
5331894408 ps |
| T485 |
/workspace/coverage/default/40.sram_ctrl_regwen.965572716 |
|
|
Mar 07 01:26:13 PM PST 24 |
Mar 07 01:28:23 PM PST 24 |
2401779035 ps |
| T486 |
/workspace/coverage/default/16.sram_ctrl_regwen.4129272718 |
|
|
Mar 07 01:23:19 PM PST 24 |
Mar 07 01:31:26 PM PST 24 |
33361986307 ps |
| T487 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2779179969 |
|
|
Mar 07 01:27:28 PM PST 24 |
Mar 07 01:27:42 PM PST 24 |
70118560 ps |
| T488 |
/workspace/coverage/default/15.sram_ctrl_executable.3557124150 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:27:44 PM PST 24 |
3742404143 ps |
| T489 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2658447214 |
|
|
Mar 07 01:26:16 PM PST 24 |
Mar 07 01:26:17 PM PST 24 |
51183349 ps |
| T490 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.905818915 |
|
|
Mar 07 01:26:37 PM PST 24 |
Mar 07 01:26:43 PM PST 24 |
442207306 ps |
| T491 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1780481904 |
|
|
Mar 07 01:22:54 PM PST 24 |
Mar 07 01:26:29 PM PST 24 |
5231518757 ps |
| T492 |
/workspace/coverage/default/6.sram_ctrl_bijection.971478528 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:22:44 PM PST 24 |
3086684397 ps |
| T493 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2752648845 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:23:46 PM PST 24 |
176151078 ps |
| T494 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2392367014 |
|
|
Mar 07 01:25:00 PM PST 24 |
Mar 07 02:30:35 PM PST 24 |
37532718275 ps |
| T495 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1603515288 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:23:33 PM PST 24 |
387847711 ps |
| T496 |
/workspace/coverage/default/6.sram_ctrl_smoke.896283017 |
|
|
Mar 07 01:22:30 PM PST 24 |
Mar 07 01:22:40 PM PST 24 |
461222897 ps |
| T497 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2123917252 |
|
|
Mar 07 01:24:52 PM PST 24 |
Mar 07 01:24:57 PM PST 24 |
555924244 ps |
| T498 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.77708820 |
|
|
Mar 07 01:22:11 PM PST 24 |
Mar 07 01:39:29 PM PST 24 |
3731757270 ps |
| T499 |
/workspace/coverage/default/27.sram_ctrl_executable.385094603 |
|
|
Mar 07 01:24:38 PM PST 24 |
Mar 07 01:27:20 PM PST 24 |
2060210829 ps |
| T500 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2213923095 |
|
|
Mar 07 01:23:29 PM PST 24 |
Mar 07 01:23:29 PM PST 24 |
14605488 ps |
| T501 |
/workspace/coverage/default/44.sram_ctrl_smoke.1728347718 |
|
|
Mar 07 01:27:02 PM PST 24 |
Mar 07 01:27:09 PM PST 24 |
374238214 ps |
| T502 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1936320900 |
|
|
Mar 07 01:22:18 PM PST 24 |
Mar 07 02:28:22 PM PST 24 |
52353175443 ps |
| T503 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3665053370 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:22:24 PM PST 24 |
50614321 ps |
| T504 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1439501128 |
|
|
Mar 07 01:24:07 PM PST 24 |
Mar 07 01:26:01 PM PST 24 |
1085071762 ps |
| T505 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3515860033 |
|
|
Mar 07 01:23:26 PM PST 24 |
Mar 07 01:25:00 PM PST 24 |
11896354510 ps |
| T506 |
/workspace/coverage/default/31.sram_ctrl_executable.2831123386 |
|
|
Mar 07 01:25:12 PM PST 24 |
Mar 07 01:37:50 PM PST 24 |
12492975131 ps |
| T507 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1167900956 |
|
|
Mar 07 01:23:00 PM PST 24 |
Mar 07 02:48:58 PM PST 24 |
18842561637 ps |
| T508 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3331840867 |
|
|
Mar 07 01:27:37 PM PST 24 |
Mar 07 01:27:38 PM PST 24 |
30668310 ps |
| T509 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.709318911 |
|
|
Mar 07 01:26:24 PM PST 24 |
Mar 07 01:29:29 PM PST 24 |
7636107569 ps |
| T510 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1268962954 |
|
|
Mar 07 01:22:57 PM PST 24 |
Mar 07 01:23:00 PM PST 24 |
435303118 ps |
| T511 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2588358557 |
|
|
Mar 07 01:26:03 PM PST 24 |
Mar 07 01:26:03 PM PST 24 |
74930587 ps |
| T512 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3223016947 |
|
|
Mar 07 01:23:15 PM PST 24 |
Mar 07 01:23:21 PM PST 24 |
929695984 ps |
| T513 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3524885609 |
|
|
Mar 07 01:23:28 PM PST 24 |
Mar 07 01:23:34 PM PST 24 |
896620277 ps |
| T514 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.193956559 |
|
|
Mar 07 01:26:34 PM PST 24 |
Mar 07 01:33:03 PM PST 24 |
8271939929 ps |
| T515 |
/workspace/coverage/default/28.sram_ctrl_smoke.1398721157 |
|
|
Mar 07 01:24:37 PM PST 24 |
Mar 07 01:25:24 PM PST 24 |
109959967 ps |
| T516 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3016608113 |
|
|
Mar 07 01:23:55 PM PST 24 |
Mar 07 01:23:56 PM PST 24 |
32932835 ps |
| T517 |
/workspace/coverage/default/0.sram_ctrl_bijection.331340073 |
|
|
Mar 07 01:22:14 PM PST 24 |
Mar 07 01:23:15 PM PST 24 |
7962474435 ps |
| T113 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1839540515 |
|
|
Mar 07 01:27:46 PM PST 24 |
Mar 07 01:28:25 PM PST 24 |
6741089140 ps |
| T518 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1570379207 |
|
|
Mar 07 01:23:06 PM PST 24 |
Mar 07 01:23:29 PM PST 24 |
1518339727 ps |
| T519 |
/workspace/coverage/default/2.sram_ctrl_regwen.4158978756 |
|
|
Mar 07 01:22:18 PM PST 24 |
Mar 07 01:41:42 PM PST 24 |
2219199380 ps |
| T520 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2307597998 |
|
|
Mar 07 01:27:38 PM PST 24 |
Mar 07 01:49:45 PM PST 24 |
13758772697 ps |
| T521 |
/workspace/coverage/default/39.sram_ctrl_smoke.1851661524 |
|
|
Mar 07 01:26:06 PM PST 24 |
Mar 07 01:26:17 PM PST 24 |
393444879 ps |
| T522 |
/workspace/coverage/default/0.sram_ctrl_executable.3371391687 |
|
|
Mar 07 01:22:07 PM PST 24 |
Mar 07 01:34:29 PM PST 24 |
42918312164 ps |
| T523 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.58544997 |
|
|
Mar 07 01:27:20 PM PST 24 |
Mar 07 01:29:32 PM PST 24 |
5484841323 ps |
| T524 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2251299364 |
|
|
Mar 07 01:27:29 PM PST 24 |
Mar 07 01:44:12 PM PST 24 |
10458197266 ps |
| T525 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.323359456 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:34:33 PM PST 24 |
9497981852 ps |
| T526 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.940081225 |
|
|
Mar 07 01:23:28 PM PST 24 |
Mar 07 01:43:37 PM PST 24 |
4801251155 ps |
| T527 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2511099333 |
|
|
Mar 07 01:23:52 PM PST 24 |
Mar 07 01:23:52 PM PST 24 |
23971424 ps |
| T528 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.4113942733 |
|
|
Mar 07 01:24:02 PM PST 24 |
Mar 07 01:24:07 PM PST 24 |
74694409 ps |
| T529 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1617757120 |
|
|
Mar 07 01:26:38 PM PST 24 |
Mar 07 01:27:08 PM PST 24 |
2901223733 ps |
| T530 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1453448157 |
|
|
Mar 07 01:24:15 PM PST 24 |
Mar 07 01:31:09 PM PST 24 |
4682760868 ps |
| T531 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1383256855 |
|
|
Mar 07 01:22:13 PM PST 24 |
Mar 07 01:22:15 PM PST 24 |
360098551 ps |
| T532 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1899225785 |
|
|
Mar 07 01:24:57 PM PST 24 |
Mar 07 01:24:58 PM PST 24 |
21956303 ps |
| T533 |
/workspace/coverage/default/20.sram_ctrl_smoke.2914900475 |
|
|
Mar 07 01:23:39 PM PST 24 |
Mar 07 01:23:52 PM PST 24 |
471127326 ps |
| T534 |
/workspace/coverage/default/23.sram_ctrl_bijection.3147503861 |
|
|
Mar 07 01:24:09 PM PST 24 |
Mar 07 01:25:05 PM PST 24 |
918309640 ps |
| T535 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3960094139 |
|
|
Mar 07 01:25:30 PM PST 24 |
Mar 07 01:25:32 PM PST 24 |
189894550 ps |
| T536 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.618440846 |
|
|
Mar 07 01:25:32 PM PST 24 |
Mar 07 01:25:33 PM PST 24 |
72974738 ps |
| T537 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.188580578 |
|
|
Mar 07 01:26:23 PM PST 24 |
Mar 07 01:28:27 PM PST 24 |
442380440 ps |
| T538 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2165149519 |
|
|
Mar 07 01:27:30 PM PST 24 |
Mar 07 01:31:35 PM PST 24 |
10383251949 ps |
| T539 |
/workspace/coverage/default/30.sram_ctrl_executable.2867284985 |
|
|
Mar 07 01:24:59 PM PST 24 |
Mar 07 01:42:29 PM PST 24 |
18348494149 ps |
| T540 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.883023219 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:30:18 PM PST 24 |
65566488592 ps |
| T541 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3786220439 |
|
|
Mar 07 01:24:22 PM PST 24 |
Mar 07 01:24:41 PM PST 24 |
992023655 ps |
| T114 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3073065208 |
|
|
Mar 07 01:26:39 PM PST 24 |
Mar 07 01:30:41 PM PST 24 |
3868181885 ps |
| T542 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2222191972 |
|
|
Mar 07 01:22:42 PM PST 24 |
Mar 07 01:22:48 PM PST 24 |
359079906 ps |
| T543 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1164297209 |
|
|
Mar 07 01:27:02 PM PST 24 |
Mar 07 01:27:07 PM PST 24 |
957041147 ps |
| T544 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3540211732 |
|
|
Mar 07 01:23:27 PM PST 24 |
Mar 07 01:25:06 PM PST 24 |
4162796973 ps |
| T545 |
/workspace/coverage/default/20.sram_ctrl_bijection.3047126781 |
|
|
Mar 07 01:23:40 PM PST 24 |
Mar 07 01:24:28 PM PST 24 |
6847518076 ps |
| T546 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.256879120 |
|
|
Mar 07 01:24:58 PM PST 24 |
Mar 07 01:33:08 PM PST 24 |
2269777156 ps |
| T547 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.4116703976 |
|
|
Mar 07 01:26:16 PM PST 24 |
Mar 07 01:26:25 PM PST 24 |
673205449 ps |
| T548 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1263000512 |
|
|
Mar 07 01:23:55 PM PST 24 |
Mar 07 01:25:07 PM PST 24 |
273917471 ps |
| T549 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.4218065467 |
|
|
Mar 07 01:26:24 PM PST 24 |
Mar 07 01:26:29 PM PST 24 |
282655465 ps |
| T550 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.4032262703 |
|
|
Mar 07 01:24:36 PM PST 24 |
Mar 07 01:24:37 PM PST 24 |
31963062 ps |
| T551 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.741815793 |
|
|
Mar 07 01:22:54 PM PST 24 |
Mar 07 01:23:05 PM PST 24 |
963982643 ps |
| T552 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1106569736 |
|
|
Mar 07 01:23:39 PM PST 24 |
Mar 07 01:35:51 PM PST 24 |
9975875384 ps |
| T553 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2060594089 |
|
|
Mar 07 01:22:21 PM PST 24 |
Mar 07 01:22:46 PM PST 24 |
217409110 ps |