| T798 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1724874266 |
|
|
Mar 07 01:23:09 PM PST 24 |
Mar 07 01:23:15 PM PST 24 |
315831185 ps |
| T799 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1107324462 |
|
|
Mar 07 01:27:08 PM PST 24 |
Mar 07 01:27:51 PM PST 24 |
924976595 ps |
| T800 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2529972291 |
|
|
Mar 07 01:24:03 PM PST 24 |
Mar 07 01:27:15 PM PST 24 |
5035481818 ps |
| T801 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.268693323 |
|
|
Mar 07 01:25:56 PM PST 24 |
Mar 07 01:26:06 PM PST 24 |
1326613531 ps |
| T802 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1192802289 |
|
|
Mar 07 01:22:08 PM PST 24 |
Mar 07 01:32:38 PM PST 24 |
14057625619 ps |
| T803 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.653500507 |
|
|
Mar 07 01:24:08 PM PST 24 |
Mar 07 01:24:09 PM PST 24 |
49608850 ps |
| T804 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2069371476 |
|
|
Mar 07 01:25:29 PM PST 24 |
Mar 07 01:29:53 PM PST 24 |
3930305141 ps |
| T805 |
/workspace/coverage/default/48.sram_ctrl_regwen.1913948581 |
|
|
Mar 07 01:27:38 PM PST 24 |
Mar 07 01:45:37 PM PST 24 |
9071969183 ps |
| T806 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1638497181 |
|
|
Mar 07 01:22:08 PM PST 24 |
Mar 07 01:22:09 PM PST 24 |
47201664 ps |
| T807 |
/workspace/coverage/default/44.sram_ctrl_partial_access.990676559 |
|
|
Mar 07 01:26:59 PM PST 24 |
Mar 07 01:27:02 PM PST 24 |
753380612 ps |
| T808 |
/workspace/coverage/default/4.sram_ctrl_regwen.1903329339 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:28:09 PM PST 24 |
31686042383 ps |
| T809 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2414262818 |
|
|
Mar 07 01:27:18 PM PST 24 |
Mar 07 01:32:11 PM PST 24 |
12387741186 ps |
| T810 |
/workspace/coverage/default/35.sram_ctrl_bijection.4063723944 |
|
|
Mar 07 01:25:26 PM PST 24 |
Mar 07 01:26:39 PM PST 24 |
3475813589 ps |
| T811 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3906286324 |
|
|
Mar 07 01:24:07 PM PST 24 |
Mar 07 01:40:40 PM PST 24 |
2802485875 ps |
| T812 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3093095775 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:27:23 PM PST 24 |
8299854188 ps |
| T813 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3603218830 |
|
|
Mar 07 01:22:52 PM PST 24 |
Mar 07 01:24:54 PM PST 24 |
136350049 ps |
| T814 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.4037687210 |
|
|
Mar 07 01:24:46 PM PST 24 |
Mar 07 01:37:02 PM PST 24 |
6615499125 ps |
| T815 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2915985123 |
|
|
Mar 07 01:25:08 PM PST 24 |
Mar 07 01:33:34 PM PST 24 |
1057007996 ps |
| T816 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2469192965 |
|
|
Mar 07 01:25:19 PM PST 24 |
Mar 07 01:28:32 PM PST 24 |
3989102258 ps |
| T817 |
/workspace/coverage/default/29.sram_ctrl_smoke.2903815146 |
|
|
Mar 07 01:24:39 PM PST 24 |
Mar 07 01:25:21 PM PST 24 |
593321436 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.740171810 |
|
|
Mar 07 01:22:58 PM PST 24 |
Mar 07 01:23:48 PM PST 24 |
110011201 ps |
| T819 |
/workspace/coverage/default/3.sram_ctrl_regwen.836701026 |
|
|
Mar 07 01:22:21 PM PST 24 |
Mar 07 01:22:48 PM PST 24 |
923041045 ps |
| T820 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.4096286177 |
|
|
Mar 07 01:22:41 PM PST 24 |
Mar 07 01:23:15 PM PST 24 |
172316836 ps |
| T821 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2851169081 |
|
|
Mar 07 01:25:43 PM PST 24 |
Mar 07 01:28:21 PM PST 24 |
594298402 ps |
| T822 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.938052920 |
|
|
Mar 07 01:25:10 PM PST 24 |
Mar 07 01:26:25 PM PST 24 |
106712516 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_bijection.2003856222 |
|
|
Mar 07 01:22:41 PM PST 24 |
Mar 07 01:23:02 PM PST 24 |
4532646412 ps |
| T824 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2207670825 |
|
|
Mar 07 01:24:06 PM PST 24 |
Mar 07 01:24:07 PM PST 24 |
19389063 ps |
| T825 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3774872135 |
|
|
Mar 07 01:22:53 PM PST 24 |
Mar 07 01:26:07 PM PST 24 |
7800629843 ps |
| T826 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.781585606 |
|
|
Mar 07 01:23:39 PM PST 24 |
Mar 07 01:47:00 PM PST 24 |
15702014083 ps |
| T827 |
/workspace/coverage/default/23.sram_ctrl_regwen.3285344795 |
|
|
Mar 07 01:24:06 PM PST 24 |
Mar 07 01:35:00 PM PST 24 |
92807577381 ps |
| T828 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.408816977 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:27:01 PM PST 24 |
242748824 ps |
| T829 |
/workspace/coverage/default/18.sram_ctrl_regwen.545047439 |
|
|
Mar 07 01:23:27 PM PST 24 |
Mar 07 01:35:26 PM PST 24 |
11215799540 ps |
| T830 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3517960480 |
|
|
Mar 07 01:22:14 PM PST 24 |
Mar 07 01:22:15 PM PST 24 |
80204064 ps |
| T831 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1883124022 |
|
|
Mar 07 01:24:16 PM PST 24 |
Mar 07 01:30:12 PM PST 24 |
7560588828 ps |
| T832 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2324540957 |
|
|
Mar 07 01:22:19 PM PST 24 |
Mar 07 01:24:37 PM PST 24 |
312742366 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_regwen.3775306157 |
|
|
Mar 07 01:25:56 PM PST 24 |
Mar 07 01:54:23 PM PST 24 |
42846212951 ps |
| T834 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1233471120 |
|
|
Mar 07 01:27:09 PM PST 24 |
Mar 07 01:38:54 PM PST 24 |
3521307118 ps |
| T835 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2462969015 |
|
|
Mar 07 01:26:31 PM PST 24 |
Mar 07 01:26:44 PM PST 24 |
183437132 ps |
| T836 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1849044963 |
|
|
Mar 07 01:26:22 PM PST 24 |
Mar 07 01:28:55 PM PST 24 |
360241775 ps |
| T837 |
/workspace/coverage/default/21.sram_ctrl_regwen.1210918559 |
|
|
Mar 07 01:23:53 PM PST 24 |
Mar 07 01:34:05 PM PST 24 |
37649909904 ps |
| T838 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2102588722 |
|
|
Mar 07 01:25:17 PM PST 24 |
Mar 07 01:35:25 PM PST 24 |
11480934679 ps |
| T839 |
/workspace/coverage/default/39.sram_ctrl_regwen.3748997541 |
|
|
Mar 07 01:26:04 PM PST 24 |
Mar 07 01:35:29 PM PST 24 |
8691476390 ps |
| T840 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.756217253 |
|
|
Mar 07 01:23:04 PM PST 24 |
Mar 07 01:27:25 PM PST 24 |
5436179040 ps |
| T841 |
/workspace/coverage/default/45.sram_ctrl_bijection.1623669680 |
|
|
Mar 07 01:27:10 PM PST 24 |
Mar 07 01:28:25 PM PST 24 |
7232108227 ps |
| T842 |
/workspace/coverage/default/38.sram_ctrl_stress_all.384463805 |
|
|
Mar 07 01:26:05 PM PST 24 |
Mar 07 01:50:19 PM PST 24 |
28480482985 ps |
| T843 |
/workspace/coverage/default/46.sram_ctrl_regwen.904699287 |
|
|
Mar 07 01:27:19 PM PST 24 |
Mar 07 01:35:10 PM PST 24 |
5527507162 ps |
| T844 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2095447252 |
|
|
Mar 07 01:26:26 PM PST 24 |
Mar 07 01:27:36 PM PST 24 |
128908638 ps |
| T31 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1276173201 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:22:25 PM PST 24 |
851810335 ps |
| T845 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3182817701 |
|
|
Mar 07 01:27:38 PM PST 24 |
Mar 07 01:27:42 PM PST 24 |
427469876 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_regwen.118490449 |
|
|
Mar 07 01:22:50 PM PST 24 |
Mar 07 01:28:38 PM PST 24 |
1274752829 ps |
| T847 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2744545988 |
|
|
Mar 07 01:23:39 PM PST 24 |
Mar 07 01:23:49 PM PST 24 |
534225942 ps |
| T848 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1498591772 |
|
|
Mar 07 01:27:47 PM PST 24 |
Mar 07 01:34:02 PM PST 24 |
21327421960 ps |
| T849 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2055885831 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:23:15 PM PST 24 |
81971862 ps |
| T850 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2348883730 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:26:54 PM PST 24 |
9454078631 ps |
| T851 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1973839468 |
|
|
Mar 07 01:27:09 PM PST 24 |
Mar 07 01:27:11 PM PST 24 |
100507883 ps |
| T852 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1987049102 |
|
|
Mar 07 01:25:47 PM PST 24 |
Mar 07 01:26:03 PM PST 24 |
83278622 ps |
| T853 |
/workspace/coverage/default/32.sram_ctrl_bijection.1556586048 |
|
|
Mar 07 01:25:08 PM PST 24 |
Mar 07 01:25:43 PM PST 24 |
9041957768 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2308350799 |
|
|
Mar 07 01:26:48 PM PST 24 |
Mar 07 01:26:54 PM PST 24 |
311756908 ps |
| T855 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3135069453 |
|
|
Mar 07 01:22:29 PM PST 24 |
Mar 07 01:27:26 PM PST 24 |
15002983047 ps |
| T856 |
/workspace/coverage/default/23.sram_ctrl_smoke.1543516335 |
|
|
Mar 07 01:24:05 PM PST 24 |
Mar 07 01:24:33 PM PST 24 |
1474337928 ps |
| T857 |
/workspace/coverage/default/10.sram_ctrl_regwen.1684964142 |
|
|
Mar 07 01:22:52 PM PST 24 |
Mar 07 01:34:17 PM PST 24 |
2505378621 ps |
| T858 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1118269222 |
|
|
Mar 07 01:23:34 PM PST 24 |
Mar 07 02:07:52 PM PST 24 |
83440158843 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2241114713 |
|
|
Mar 07 01:25:17 PM PST 24 |
Mar 07 01:25:18 PM PST 24 |
23291200 ps |
| T860 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.149994919 |
|
|
Mar 07 01:23:00 PM PST 24 |
Mar 07 01:28:03 PM PST 24 |
5631716156 ps |
| T861 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.242243869 |
|
|
Mar 07 01:27:39 PM PST 24 |
Mar 07 01:32:46 PM PST 24 |
11016320799 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1000726523 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:29:31 PM PST 24 |
762648226 ps |
| T863 |
/workspace/coverage/default/32.sram_ctrl_smoke.3696761722 |
|
|
Mar 07 01:25:11 PM PST 24 |
Mar 07 01:25:19 PM PST 24 |
677005161 ps |
| T864 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2287359486 |
|
|
Mar 07 01:23:18 PM PST 24 |
Mar 07 01:49:26 PM PST 24 |
12654654921 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4260397635 |
|
|
Mar 07 01:27:12 PM PST 24 |
Mar 07 01:28:00 PM PST 24 |
1545122269 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.516486556 |
|
|
Mar 07 01:23:32 PM PST 24 |
Mar 07 01:24:11 PM PST 24 |
268277483 ps |
| T867 |
/workspace/coverage/default/31.sram_ctrl_bijection.1338186587 |
|
|
Mar 07 01:24:57 PM PST 24 |
Mar 07 01:25:58 PM PST 24 |
3721760928 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.4105109485 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:38:23 PM PST 24 |
11868185685 ps |
| T32 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2750747890 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:22:30 PM PST 24 |
634491625 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_bijection.2458585186 |
|
|
Mar 07 01:25:28 PM PST 24 |
Mar 07 01:26:29 PM PST 24 |
975119338 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.4151122798 |
|
|
Mar 07 01:24:56 PM PST 24 |
Mar 07 01:42:52 PM PST 24 |
8974054137 ps |
| T871 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2153193005 |
|
|
Mar 07 01:26:12 PM PST 24 |
Mar 07 01:27:57 PM PST 24 |
992205048 ps |
| T872 |
/workspace/coverage/default/42.sram_ctrl_alert_test.713456186 |
|
|
Mar 07 01:26:40 PM PST 24 |
Mar 07 01:26:40 PM PST 24 |
40796615 ps |
| T873 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1390440471 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:23:55 PM PST 24 |
173089352 ps |
| T874 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4252918561 |
|
|
Mar 07 01:26:48 PM PST 24 |
Mar 07 01:26:50 PM PST 24 |
83533264 ps |
| T875 |
/workspace/coverage/default/4.sram_ctrl_executable.13813342 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:30:15 PM PST 24 |
14511593777 ps |
| T876 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1913072259 |
|
|
Mar 07 01:22:28 PM PST 24 |
Mar 07 01:26:59 PM PST 24 |
16186796838 ps |
| T877 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.497743158 |
|
|
Mar 07 01:25:46 PM PST 24 |
Mar 07 01:25:51 PM PST 24 |
147177254 ps |
| T878 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.373569259 |
|
|
Mar 07 01:24:27 PM PST 24 |
Mar 07 01:37:24 PM PST 24 |
12504118635 ps |
| T879 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1223662299 |
|
|
Mar 07 01:26:26 PM PST 24 |
Mar 07 01:30:21 PM PST 24 |
3284495741 ps |
| T880 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.667882626 |
|
|
Mar 07 01:22:42 PM PST 24 |
Mar 07 01:27:43 PM PST 24 |
3197829929 ps |
| T881 |
/workspace/coverage/default/24.sram_ctrl_smoke.334555046 |
|
|
Mar 07 01:24:08 PM PST 24 |
Mar 07 01:24:14 PM PST 24 |
1242939725 ps |
| T882 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2279921531 |
|
|
Mar 07 01:22:44 PM PST 24 |
Mar 07 01:32:46 PM PST 24 |
3027768747 ps |
| T883 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.613468076 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:23:56 PM PST 24 |
76680461 ps |
| T884 |
/workspace/coverage/default/8.sram_ctrl_bijection.2531888842 |
|
|
Mar 07 01:22:39 PM PST 24 |
Mar 07 01:23:23 PM PST 24 |
4222406200 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1740251114 |
|
|
Mar 07 01:22:56 PM PST 24 |
Mar 07 01:26:58 PM PST 24 |
8811525169 ps |
| T886 |
/workspace/coverage/default/17.sram_ctrl_partial_access.456680436 |
|
|
Mar 07 01:23:24 PM PST 24 |
Mar 07 01:23:33 PM PST 24 |
80918500 ps |
| T887 |
/workspace/coverage/default/29.sram_ctrl_bijection.2336547320 |
|
|
Mar 07 01:24:52 PM PST 24 |
Mar 07 01:25:33 PM PST 24 |
640076548 ps |
| T888 |
/workspace/coverage/default/44.sram_ctrl_executable.3144235208 |
|
|
Mar 07 01:27:01 PM PST 24 |
Mar 07 01:43:08 PM PST 24 |
12403628383 ps |
| T889 |
/workspace/coverage/default/41.sram_ctrl_regwen.1802429209 |
|
|
Mar 07 01:26:23 PM PST 24 |
Mar 07 01:44:06 PM PST 24 |
4741545617 ps |
| T890 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3842165980 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:38:04 PM PST 24 |
9400324372 ps |
| T891 |
/workspace/coverage/default/30.sram_ctrl_regwen.8602266 |
|
|
Mar 07 01:24:58 PM PST 24 |
Mar 07 01:28:18 PM PST 24 |
1455163093 ps |
| T892 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.577700559 |
|
|
Mar 07 01:22:09 PM PST 24 |
Mar 07 01:25:22 PM PST 24 |
8426004995 ps |
| T893 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1702604883 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:32:25 PM PST 24 |
2591035494 ps |
| T894 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2876016259 |
|
|
Mar 07 01:26:05 PM PST 24 |
Mar 07 01:30:16 PM PST 24 |
16824452851 ps |
| T895 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3158722156 |
|
|
Mar 07 01:24:38 PM PST 24 |
Mar 07 01:24:39 PM PST 24 |
76573131 ps |
| T896 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1723961276 |
|
|
Mar 07 01:24:45 PM PST 24 |
Mar 07 01:28:17 PM PST 24 |
4825994053 ps |
| T897 |
/workspace/coverage/default/16.sram_ctrl_smoke.2943302706 |
|
|
Mar 07 01:23:14 PM PST 24 |
Mar 07 01:24:32 PM PST 24 |
3166723006 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2649490263 |
|
|
Mar 07 01:25:29 PM PST 24 |
Mar 07 01:26:56 PM PST 24 |
125628386 ps |
| T899 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2332592643 |
|
|
Mar 07 01:23:15 PM PST 24 |
Mar 07 01:23:20 PM PST 24 |
679337608 ps |
| T900 |
/workspace/coverage/default/41.sram_ctrl_smoke.2957395266 |
|
|
Mar 07 01:26:27 PM PST 24 |
Mar 07 01:26:31 PM PST 24 |
227302569 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3781363717 |
|
|
Mar 07 01:24:08 PM PST 24 |
Mar 07 01:24:13 PM PST 24 |
152595166 ps |
| T902 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3640551043 |
|
|
Mar 07 01:26:49 PM PST 24 |
Mar 07 01:26:54 PM PST 24 |
473359192 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1281597711 |
|
|
Mar 07 01:23:54 PM PST 24 |
Mar 07 01:24:00 PM PST 24 |
190116628 ps |
| T904 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.827469743 |
|
|
Mar 07 01:22:27 PM PST 24 |
Mar 07 01:22:30 PM PST 24 |
336698388 ps |
| T905 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2547479129 |
|
|
Mar 07 01:25:38 PM PST 24 |
Mar 07 01:25:40 PM PST 24 |
146526846 ps |
| T906 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2712786608 |
|
|
Mar 07 01:22:55 PM PST 24 |
Mar 07 01:23:05 PM PST 24 |
1088786156 ps |
| T907 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3816150717 |
|
|
Mar 07 01:23:01 PM PST 24 |
Mar 07 01:27:40 PM PST 24 |
16384364126 ps |
| T908 |
/workspace/coverage/default/10.sram_ctrl_stress_all.4068124843 |
|
|
Mar 07 01:22:52 PM PST 24 |
Mar 07 02:23:26 PM PST 24 |
41128273203 ps |
| T909 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3469806105 |
|
|
Mar 07 01:25:37 PM PST 24 |
Mar 07 01:26:18 PM PST 24 |
97843292 ps |
| T910 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3572376396 |
|
|
Mar 07 01:25:32 PM PST 24 |
Mar 07 01:25:33 PM PST 24 |
47307194 ps |
| T911 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.16281310 |
|
|
Mar 07 01:24:07 PM PST 24 |
Mar 07 01:24:23 PM PST 24 |
1304873982 ps |
| T912 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1782997218 |
|
|
Mar 07 01:23:08 PM PST 24 |
Mar 07 01:26:57 PM PST 24 |
8428510030 ps |
| T913 |
/workspace/coverage/default/32.sram_ctrl_regwen.1745274375 |
|
|
Mar 07 01:25:11 PM PST 24 |
Mar 07 01:27:34 PM PST 24 |
13549918485 ps |
| T914 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.322789973 |
|
|
Mar 07 01:23:16 PM PST 24 |
Mar 07 01:23:48 PM PST 24 |
758770580 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1687956535 |
|
|
Mar 07 01:23:41 PM PST 24 |
Mar 07 01:23:50 PM PST 24 |
407761443 ps |
| T916 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2502664424 |
|
|
Mar 07 01:26:06 PM PST 24 |
Mar 07 01:46:03 PM PST 24 |
1815877968 ps |
| T917 |
/workspace/coverage/default/28.sram_ctrl_executable.763048083 |
|
|
Mar 07 01:24:36 PM PST 24 |
Mar 07 01:43:38 PM PST 24 |
50302722975 ps |
| T918 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1820430382 |
|
|
Mar 07 01:27:47 PM PST 24 |
Mar 07 01:27:48 PM PST 24 |
41754729 ps |
| T919 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2860445913 |
|
|
Mar 07 01:26:05 PM PST 24 |
Mar 07 01:26:34 PM PST 24 |
525166363 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4075996321 |
|
|
Mar 07 01:22:10 PM PST 24 |
Mar 07 01:23:20 PM PST 24 |
507240817 ps |
| T921 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1207894550 |
|
|
Mar 07 01:27:52 PM PST 24 |
Mar 07 01:27:57 PM PST 24 |
69134380 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2699312421 |
|
|
Mar 07 01:25:29 PM PST 24 |
Mar 07 01:25:30 PM PST 24 |
12404243 ps |
| T923 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1654692158 |
|
|
Mar 07 01:22:22 PM PST 24 |
Mar 07 01:22:26 PM PST 24 |
244683916 ps |
| T924 |
/workspace/coverage/default/21.sram_ctrl_executable.1504937107 |
|
|
Mar 07 01:23:52 PM PST 24 |
Mar 07 01:37:37 PM PST 24 |
39270221359 ps |
| T925 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3739319375 |
|
|
Mar 07 01:25:11 PM PST 24 |
Mar 07 01:30:58 PM PST 24 |
26285165615 ps |
| T926 |
/workspace/coverage/default/15.sram_ctrl_smoke.819838037 |
|
|
Mar 07 01:23:08 PM PST 24 |
Mar 07 01:23:12 PM PST 24 |
613273772 ps |
| T927 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1403500224 |
|
|
Mar 07 01:25:17 PM PST 24 |
Mar 07 01:25:18 PM PST 24 |
45173607 ps |
| T928 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.379505060 |
|
|
Mar 07 01:26:15 PM PST 24 |
Mar 07 01:37:47 PM PST 24 |
8106448563 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1840928961 |
|
|
Mar 07 01:10:34 PM PST 24 |
Mar 07 01:10:36 PM PST 24 |
221202471 ps |
| T929 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.105587255 |
|
|
Mar 07 01:10:55 PM PST 24 |
Mar 07 01:10:58 PM PST 24 |
269273982 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2571533293 |
|
|
Mar 07 01:10:45 PM PST 24 |
Mar 07 01:10:45 PM PST 24 |
46263818 ps |
| T930 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1374945673 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
26635915 ps |
| T93 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4020277783 |
|
|
Mar 07 01:10:59 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
51561219 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1823182771 |
|
|
Mar 07 01:10:48 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
1075969519 ps |
| T931 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.194165797 |
|
|
Mar 07 01:10:46 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
105575439 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2271191700 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
25555150 ps |
| T104 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.356095763 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:46 PM PST 24 |
670656006 ps |
| T94 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.434299285 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
89262664 ps |
| T932 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4198429031 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:10:58 PM PST 24 |
39879155 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3830616431 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:57 PM PST 24 |
741048004 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3071447111 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
153744269 ps |
| T933 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1429511076 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:11:01 PM PST 24 |
114683722 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.476289581 |
|
|
Mar 07 01:10:46 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
290784303 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3868513234 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
35634734 ps |
| T127 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.942788881 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
149542304 ps |
| T128 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1073628986 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
135877287 ps |
| T129 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3211023901 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
302865778 ps |
| T934 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1024713949 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
113764131 ps |
| T935 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2351492144 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:10:58 PM PST 24 |
33082774 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.183140326 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:56 PM PST 24 |
213803128 ps |
| T936 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.916238358 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
277806532 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1710036426 |
|
|
Mar 07 01:10:35 PM PST 24 |
Mar 07 01:10:37 PM PST 24 |
130939616 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3646372645 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
128417652 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2276983335 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:45 PM PST 24 |
105592556 ps |
| T939 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3613997880 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:56 PM PST 24 |
33935765 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2572243520 |
|
|
Mar 07 01:10:38 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
50410627 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.835936203 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
204256178 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2968358657 |
|
|
Mar 07 01:10:36 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
801556818 ps |
| T97 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3816671219 |
|
|
Mar 07 01:10:45 PM PST 24 |
Mar 07 01:10:46 PM PST 24 |
24527791 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1951871889 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
21510040 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2238980631 |
|
|
Mar 07 01:10:48 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
16400875 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.221442793 |
|
|
Mar 07 01:10:45 PM PST 24 |
Mar 07 01:10:47 PM PST 24 |
25764532 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4011006725 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
798561493 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.902425815 |
|
|
Mar 07 01:10:36 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
173700172 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3089611357 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:10:57 PM PST 24 |
41604811 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.17005412 |
|
|
Mar 07 01:10:38 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
51428676 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1401551228 |
|
|
Mar 07 01:10:36 PM PST 24 |
Mar 07 01:10:36 PM PST 24 |
41280859 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4234507153 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
41449200 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.111951179 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:46 PM PST 24 |
33199560 ps |
| T134 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3035325131 |
|
|
Mar 07 01:10:45 PM PST 24 |
Mar 07 01:10:47 PM PST 24 |
411207211 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1579052193 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
302670864 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3062265906 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:54 PM PST 24 |
40085357 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1343751241 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
799927268 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2752665893 |
|
|
Mar 07 01:10:48 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
436905283 ps |
| T73 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.389453347 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
1057564631 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2064688946 |
|
|
Mar 07 01:10:52 PM PST 24 |
Mar 07 01:10:56 PM PST 24 |
71452327 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2665347764 |
|
|
Mar 07 01:10:39 PM PST 24 |
Mar 07 01:10:42 PM PST 24 |
132664959 ps |
| T953 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1595315395 |
|
|
Mar 07 01:10:50 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
15489982 ps |
| T135 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.119923230 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:11:01 PM PST 24 |
279378414 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3101979402 |
|
|
Mar 07 01:10:33 PM PST 24 |
Mar 07 01:10:35 PM PST 24 |
398248727 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.73962094 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:03 PM PST 24 |
448400801 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2013462496 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:55 PM PST 24 |
61163712 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3299285092 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
788653396 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2535779173 |
|
|
Mar 07 01:10:36 PM PST 24 |
Mar 07 01:10:36 PM PST 24 |
25061359 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2527813475 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:47 PM PST 24 |
157922363 ps |
| T958 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2027449768 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
54562251 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1161929967 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:55 PM PST 24 |
78190526 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3476945048 |
|
|
Mar 07 01:10:43 PM PST 24 |
Mar 07 01:10:44 PM PST 24 |
27434353 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3406205506 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
125739003 ps |
| T137 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.846648676 |
|
|
Mar 07 01:10:50 PM PST 24 |
Mar 07 01:10:53 PM PST 24 |
276729230 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3464958029 |
|
|
Mar 07 01:10:59 PM PST 24 |
Mar 07 01:11:01 PM PST 24 |
138797689 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3552799470 |
|
|
Mar 07 01:10:34 PM PST 24 |
Mar 07 01:10:35 PM PST 24 |
38137885 ps |
| T75 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1469863211 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:46 PM PST 24 |
904564053 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3780320973 |
|
|
Mar 07 01:11:09 PM PST 24 |
Mar 07 01:11:10 PM PST 24 |
42605561 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.438625067 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:56 PM PST 24 |
33220138 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2411173084 |
|
|
Mar 07 01:10:34 PM PST 24 |
Mar 07 01:10:34 PM PST 24 |
21238658 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.192421300 |
|
|
Mar 07 01:10:50 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
98220868 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2292231817 |
|
|
Mar 07 01:11:08 PM PST 24 |
Mar 07 01:11:09 PM PST 24 |
71829846 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4029802079 |
|
|
Mar 07 01:10:43 PM PST 24 |
Mar 07 01:10:44 PM PST 24 |
38715960 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3717039577 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
503418927 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2203302345 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
470380381 ps |
| T77 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1530718941 |
|
|
Mar 07 01:10:59 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
791754611 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2556630649 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
12734005 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.126866411 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:55 PM PST 24 |
38089183 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1231359182 |
|
|
Mar 07 01:10:46 PM PST 24 |
Mar 07 01:10:48 PM PST 24 |
23826218 ps |
| T85 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3689677107 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
924182719 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3414045207 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:10:57 PM PST 24 |
31241485 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3412809353 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:10:57 PM PST 24 |
18077302 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2024374820 |
|
|
Mar 07 01:10:38 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
19709687 ps |
| T136 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1868058790 |
|
|
Mar 07 01:10:50 PM PST 24 |
Mar 07 01:10:53 PM PST 24 |
653156997 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3794485214 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
131638357 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.106408742 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
235551345 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2727783062 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:01 PM PST 24 |
29395069 ps |
| T138 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1379838867 |
|
|
Mar 07 01:10:54 PM PST 24 |
Mar 07 01:10:56 PM PST 24 |
1039841373 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1109328350 |
|
|
Mar 07 01:10:42 PM PST 24 |
Mar 07 01:10:43 PM PST 24 |
207375059 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3195596044 |
|
|
Mar 07 01:10:44 PM PST 24 |
Mar 07 01:10:45 PM PST 24 |
24692606 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3568324671 |
|
|
Mar 07 01:10:53 PM PST 24 |
Mar 07 01:10:54 PM PST 24 |
49221585 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.294863634 |
|
|
Mar 07 01:10:51 PM PST 24 |
Mar 07 01:10:53 PM PST 24 |
222470417 ps |
| T87 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3169512026 |
|
|
Mar 07 01:10:59 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
21886382 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3421898047 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:41 PM PST 24 |
111619861 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2988588416 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
276999173 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.959848802 |
|
|
Mar 07 01:10:51 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
70138713 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3595383614 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
335183727 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2641804517 |
|
|
Mar 07 01:10:38 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
17226522 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1446292172 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
218385452 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.715354969 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:39 PM PST 24 |
460724163 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2556919927 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
789887377 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2802288002 |
|
|
Mar 07 01:10:59 PM PST 24 |
Mar 07 01:11:03 PM PST 24 |
808362370 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1235790802 |
|
|
Mar 07 01:10:45 PM PST 24 |
Mar 07 01:10:46 PM PST 24 |
120304889 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.802861108 |
|
|
Mar 07 01:10:37 PM PST 24 |
Mar 07 01:10:38 PM PST 24 |
32937674 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1319204850 |
|
|
Mar 07 01:10:46 PM PST 24 |
Mar 07 01:10:48 PM PST 24 |
298350071 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1508391376 |
|
|
Mar 07 01:10:46 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
519217190 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3929815264 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:49 PM PST 24 |
46142428 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1292925288 |
|
|
Mar 07 01:10:56 PM PST 24 |
Mar 07 01:11:00 PM PST 24 |
114309094 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4041843138 |
|
|
Mar 07 01:10:52 PM PST 24 |
Mar 07 01:10:53 PM PST 24 |
22676998 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3874021564 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
67192040 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1713648533 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:11:03 PM PST 24 |
437837968 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2708898087 |
|
|
Mar 07 01:10:39 PM PST 24 |
Mar 07 01:10:40 PM PST 24 |
16018223 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2376017862 |
|
|
Mar 07 01:10:50 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
17474284 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3507514338 |
|
|
Mar 07 01:10:47 PM PST 24 |
Mar 07 01:10:52 PM PST 24 |
981616157 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.972772871 |
|
|
Mar 07 01:10:57 PM PST 24 |
Mar 07 01:10:58 PM PST 24 |
21978661 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1322039962 |
|
|
Mar 07 01:11:00 PM PST 24 |
Mar 07 01:11:02 PM PST 24 |
203192453 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.36670285 |
|
|
Mar 07 01:10:48 PM PST 24 |
Mar 07 01:10:50 PM PST 24 |
120809528 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3318774887 |
|
|
Mar 07 01:10:58 PM PST 24 |
Mar 07 01:10:59 PM PST 24 |
18597352 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1531600344 |
|
|
Mar 07 01:10:49 PM PST 24 |
Mar 07 01:10:51 PM PST 24 |
268493826 ps |