Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14177690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58574751

1

T1

2876

T2

70

T3

384002

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36260161	1			T1	1575		T2	373		T3	210641
values[0x0]	16834007	1			T1	780		T2	192		T3	101751
values[0x1]	19658273	1			T1	812		T2	446		T3	108492

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7063843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65688598

1

T1

3016

T2

477

T3

402332

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	256762	1			T1	16		T2	8		T5	5
valid_sources[0x01]	289736	1			T1	5		T3	11		T5	3
valid_sources[0x02]	360720	1			T1	5		T2	1		T5	12
valid_sources[0x03]	310440	1			T1	8		T2	5		T3	3454
valid_sources[0x04]	314507	1			T1	10		T2	4		T5	7
valid_sources[0x05]	289459	1			T1	11		T2	6		T5	10
valid_sources[0x06]	329496	1			T1	14		T2	8		T5	13
valid_sources[0x07]	247753	1			T1	10		T2	2		T3	18
valid_sources[0x08]	291823	1			T1	5		T2	1		T5	3
valid_sources[0x09]	275312	1			T1	22		T2	7		T5	6
valid_sources[0x0a]	251641	1			T1	17		T2	8		T3	55
valid_sources[0x0b]	296273	1			T1	18		T2	4		T5	11
valid_sources[0x0c]	286359	1			T1	11		T2	5		T5	3
valid_sources[0x0d]	285708	1			T1	7		T2	2		T5	7
valid_sources[0x0e]	261230	1			T1	12		T2	3		T5	16
valid_sources[0x0f]	252293	1			T1	9		T2	8		T5	5
valid_sources[0x10]	322002	1			T1	11		T2	8		T5	8
valid_sources[0x11]	290539	1			T1	11		T2	4		T3	640
valid_sources[0x12]	285277	1			T1	12		T2	2		T3	22281
valid_sources[0x13]	245992	1			T1	12		T5	7		T6	22
valid_sources[0x14]	249220	1			T1	19		T2	4		T5	9
valid_sources[0x15]	324020	1			T1	5		T2	1		T5	17
valid_sources[0x16]	249752	1			T1	24		T2	5		T5	4
valid_sources[0x17]	270238	1			T1	15		T2	4		T5	11
valid_sources[0x18]	290047	1			T1	14		T2	2		T5	4
valid_sources[0x19]	245948	1			T1	6		T2	8		T3	6715
valid_sources[0x1a]	332434	1			T1	26		T2	6		T5	5
valid_sources[0x1b]	280445	1			T1	7		T2	1		T5	13
valid_sources[0x1c]	261829	1			T1	15		T5	10		T6	12
valid_sources[0x1d]	288823	1			T1	18		T2	1		T5	15
valid_sources[0x1e]	273832	1			T1	11		T5	6		T6	21
valid_sources[0x1f]	291292	1			T1	4		T2	7		T5	7
valid_sources[0x20]	290082	1			T1	13		T2	6		T5	3
valid_sources[0x21]	266772	1			T1	9		T5	10		T6	23
valid_sources[0x22]	277837	1			T1	8		T2	9		T5	14
valid_sources[0x23]	326561	1			T1	13		T2	4		T5	15
valid_sources[0x24]	250019	1			T1	3		T2	2		T3	106
valid_sources[0x25]	246429	1			T1	10		T2	2		T5	18
valid_sources[0x26]	371929	1			T1	17		T2	1		T3	16350
valid_sources[0x27]	327345	1			T1	15		T2	3		T3	3549
valid_sources[0x28]	310491	1			T1	12		T2	2		T5	3
valid_sources[0x29]	311731	1			T1	9		T2	2		T5	7
valid_sources[0x2a]	253658	1			T1	10		T2	11		T5	9
valid_sources[0x2b]	273926	1			T1	11		T2	4		T5	5
valid_sources[0x2c]	293943	1			T1	15		T2	3		T5	9
valid_sources[0x2d]	288449	1			T1	23		T2	3		T3	70
valid_sources[0x2e]	264040	1			T1	5		T2	8		T3	28
valid_sources[0x2f]	283863	1			T1	13		T2	10		T5	3
valid_sources[0x30]	296250	1			T1	9		T2	3		T5	14
valid_sources[0x31]	246777	1			T1	4		T2	4		T3	64
valid_sources[0x32]	304534	1			T1	8		T2	2		T5	6
valid_sources[0x33]	260536	1			T1	13		T2	4		T5	3
valid_sources[0x34]	396202	1			T1	5		T2	4		T5	12
valid_sources[0x35]	276994	1			T1	9		T2	1		T5	12
valid_sources[0x36]	270601	1			T1	17		T2	5		T5	6
valid_sources[0x37]	248613	1			T1	12		T2	2		T5	13
valid_sources[0x38]	312124	1			T1	4		T2	1		T5	8
valid_sources[0x39]	332543	1			T1	9		T2	5		T5	8
valid_sources[0x3a]	284940	1			T1	8		T2	3		T5	10
valid_sources[0x3b]	262432	1			T1	18		T2	5		T5	10
valid_sources[0x3c]	331921	1			T1	9		T2	4		T3	45
valid_sources[0x3d]	252735	1			T1	6		T2	8		T3	49
valid_sources[0x3e]	294846	1			T1	27		T2	3		T3	1873
valid_sources[0x3f]	281536	1			T1	17		T2	4		T5	5
valid_sources[0x40]	264127	1			T1	26		T2	4		T5	14
valid_sources[0x41]	283959	1			T1	16		T2	3		T5	5
valid_sources[0x42]	250215	1			T1	28		T2	3		T5	7
valid_sources[0x43]	320592	1			T1	10		T2	5		T5	14
valid_sources[0x44]	276115	1			T1	13		T2	1		T5	5
valid_sources[0x45]	322080	1			T1	14		T2	4		T5	7
valid_sources[0x46]	363387	1			T1	11		T2	1		T3	934
valid_sources[0x47]	241304	1			T1	15		T2	3		T5	11
valid_sources[0x48]	264746	1			T1	20		T2	6		T3	46
valid_sources[0x49]	338644	1			T1	12		T2	5		T5	6
valid_sources[0x4a]	268776	1			T1	2		T2	12		T3	12946
valid_sources[0x4b]	254482	1			T1	17		T2	1		T3	4601
valid_sources[0x4c]	258066	1			T1	15		T5	8		T6	26
valid_sources[0x4d]	372908	1			T1	14		T2	5		T3	3897
valid_sources[0x4e]	273564	1			T1	11		T2	3		T3	34015
valid_sources[0x4f]	283657	1			T1	11		T2	4		T5	5
valid_sources[0x50]	325675	1			T1	12		T2	1		T3	125
valid_sources[0x51]	297143	1			T1	12		T2	6		T5	9
valid_sources[0x52]	320238	1			T1	9		T2	2		T3	20
valid_sources[0x53]	272563	1			T1	4		T5	9		T6	28
valid_sources[0x54]	374453	1			T1	11		T2	9		T5	4
valid_sources[0x55]	283395	1			T1	13		T2	9		T3	2739
valid_sources[0x56]	243373	1			T1	13		T2	3		T3	270
valid_sources[0x57]	265228	1			T1	6		T2	5		T5	6
valid_sources[0x58]	258845	1			T1	15		T2	6		T5	9
valid_sources[0x59]	256960	1			T1	8		T2	4		T5	3
valid_sources[0x5a]	346289	1			T1	16		T2	2		T5	18
valid_sources[0x5b]	292351	1			T1	17		T2	1		T3	17
valid_sources[0x5c]	246870	1			T1	11		T2	3		T3	104
valid_sources[0x5d]	271539	1			T1	13		T2	1		T5	17
valid_sources[0x5e]	329831	1			T1	13		T2	3		T3	40948
valid_sources[0x5f]	268563	1			T1	8		T2	11		T5	6
valid_sources[0x60]	310443	1			T1	13		T2	1		T5	4
valid_sources[0x61]	261312	1			T1	4		T5	5		T6	37
valid_sources[0x62]	253462	1			T1	17		T2	9		T5	8
valid_sources[0x63]	255130	1			T1	12		T2	8		T3	128
valid_sources[0x64]	269244	1			T1	7		T2	1		T3	35
valid_sources[0x65]	261192	1			T1	8		T2	1		T5	8
valid_sources[0x66]	266772	1			T1	15		T2	5		T5	6
valid_sources[0x67]	252797	1			T1	8		T2	4		T3	59
valid_sources[0x68]	257728	1			T1	11		T2	4		T3	21
valid_sources[0x69]	295213	1			T1	10		T2	3		T5	6
valid_sources[0x6a]	248123	1			T1	8		T2	1		T5	5
valid_sources[0x6b]	315604	1			T1	10		T2	3		T3	83
valid_sources[0x6c]	308425	1			T1	7		T2	2		T5	4
valid_sources[0x6d]	269364	1			T1	20		T2	5		T5	6
valid_sources[0x6e]	276011	1			T1	14		T2	8		T5	9
valid_sources[0x6f]	274101	1			T1	17		T2	3		T5	7
valid_sources[0x70]	245773	1			T1	10		T2	2		T5	12
valid_sources[0x71]	282859	1			T1	11		T5	11		T6	13
valid_sources[0x72]	255057	1			T1	21		T2	1		T5	4
valid_sources[0x73]	243477	1			T1	21		T2	2		T5	12
valid_sources[0x74]	291087	1			T1	21		T2	5		T5	9
valid_sources[0x75]	280508	1			T1	9		T2	1		T3	22392
valid_sources[0x76]	283689	1			T1	10		T2	3		T5	16
valid_sources[0x77]	248441	1			T1	10		T2	1		T3	58
valid_sources[0x78]	256594	1			T1	10		T2	7		T3	2903
valid_sources[0x79]	267742	1			T1	11		T2	6		T5	5
valid_sources[0x7a]	260706	1			T1	19		T2	2		T5	4
valid_sources[0x7b]	283714	1			T1	21		T2	2		T5	14
valid_sources[0x7c]	305162	1			T1	9		T2	4		T5	6
valid_sources[0x7d]	277333	1			T1	14		T2	7		T5	8
valid_sources[0x7e]	311475	1			T1	12		T2	3		T3	85
valid_sources[0x7f]	353183	1			T1	13		T2	6		T5	4
valid_sources[0x80]	252952	1			T1	15		T2	5		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29176760

1

T1

1453

T2

4

T3

192326

values[0x0]

all_enables

biggest_size

14705637

1

T1

728

T2

31

T3

96092

values[0x1]

all_enables

biggest_size

14692354

1

T1

695

T2

35

T3

95584

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132961

1

T1

24

T3

52

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49324	1			T1	26		T3	38		T4	14
values[0x0]	57524	1			T1	16		T3	68		T6	1
values[0x1]	60709	1			T1	8		T2	1		T3	73

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141129

1

T1

27

T3

66

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	783	1			T23	1		T61	1		T16	1
valid_sources[0x01]	894	1			T12	1		T23	1		T27	43
valid_sources[0x02]	611	1			T91	2		T59	2		T61	1
valid_sources[0x03]	446	1			T61	1		T16	1		T27	41
valid_sources[0x04]	803	1			T61	7		T30	1		T27	19
valid_sources[0x05]	762	1			T23	1		T61	4		T27	38
valid_sources[0x06]	759	1			T24	2		T59	1		T16	1
valid_sources[0x07]	565	1			T1	1		T15	19		T61	1
valid_sources[0x08]	515	1			T24	1		T61	2		T27	37
valid_sources[0x09]	549	1			T14	1		T24	1		T27	26
valid_sources[0x0a]	675	1			T17	1		T44	1		T23	2
valid_sources[0x0b]	632	1			T14	1		T24	2		T60	1
valid_sources[0x0c]	396	1			T146	2		T24	2		T61	2
valid_sources[0x0d]	1224	1			T61	1		T27	32		T101	7
valid_sources[0x0e]	424	1			T12	1		T23	1		T27	24
valid_sources[0x0f]	453	1			T1	2		T24	1		T59	1
valid_sources[0x10]	959	1			T14	1		T59	1		T61	2
valid_sources[0x11]	532	1			T61	5		T147	1		T27	33
valid_sources[0x12]	897	1			T24	3		T59	1		T27	36
valid_sources[0x13]	653	1			T61	7		T27	42		T141	1
valid_sources[0x14]	638	1			T1	7		T16	1		T27	46
valid_sources[0x15]	748	1			T9	2		T61	1		T16	1
valid_sources[0x16]	629	1			T12	1		T61	4		T147	1
valid_sources[0x17]	480	1			T59	1		T27	58		T148	1
valid_sources[0x18]	767	1			T23	1		T27	19		T134	1
valid_sources[0x19]	434	1			T23	1		T61	2		T27	9
valid_sources[0x1a]	430	1			T61	1		T27	15		T140	1
valid_sources[0x1b]	864	1			T59	1		T61	1		T16	1
valid_sources[0x1c]	893	1			T11	2		T23	1		T59	1
valid_sources[0x1d]	592	1			T23	2		T59	1		T61	3
valid_sources[0x1e]	534	1			T61	3		T27	39		T149	6
valid_sources[0x1f]	778	1			T61	2		T27	48		T134	1
valid_sources[0x20]	508	1			T14	1		T59	1		T16	1
valid_sources[0x21]	701	1			T23	1		T24	3		T100	1
valid_sources[0x22]	701	1			T14	2		T24	1		T27	31
valid_sources[0x23]	521	1			T12	1		T59	1		T61	1
valid_sources[0x24]	635	1			T4	11		T24	3		T59	1
valid_sources[0x25]	448	1			T24	1		T31	1		T27	17
valid_sources[0x26]	786	1			T59	1		T27	40		T141	1
valid_sources[0x27]	607	1			T90	1		T23	1		T27	27
valid_sources[0x28]	550	1			T27	16		T134	4		T150	1
valid_sources[0x29]	1159	1			T59	1		T27	43		T134	1
valid_sources[0x2a]	812	1			T24	1		T27	19		T53	1
valid_sources[0x2b]	761	1			T12	2		T27	24		T148	1
valid_sources[0x2c]	492	1			T23	1		T24	2		T61	4
valid_sources[0x2d]	723	1			T12	1		T24	2		T61	2
valid_sources[0x2e]	488	1			T59	1		T16	1		T27	20
valid_sources[0x2f]	952	1			T27	25		T151	1		T28	5
valid_sources[0x30]	639	1			T60	1		T61	3		T27	26
valid_sources[0x31]	689	1			T6	1		T16	1		T27	31
valid_sources[0x32]	820	1			T59	1		T27	27		T134	5
valid_sources[0x33]	675	1			T61	5		T27	46		T152	2
valid_sources[0x34]	800	1			T23	1		T24	1		T59	1
valid_sources[0x35]	698	1			T59	1		T61	4		T16	1
valid_sources[0x36]	636	1			T27	42		T153	4		T154	1
valid_sources[0x37]	686	1			T12	1		T13	17		T44	1
valid_sources[0x38]	589	1			T44	1		T61	2		T27	20
valid_sources[0x39]	539	1			T12	1		T13	8		T59	1
valid_sources[0x3a]	564	1			T59	2		T27	30		T134	1
valid_sources[0x3b]	735	1			T24	1		T61	1		T27	29
valid_sources[0x3c]	544	1			T14	1		T155	1		T24	1
valid_sources[0x3d]	717	1			T91	1		T23	1		T59	1
valid_sources[0x3e]	742	1			T1	2		T61	1		T97	1
valid_sources[0x3f]	725	1			T14	1		T27	28		T134	1
valid_sources[0x40]	556	1			T8	10		T17	1		T23	2
valid_sources[0x41]	503	1			T23	2		T61	7		T27	26
valid_sources[0x42]	469	1			T12	1		T61	1		T97	1
valid_sources[0x43]	621	1			T61	3		T27	29		T141	2
valid_sources[0x44]	556	1			T23	1		T24	1		T61	4
valid_sources[0x45]	583	1			T23	1		T27	28		T134	1
valid_sources[0x46]	692	1			T61	5		T27	27		T141	2
valid_sources[0x47]	1039	1			T12	2		T23	1		T27	23
valid_sources[0x48]	499	1			T12	1		T23	1		T27	22
valid_sources[0x49]	663	1			T59	1		T27	12		T141	1
valid_sources[0x4a]	514	1			T23	1		T61	1		T27	33
valid_sources[0x4b]	622	1			T23	1		T24	1		T16	1
valid_sources[0x4c]	553	1			T23	2		T24	2		T61	1
valid_sources[0x4d]	505	1			T23	1		T61	2		T27	8
valid_sources[0x4e]	792	1			T13	42		T59	1		T100	1
valid_sources[0x4f]	535	1			T156	3		T27	24		T157	1
valid_sources[0x50]	520	1			T12	1		T90	1		T24	1
valid_sources[0x51]	426	1			T12	1		T60	2		T61	1
valid_sources[0x52]	710	1			T12	2		T14	1		T44	1
valid_sources[0x53]	649	1			T59	2		T61	1		T27	22
valid_sources[0x54]	935	1			T27	33		T134	7		T158	1
valid_sources[0x55]	697	1			T60	1		T61	1		T27	22
valid_sources[0x56]	674	1			T14	2		T61	3		T27	48
valid_sources[0x57]	675	1			T4	12		T23	1		T61	1
valid_sources[0x58]	1215	1			T44	1		T61	6		T27	19
valid_sources[0x59]	550	1			T23	2		T24	5		T59	2
valid_sources[0x5a]	531	1			T23	1		T27	38		T159	2
valid_sources[0x5b]	774	1			T23	1		T24	6		T59	1
valid_sources[0x5c]	723	1			T27	46		T142	1		T134	6
valid_sources[0x5d]	448	1			T27	17		T134	1		T141	1
valid_sources[0x5e]	457	1			T60	1		T96	1		T27	36
valid_sources[0x5f]	417	1			T1	3		T23	1		T59	1
valid_sources[0x60]	494	1			T59	1		T61	3		T16	1
valid_sources[0x61]	595	1			T99	1		T27	25		T153	2
valid_sources[0x62]	793	1			T23	1		T59	1		T61	4
valid_sources[0x63]	691	1			T12	1		T61	6		T27	25
valid_sources[0x64]	692	1			T91	2		T61	3		T27	34
valid_sources[0x65]	460	1			T24	3		T59	5		T27	21
valid_sources[0x66]	582	1			T23	1		T24	1		T27	20
valid_sources[0x67]	636	1			T12	1		T160	1		T27	22
valid_sources[0x68]	682	1			T12	2		T44	2		T23	1
valid_sources[0x69]	706	1			T23	1		T24	2		T61	4
valid_sources[0x6a]	736	1			T14	2		T13	13		T60	1
valid_sources[0x6b]	571	1			T4	5		T12	1		T24	2
valid_sources[0x6c]	680	1			T24	3		T27	28		T141	1
valid_sources[0x6d]	907	1			T2	1		T23	1		T61	1
valid_sources[0x6e]	496	1			T23	2		T24	1		T61	3
valid_sources[0x6f]	559	1			T1	1		T12	1		T44	1
valid_sources[0x70]	715	1			T59	1		T61	3		T27	32
valid_sources[0x71]	710	1			T14	1		T61	6		T27	33
valid_sources[0x72]	659	1			T10	1		T17	1		T61	1
valid_sources[0x73]	799	1			T23	1		T161	1		T27	20
valid_sources[0x74]	652	1			T44	1		T61	7		T27	24
valid_sources[0x75]	646	1			T23	2		T61	1		T27	22
valid_sources[0x76]	583	1			T27	42		T162	1		T134	1
valid_sources[0x77]	872	1			T1	2		T59	1		T61	1
valid_sources[0x78]	708	1			T27	54		T134	2		T28	16
valid_sources[0x79]	852	1			T44	2		T27	36		T134	6
valid_sources[0x7a]	920	1			T12	2		T14	1		T59	2
valid_sources[0x7b]	677	1			T12	2		T24	1		T61	1
valid_sources[0x7c]	640	1			T17	1		T27	24		T163	11
valid_sources[0x7d]	474	1			T61	7		T27	31		T153	1
valid_sources[0x7e]	461	1			T61	3		T27	33		T140	3
valid_sources[0x7f]	581	1			T23	1		T61	10		T27	55
valid_sources[0x80]	691	1			T44	2		T59	1		T27	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36813

1

T1

14

T3

20

T4

10

values[0x0]

all_enables

biggest_size

49343

1

T1

8

T3

16

T7

1

values[0x1]

all_enables

biggest_size

46805

1

T1

2

T3

16

T7

1