Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13854695

1

T1

20

T2

941

T3

29673

full_word

53360360

1

T1

160

T2

70

T3

311311

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67214715	1			T1	180		T2	1011		T3	340984
auto[TlIntgErrCmd]	111	1			T103	8		T104	3		T105	4
auto[TlIntgErrData]	105	1			T103	7		T104	4		T105	5
auto[TlIntgErrBoth]	124	1			T103	5		T104	3		T105	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30632926

1

T1

99

T2

373

T3

131901

auto[1]

36582129

1

T1

81

T2

638

T3

209083

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6608854	1			T1	7		T2	369		T3	11212
auto[TlIntgErrNone]	partial	auto[1]	7245529	1			T1	13		T2	572		T3	18461
auto[TlIntgErrNone]	full_word	auto[0]	24023913	1			T1	92		T2	4		T3	120689
auto[TlIntgErrNone]	full_word	auto[1]	29336419	1			T1	68		T2	66		T3	190622
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T103	4		T104	1		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T103	4		T104	2		T105	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T105	1		T128	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T123	1		T131	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T103	3		T104	4		T105	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T103	3		T105	2		T123	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T123	1		T131	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T103	1		T131	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T103	3		T104	2		T105	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T103	2		T104	1		T105	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T127	1		T132	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T123	2		T127	1		T130	1