Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	500429	1			T1	10		T6	835		T7	7269
auto[1]	9875078	1			T1	5		T2	51		T3	933
auto[2]	417657	1			T1	6		T6	587		T7	6631
auto[3]	9802043	1			T1	5		T2	101		T3	944

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13406774	1			T1	15		T3	1336		T6	67
auto[1]	1957525	1			T1	6		T2	5		T3	251
auto[2]	1966204	1			T1	4		T2	12		T3	259
auto[3]	3264704	1			T1	1		T2	135		T3	31

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7894921

1

T1

26

T2

152

T3

1876

auto[1]

12700286

1

T3

1

T6

7

T7

14

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	187607	1			T1	9		T6	31		T7	5990
auto[0]	auto[0]	auto[1]	19971	1			T1	1		T6	125		T7	609
auto[0]	auto[0]	auto[2]	20021	1			T6	123		T7	591		T13	88
auto[0]	auto[0]	auto[3]	9811	1			T6	552		T7	74		T13	3
auto[0]	auto[1]	auto[0]	3069015	1			T1	3		T3	666		T6	1
auto[0]	auto[1]	auto[1]	316092	1			T1	1		T2	1		T3	181
auto[0]	auto[1]	auto[2]	305196	1			T1	1		T2	4		T3	70
auto[0]	auto[1]	auto[3]	59994	1			T2	46		T3	15		T6	530
auto[0]	auto[2]	auto[0]	151314	1			T1	2		T6	32		T7	5408
auto[0]	auto[2]	auto[1]	16574	1			T1	1		T6	112		T7	616
auto[0]	auto[2]	auto[2]	17000	1			T1	2		T6	73		T7	542
auto[0]	auto[2]	auto[3]	7680	1			T1	1		T6	370		T7	58
auto[0]	auto[3]	auto[0]	3036867	1			T1	1		T3	670		T6	2
auto[0]	auto[3]	auto[1]	301825	1			T1	3		T2	4		T3	69
auto[0]	auto[3]	auto[2]	314492	1			T1	1		T2	8		T3	189
auto[0]	auto[3]	auto[3]	61462	1			T2	89		T3	16		T6	370
auto[1]	auto[0]	auto[0]	8945	1			T6	1		T7	4		T44	4
auto[1]	auto[0]	auto[1]	39009	1			T44	1		T140	3		T141	2
auto[1]	auto[0]	auto[2]	39299	1			T6	1		T7	1		T23	1
auto[1]	auto[0]	auto[3]	175766	1			T6	2		T61	1		T142	1
auto[1]	auto[1]	auto[0]	3475422	1			T8	12		T9	3		T10	116427
auto[1]	auto[1]	auto[1]	631706	1			T3	1		T8	2		T10	11490
auto[1]	auto[1]	auto[2]	608958	1			T8	2		T10	11629		T11	1
auto[1]	auto[1]	auto[3]	1408695	1			T6	1		T10	1175		T14	1
auto[1]	auto[2]	auto[0]	7327	1			T7	5		T44	1		T23	18
auto[1]	auto[2]	auto[1]	32374	1			T7	2		T13	1		T23	1
auto[1]	auto[2]	auto[2]	33770	1			T23	3		T140	1		T141	1
auto[1]	auto[2]	auto[3]	151618	1			T143	1		T137	8139		T138	11139
auto[1]	auto[3]	auto[0]	3470277	1			T8	11		T10	116607		T11	4
auto[1]	auto[3]	auto[1]	599974	1			T10	11566		T11	1		T90	1
auto[1]	auto[3]	auto[2]	627468	1			T6	1		T7	2		T8	2
auto[1]	auto[3]	auto[3]	1389678	1			T6	1		T10	1102		T72	595