Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	316770301	128853	0	0
ctrl_regwen_rd_A	316770301	5652	0	0
exec_rd_A	316770301	5352	0	0
exec_regwen_rd_A	316770301	5383	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316770301	128853	0	0
T18	1179	0	0	0
T19	974	0	0	0
T27	296568	9623	0	0
T28	0	1152	0	0
T29	0	3437	0	0
T45	0	3132	0	0
T46	0	4686	0	0
T47	0	9291	0	0
T48	0	3232	0	0
T49	0	1845	0	0
T50	0	1900	0	0
T51	0	599	0	0
T52	381518	0	0	0
T53	189615	0	0	0
T54	863654	0	0	0
T55	16658	0	0	0
T56	100300	0	0	0
T57	6899	0	0	0
T58	673	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316770301	5652	0	0
T26	34084	0	0	0
T28	76140	360	0	0
T48	0	750	0	0
T49	0	381	0	0
T51	0	98	0	0
T106	0	198	0	0
T107	0	268	0	0
T108	0	203	0	0
T109	0	622	0	0
T110	0	213	0	0
T111	0	686	0	0
T112	167868	0	0	0
T113	1064	0	0	0
T114	80812	0	0	0
T115	78529	0	0	0
T116	872887	0	0	0
T117	16313	0	0	0
T118	65951	0	0	0
T119	974305	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316770301	5352	0	0
T26	34084	0	0	0
T28	76140	367	0	0
T48	0	740	0	0
T49	0	357	0	0
T51	0	61	0	0
T106	0	231	0	0
T107	0	277	0	0
T108	0	181	0	0
T109	0	603	0	0
T110	0	231	0	0
T111	0	554	0	0
T112	167868	0	0	0
T113	1064	0	0	0
T114	80812	0	0	0
T115	78529	0	0	0
T116	872887	0	0	0
T117	16313	0	0	0
T118	65951	0	0	0
T119	974305	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316770301	5383	0	0
T26	34084	0	0	0
T28	76140	397	0	0
T48	0	755	0	0
T49	0	320	0	0
T51	0	77	0	0
T106	0	202	0	0
T107	0	286	0	0
T108	0	233	0	0
T109	0	555	0	0
T110	0	206	0	0
T111	0	536	0	0
T112	167868	0	0	0
T113	1064	0	0	0
T114	80812	0	0	0
T115	78529	0	0	0
T116	872887	0	0	0
T117	16313	0	0	0
T118	65951	0	0	0
T119	974305	0	0	0