Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140984064	1			T1	240448		T2	15790		T3	13954
instr_valid_dis	112455957	1			T1	12626		T2	15790		T3	13954
instr_en	19661417	1			T1	36254		T10	120094		T18	158212

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10357985	1			T10	17710		T18	119402		T37	54358
sram_ifetch_valid_disable	109808937	1			T1	188254		T2	15790		T3	13954
sram_ifetch_enable	20817142	1			T1	52194		T10	57098		T37	106306

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140984064	1			T1	240448		T2	15790		T3	13954
hw_debug_en_valid_off	110985125	1			T1	142066		T2	15790		T3	13954
hw_debug_en_on	18863622	1			T1	28374		T10	111080		T37	57158

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109808937	1			T1	188254		T2	15790		T3	13954
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99091686	1			T2	15790		T3	13954		T7	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7644587	1			T1	36254		T10	63930		T18	54820
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4520072	1			T18	119402		T37	48532		T31	48620
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1932600	1			T18	16010		T31	48620		T66	14132
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1812118	1			T18	103392		T15	35754		T33	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3591859	1			T10	17710		T37	5826		T15	97632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1699340	1			T66	17554		T138	16278		T142	23870
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1176048	1			T10	17710		T37	5826		T15	57838
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7128624	1			T1	17666		T10	73370		T37	35350
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3142050	1			T10	44448		T37	27062		T15	47980
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2720894	1			T37	8288		T15	137240		T5	29612

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8258932	1			T10	38454		T37	15982		T31	7694
lc_exec_en	8143139	1			T1	10708		T10	20000		T37	15982
valid_exec_dis	106960779	1			T1	141552		T2	15790		T3	13954
invalid_exec_dis	31175127	1			T1	52194		T10	74808		T18	119402