Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.39 100.00 97.77 100.00 100.00 99.71 99.70 98.52


Total tests in report: 1013
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
77.61 77.61 97.18 97.18 71.27 71.27 75.18 75.18 71.43 71.43 89.05 89.05 94.45 94.45 44.71 44.71 /workspace/coverage/default/49.sram_ctrl_executable.913313846
88.39 10.78 98.15 0.97 85.63 14.37 93.53 18.35 71.43 0.00 92.22 3.17 95.95 1.50 81.82 37.11 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2178219165
95.25 6.86 99.51 1.36 92.75 7.11 93.88 0.36 100.00 28.57 97.69 5.48 96.25 0.30 86.64 4.82 /workspace/coverage/default/31.sram_ctrl_stress_all.1968946042
96.28 1.04 99.71 0.19 93.72 0.98 94.10 0.21 100.00 0.00 98.56 0.86 96.25 0.00 91.65 5.01 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1028747353
96.93 0.65 99.71 0.00 94.00 0.28 95.49 1.39 100.00 0.00 98.85 0.29 96.40 0.15 94.06 2.41 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.676967922
97.57 0.64 99.90 0.19 96.09 2.09 95.85 0.36 100.00 0.00 99.71 0.86 97.00 0.60 94.43 0.37 /workspace/coverage/default/1.sram_ctrl_sec_cm.486451173
97.96 0.39 99.90 0.00 96.93 0.84 97.75 1.90 100.00 0.00 99.71 0.00 97.00 0.00 94.43 0.00 /workspace/coverage/default/9.sram_ctrl_smoke.2227242035
98.21 0.25 99.90 0.00 96.93 0.00 98.39 0.64 100.00 0.00 99.71 0.00 97.00 0.00 95.55 1.11 /workspace/coverage/default/20.sram_ctrl_regwen.3227963914
98.42 0.20 99.90 0.00 96.93 0.00 98.46 0.07 100.00 0.00 99.71 0.00 98.35 1.35 95.55 0.00 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1801075814
98.62 0.20 99.90 0.00 97.35 0.42 98.89 0.43 100.00 0.00 99.71 0.00 98.35 0.00 96.10 0.56 /workspace/coverage/default/10.sram_ctrl_alert_test.3710552413
98.79 0.18 99.90 0.00 97.63 0.28 98.96 0.07 100.00 0.00 99.71 0.00 99.25 0.90 96.10 0.00 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3005135712
98.92 0.13 100.00 0.10 97.63 0.00 99.75 0.79 100.00 0.00 99.71 0.00 99.25 0.00 96.10 0.00 /workspace/coverage/default/46.sram_ctrl_ram_cfg.532832009
99.03 0.11 100.00 0.00 97.63 0.00 99.75 0.00 100.00 0.00 99.71 0.00 99.25 0.00 96.85 0.74 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.546597819
99.12 0.09 100.00 0.00 97.63 0.00 99.75 0.00 100.00 0.00 99.71 0.00 99.70 0.45 97.03 0.19 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.187437812
99.20 0.08 100.00 0.00 97.63 0.00 99.75 0.00 100.00 0.00 99.71 0.00 99.70 0.00 97.59 0.56 /workspace/coverage/default/6.sram_ctrl_executable.1963668582
99.25 0.05 100.00 0.00 97.63 0.00 99.75 0.00 100.00 0.00 99.71 0.00 99.70 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.408920114
99.29 0.04 100.00 0.00 97.63 0.00 99.82 0.07 100.00 0.00 99.71 0.00 99.70 0.00 98.14 0.19 /workspace/coverage/default/16.sram_ctrl_stress_all.1724839965
99.31 0.03 100.00 0.00 97.63 0.00 99.82 0.00 100.00 0.00 99.71 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1505612978
99.34 0.03 100.00 0.00 97.63 0.00 99.82 0.00 100.00 0.00 99.71 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1662764086
99.36 0.02 100.00 0.00 97.63 0.00 99.93 0.11 100.00 0.00 99.71 0.00 99.70 0.00 98.52 0.00 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1141027103
99.37 0.01 100.00 0.00 97.63 0.00 100.00 0.07 100.00 0.00 99.71 0.00 99.70 0.00 98.52 0.00 /workspace/coverage/default/1.sram_ctrl_bijection.2119922126

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1610058817
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2253175713
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3086522822
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.357122235
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2464256671
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3698673701
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2787110902
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1355957181
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1012397870
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4156545029
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2020507803
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2793875024
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3565128800
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.112776495
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3532957583
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1935238644
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3962028543
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2909281790
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.581040708
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1778810631
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3537891791
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.605731490
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1134610780
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.862999509
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4090451916
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.666403093
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2108736976
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.17068999
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1037366092
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3464795302
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3445158708
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2273556614
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3701836498
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1111632767
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2309559108
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1411579454
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.245836965
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2181347220
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2519765396
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2181195716
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4031467972
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2294363454
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4111573330
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1350008730
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1176726589
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1300612853
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.558300822
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2661880795
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2362057146
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3491237901
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.515230715
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3576250717
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3284773197
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3635942111
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1721632150
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2549753081
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.433864760
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3480094768
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.183431342
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.174730554
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1711708888
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3164175024
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3666222288
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3044325722
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3376987771
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1389466343
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.396535254
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1449343760
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.553787769
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.69749692
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1214585049
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2818772858
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.823712975
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2912494233
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.647331761
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2961166520
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.160381088
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3678559481
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1478340532
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2017967271
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.964102534
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1936209792
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3897228805
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1373404406
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2699357379
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.342617153
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1287552510
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3793742585
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2872492145
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.804033559
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.491306292
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1997424882
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.160835604
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3499336329
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4215746116
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.308253844
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.47871653
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1283596265
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.811310949
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.227619810
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1265219939
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2431222170
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3801916212
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2898312845
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1742066579
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1292275670
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4291847973
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.953727564
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2367169748
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2092235079
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1743884289
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4178545729
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3528390397
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2595759222
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1711427596
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.446432308
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.925081395
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3914054628
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2288668233
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3564918387
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2953569890
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3518882915
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4181141308
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2442272154
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1145183799
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.456525736
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.842505482
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1164476145
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2343659728
/workspace/coverage/default/0.sram_ctrl_alert_test.3925984785
/workspace/coverage/default/0.sram_ctrl_bijection.703154158
/workspace/coverage/default/0.sram_ctrl_executable.458844727
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2751138243
/workspace/coverage/default/0.sram_ctrl_max_throughput.1530365336
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1312822699
/workspace/coverage/default/0.sram_ctrl_mem_walk.2838465513
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2797331635
/workspace/coverage/default/0.sram_ctrl_partial_access.2093402176
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.570336754
/workspace/coverage/default/0.sram_ctrl_ram_cfg.859536445
/workspace/coverage/default/0.sram_ctrl_regwen.1911740901
/workspace/coverage/default/0.sram_ctrl_sec_cm.883580818
/workspace/coverage/default/0.sram_ctrl_smoke.2031829608
/workspace/coverage/default/0.sram_ctrl_stress_all.220879116
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.782735668
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3816921905
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3648497318
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4183154027
/workspace/coverage/default/1.sram_ctrl_alert_test.3628961453
/workspace/coverage/default/1.sram_ctrl_executable.2361250938
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1742553993
/workspace/coverage/default/1.sram_ctrl_max_throughput.1376110524
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3688320505
/workspace/coverage/default/1.sram_ctrl_mem_walk.2426322854
/workspace/coverage/default/1.sram_ctrl_multiple_keys.569267368
/workspace/coverage/default/1.sram_ctrl_partial_access.2369878420
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.271833755
/workspace/coverage/default/1.sram_ctrl_ram_cfg.265468178
/workspace/coverage/default/1.sram_ctrl_regwen.3689798428
/workspace/coverage/default/1.sram_ctrl_smoke.2021663143
/workspace/coverage/default/1.sram_ctrl_stress_all.1500684381
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.279810031
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1601351602
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.999000812
/workspace/coverage/default/10.sram_ctrl_bijection.1635200615
/workspace/coverage/default/10.sram_ctrl_executable.1174349918
/workspace/coverage/default/10.sram_ctrl_lc_escalation.379598015
/workspace/coverage/default/10.sram_ctrl_max_throughput.4287560298
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2089488910
/workspace/coverage/default/10.sram_ctrl_mem_walk.1663945605
/workspace/coverage/default/10.sram_ctrl_multiple_keys.660396613
/workspace/coverage/default/10.sram_ctrl_partial_access.4166348099
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2280890902
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1364298282
/workspace/coverage/default/10.sram_ctrl_regwen.1867369948
/workspace/coverage/default/10.sram_ctrl_smoke.1305252265
/workspace/coverage/default/10.sram_ctrl_stress_all.1296222179
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4206611242
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.553244388
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1806422909
/workspace/coverage/default/11.sram_ctrl_alert_test.111157605
/workspace/coverage/default/11.sram_ctrl_bijection.1568252923
/workspace/coverage/default/11.sram_ctrl_executable.3554932475
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1651491596
/workspace/coverage/default/11.sram_ctrl_max_throughput.1914828381
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2670970157
/workspace/coverage/default/11.sram_ctrl_mem_walk.1922727025
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3047150536
/workspace/coverage/default/11.sram_ctrl_partial_access.2840645200
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3986523122
/workspace/coverage/default/11.sram_ctrl_ram_cfg.723433788
/workspace/coverage/default/11.sram_ctrl_regwen.1838225170
/workspace/coverage/default/11.sram_ctrl_smoke.2746330177
/workspace/coverage/default/11.sram_ctrl_stress_all.2288691247
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.191469887
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2602198092
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.491612733
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1055928865
/workspace/coverage/default/12.sram_ctrl_alert_test.1942761239
/workspace/coverage/default/12.sram_ctrl_bijection.120723300
/workspace/coverage/default/12.sram_ctrl_executable.308329108
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/workspace/coverage/default/43.sram_ctrl_partial_access.734541252
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3639486056
/workspace/coverage/default/43.sram_ctrl_ram_cfg.201246144
/workspace/coverage/default/43.sram_ctrl_regwen.3522666558
/workspace/coverage/default/43.sram_ctrl_smoke.513851197
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3267769667
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.321068637
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2573083403
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3686151800
/workspace/coverage/default/44.sram_ctrl_alert_test.3402687935
/workspace/coverage/default/44.sram_ctrl_bijection.2002402918
/workspace/coverage/default/44.sram_ctrl_executable.3149876897
/workspace/coverage/default/44.sram_ctrl_max_throughput.2028960168
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2760212768
/workspace/coverage/default/44.sram_ctrl_mem_walk.3557818536
/workspace/coverage/default/44.sram_ctrl_multiple_keys.59194875
/workspace/coverage/default/44.sram_ctrl_partial_access.1959484342
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2207540000
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1719225550
/workspace/coverage/default/44.sram_ctrl_regwen.174170065
/workspace/coverage/default/44.sram_ctrl_smoke.3579989062
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1060424946
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2543833399
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2212938761
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1961901284
/workspace/coverage/default/45.sram_ctrl_alert_test.1916564957
/workspace/coverage/default/45.sram_ctrl_bijection.3296043623
/workspace/coverage/default/45.sram_ctrl_executable.2623721948
/workspace/coverage/default/45.sram_ctrl_max_throughput.861201769
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2142613147
/workspace/coverage/default/45.sram_ctrl_mem_walk.2941013066
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3089200968
/workspace/coverage/default/45.sram_ctrl_partial_access.1910351275
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3152191278
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3219210592
/workspace/coverage/default/45.sram_ctrl_smoke.661354576
/workspace/coverage/default/45.sram_ctrl_stress_all.2774974074
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3792219895
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3281561097
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4259560796
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3818715526
/workspace/coverage/default/46.sram_ctrl_alert_test.4088165092
/workspace/coverage/default/46.sram_ctrl_bijection.3102419791
/workspace/coverage/default/46.sram_ctrl_executable.22681108
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2986160297
/workspace/coverage/default/46.sram_ctrl_max_throughput.1024357143
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1196575928
/workspace/coverage/default/46.sram_ctrl_mem_walk.3197730421
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2300143666
/workspace/coverage/default/46.sram_ctrl_partial_access.4146397824
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.523178179
/workspace/coverage/default/46.sram_ctrl_regwen.2474997078
/workspace/coverage/default/46.sram_ctrl_smoke.450949936
/workspace/coverage/default/46.sram_ctrl_stress_all.2338813901
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.610311222
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.325603129
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1171234095
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3884004887
/workspace/coverage/default/47.sram_ctrl_alert_test.792756658
/workspace/coverage/default/47.sram_ctrl_bijection.200165924
/workspace/coverage/default/47.sram_ctrl_executable.3036468894
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3333496513
/workspace/coverage/default/47.sram_ctrl_max_throughput.2970408548
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1960771832
/workspace/coverage/default/47.sram_ctrl_mem_walk.259441818
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3433221977
/workspace/coverage/default/47.sram_ctrl_partial_access.1002218127
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.963534466
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3908069474
/workspace/coverage/default/47.sram_ctrl_regwen.2322482030
/workspace/coverage/default/47.sram_ctrl_smoke.358505068
/workspace/coverage/default/47.sram_ctrl_stress_all.581029424
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.16182429
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2839819918
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.48382073
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3565967936
/workspace/coverage/default/48.sram_ctrl_alert_test.1013699137
/workspace/coverage/default/48.sram_ctrl_bijection.668156368
/workspace/coverage/default/48.sram_ctrl_executable.2684393463
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1599840209
/workspace/coverage/default/48.sram_ctrl_max_throughput.1242372602
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2485409439
/workspace/coverage/default/48.sram_ctrl_mem_walk.3036601489
/workspace/coverage/default/48.sram_ctrl_multiple_keys.132499361
/workspace/coverage/default/48.sram_ctrl_partial_access.1909682839
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3436871613
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1973014640
/workspace/coverage/default/48.sram_ctrl_regwen.3767826034
/workspace/coverage/default/48.sram_ctrl_smoke.1026146024
/workspace/coverage/default/48.sram_ctrl_stress_all.649270050
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1444749317
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1490880898
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1210006778
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.388093729
/workspace/coverage/default/49.sram_ctrl_alert_test.934431777
/workspace/coverage/default/49.sram_ctrl_bijection.1289710211
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2241351258
/workspace/coverage/default/49.sram_ctrl_max_throughput.2421734721
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4105662655
/workspace/coverage/default/49.sram_ctrl_mem_walk.27069156
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3078996762
/workspace/coverage/default/49.sram_ctrl_partial_access.269258997
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.374296772
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3100268390
/workspace/coverage/default/49.sram_ctrl_regwen.1491848521
/workspace/coverage/default/49.sram_ctrl_smoke.3319346855
/workspace/coverage/default/49.sram_ctrl_stress_all.3808280999
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1627927086
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1145707805
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.387614814
/workspace/coverage/default/5.sram_ctrl_alert_test.2628758359
/workspace/coverage/default/5.sram_ctrl_bijection.4021825075
/workspace/coverage/default/5.sram_ctrl_executable.3145343720
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1558203994
/workspace/coverage/default/5.sram_ctrl_max_throughput.2368452079
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2955419825
/workspace/coverage/default/5.sram_ctrl_mem_walk.1840069786
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1338177538
/workspace/coverage/default/5.sram_ctrl_partial_access.3267110818
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2232744616
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3841994627
/workspace/coverage/default/5.sram_ctrl_regwen.3561157614
/workspace/coverage/default/5.sram_ctrl_smoke.1698641413
/workspace/coverage/default/5.sram_ctrl_stress_all.1741874123
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.328001007
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3551494102
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.977644835
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2663786146
/workspace/coverage/default/6.sram_ctrl_alert_test.2151395423
/workspace/coverage/default/6.sram_ctrl_bijection.4124757087
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1806968209
/workspace/coverage/default/6.sram_ctrl_max_throughput.1547541699
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3430523202
/workspace/coverage/default/6.sram_ctrl_mem_walk.2620051543
/workspace/coverage/default/6.sram_ctrl_multiple_keys.4248876648
/workspace/coverage/default/6.sram_ctrl_partial_access.488757296
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3989483929
/workspace/coverage/default/6.sram_ctrl_regwen.1666837407
/workspace/coverage/default/6.sram_ctrl_smoke.2292894155
/workspace/coverage/default/6.sram_ctrl_stress_all.4084169216
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4223462235
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.143412513
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4002362567
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3674694886
/workspace/coverage/default/7.sram_ctrl_alert_test.1863043095
/workspace/coverage/default/7.sram_ctrl_bijection.953145713
/workspace/coverage/default/7.sram_ctrl_executable.1645991776
/workspace/coverage/default/7.sram_ctrl_max_throughput.1735682864
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.165812937
/workspace/coverage/default/7.sram_ctrl_mem_walk.1755453297
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3312600261
/workspace/coverage/default/7.sram_ctrl_partial_access.1021135568
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.446017405
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2288914278
/workspace/coverage/default/7.sram_ctrl_regwen.3491350819
/workspace/coverage/default/7.sram_ctrl_smoke.343258951
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3192706445
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2966701350
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2714133248
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3572660021
/workspace/coverage/default/8.sram_ctrl_alert_test.134367323
/workspace/coverage/default/8.sram_ctrl_bijection.1580644423
/workspace/coverage/default/8.sram_ctrl_executable.658607621
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2865321041
/workspace/coverage/default/8.sram_ctrl_max_throughput.1277866020
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3312428714
/workspace/coverage/default/8.sram_ctrl_mem_walk.2902189708
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4238116780
/workspace/coverage/default/8.sram_ctrl_partial_access.820582280
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3578772584
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3856116806
/workspace/coverage/default/8.sram_ctrl_regwen.536072995
/workspace/coverage/default/8.sram_ctrl_smoke.3625577364
/workspace/coverage/default/8.sram_ctrl_stress_all.3430038572
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3130842796
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2805107541
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4292669821
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4254623831
/workspace/coverage/default/9.sram_ctrl_alert_test.341752529
/workspace/coverage/default/9.sram_ctrl_bijection.1272499994
/workspace/coverage/default/9.sram_ctrl_executable.3297735217
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1325504691
/workspace/coverage/default/9.sram_ctrl_max_throughput.2856289555
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3007856301
/workspace/coverage/default/9.sram_ctrl_mem_walk.2481841140
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1284722238
/workspace/coverage/default/9.sram_ctrl_partial_access.448886376
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1735058560
/workspace/coverage/default/9.sram_ctrl_ram_cfg.346571401
/workspace/coverage/default/9.sram_ctrl_regwen.2270360556
/workspace/coverage/default/9.sram_ctrl_stress_all.1982684482
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2335427747
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1644383126
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4079928984



Total test records in report: 1013
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/27.sram_ctrl_regwen.1480784735 Mar 12 03:01:22 PM PDT 24 Mar 12 03:14:02 PM PDT 24 7852417687 ps
T2 /workspace/coverage/default/9.sram_ctrl_smoke.2227242035 Mar 12 02:59:47 PM PDT 24 Mar 12 03:00:00 PM PDT 24 1840380517 ps
T3 /workspace/coverage/default/29.sram_ctrl_partial_access.3969432402 Mar 12 03:01:34 PM PDT 24 Mar 12 03:02:24 PM PDT 24 697087658 ps
T7 /workspace/coverage/default/48.sram_ctrl_mem_walk.3036601489 Mar 12 03:04:35 PM PDT 24 Mar 12 03:04:40 PM PDT 24 307314623 ps
T8 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3020866643 Mar 12 03:00:01 PM PDT 24 Mar 12 03:06:21 PM PDT 24 65215309536 ps
T9 /workspace/coverage/default/7.sram_ctrl_mem_walk.1755453297 Mar 12 02:59:47 PM PDT 24 Mar 12 02:59:58 PM PDT 24 677949351 ps
T10 /workspace/coverage/default/49.sram_ctrl_executable.913313846 Mar 12 03:04:42 PM PDT 24 Mar 12 03:21:56 PM PDT 24 3411839400 ps
T11 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2573083403 Mar 12 03:03:34 PM PDT 24 Mar 12 03:03:52 PM PDT 24 159724290 ps
T12 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.369150345 Mar 12 03:00:39 PM PDT 24 Mar 12 03:05:02 PM PDT 24 11341696357 ps
T13 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.495213428 Mar 12 02:59:29 PM PDT 24 Mar 12 03:02:30 PM PDT 24 1939914934 ps
T16 /workspace/coverage/default/15.sram_ctrl_partial_access.1261478324 Mar 12 02:59:54 PM PDT 24 Mar 12 03:00:03 PM PDT 24 203598580 ps
T17 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.425334468 Mar 12 03:01:24 PM PDT 24 Mar 12 03:02:03 PM PDT 24 452389079 ps
T34 /workspace/coverage/default/33.sram_ctrl_smoke.4038642160 Mar 12 03:02:02 PM PDT 24 Mar 12 03:02:07 PM PDT 24 69620218 ps
T29 /workspace/coverage/default/49.sram_ctrl_bijection.1289710211 Mar 12 03:04:35 PM PDT 24 Mar 12 03:05:26 PM PDT 24 3479247366 ps
T30 /workspace/coverage/default/1.sram_ctrl_bijection.2119922126 Mar 12 02:59:16 PM PDT 24 Mar 12 02:59:48 PM PDT 24 2969733400 ps
T18 /workspace/coverage/default/37.sram_ctrl_executable.983705756 Mar 12 03:02:53 PM PDT 24 Mar 12 03:13:28 PM PDT 24 6243288165 ps
T14 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.676967922 Mar 12 02:59:39 PM PDT 24 Mar 12 03:04:03 PM PDT 24 11829423409 ps
T37 /workspace/coverage/default/46.sram_ctrl_executable.22681108 Mar 12 03:04:11 PM PDT 24 Mar 12 03:24:21 PM PDT 24 9973332634 ps
T4 /workspace/coverage/default/37.sram_ctrl_lc_escalation.920605882 Mar 12 03:02:39 PM PDT 24 Mar 12 03:02:50 PM PDT 24 953885948 ps
T31 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2178219165 Mar 12 03:02:54 PM PDT 24 Mar 12 03:13:53 PM PDT 24 4125829211 ps
T60 /workspace/coverage/default/38.sram_ctrl_smoke.1369829980 Mar 12 03:02:53 PM PDT 24 Mar 12 03:03:05 PM PDT 24 152754543 ps
T15 /workspace/coverage/default/22.sram_ctrl_stress_all.2993206037 Mar 12 03:00:42 PM PDT 24 Mar 12 03:49:54 PM PDT 24 200611162223 ps
T61 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.165812937 Mar 12 02:59:37 PM PDT 24 Mar 12 02:59:41 PM PDT 24 81289109 ps
T62 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2355919026 Mar 12 03:02:20 PM PDT 24 Mar 12 03:02:43 PM PDT 24 366210885 ps
T38 /workspace/coverage/default/10.sram_ctrl_ram_cfg.1364298282 Mar 12 02:59:53 PM PDT 24 Mar 12 02:59:55 PM PDT 24 47581113 ps
T39 /workspace/coverage/default/46.sram_ctrl_ram_cfg.532832009 Mar 12 03:04:09 PM PDT 24 Mar 12 03:04:10 PM PDT 24 77329652 ps
T63 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3167260890 Mar 12 03:01:14 PM PDT 24 Mar 12 03:05:54 PM PDT 24 19534988992 ps
T64 /workspace/coverage/default/8.sram_ctrl_partial_access.820582280 Mar 12 02:59:48 PM PDT 24 Mar 12 03:00:06 PM PDT 24 303355504 ps
T32 /workspace/coverage/default/44.sram_ctrl_regwen.174170065 Mar 12 03:03:51 PM PDT 24 Mar 12 03:06:38 PM PDT 24 10399598757 ps
T5 /workspace/coverage/default/31.sram_ctrl_stress_all.1968946042 Mar 12 03:01:54 PM PDT 24 Mar 12 03:14:25 PM PDT 24 19416490529 ps
T78 /workspace/coverage/default/25.sram_ctrl_bijection.2091072948 Mar 12 03:00:47 PM PDT 24 Mar 12 03:01:14 PM PDT 24 6393814848 ps
T52 /workspace/coverage/default/14.sram_ctrl_executable.3301294210 Mar 12 02:59:53 PM PDT 24 Mar 12 03:22:22 PM PDT 24 30473700444 ps
T22 /workspace/coverage/default/15.sram_ctrl_alert_test.3135397059 Mar 12 02:59:54 PM PDT 24 Mar 12 02:59:55 PM PDT 24 157168433 ps
T144 /workspace/coverage/default/44.sram_ctrl_mem_walk.3557818536 Mar 12 03:03:55 PM PDT 24 Mar 12 03:04:00 PM PDT 24 1951345445 ps
T40 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2618683568 Mar 12 02:59:55 PM PDT 24 Mar 12 02:59:56 PM PDT 24 88235216 ps
T83 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1701771160 Mar 12 02:59:53 PM PDT 24 Mar 12 02:59:56 PM PDT 24 409189079 ps
T25 /workspace/coverage/default/44.sram_ctrl_alert_test.3402687935 Mar 12 03:03:51 PM PDT 24 Mar 12 03:03:52 PM PDT 24 59587583 ps
T145 /workspace/coverage/default/34.sram_ctrl_partial_access.883665969 Mar 12 03:02:22 PM PDT 24 Mar 12 03:02:33 PM PDT 24 658750629 ps
T65 /workspace/coverage/default/28.sram_ctrl_regwen.2880530766 Mar 12 03:01:32 PM PDT 24 Mar 12 03:22:20 PM PDT 24 27407287213 ps
T146 /workspace/coverage/default/27.sram_ctrl_smoke.2476266556 Mar 12 03:01:15 PM PDT 24 Mar 12 03:03:41 PM PDT 24 1471402205 ps
T23 /workspace/coverage/default/10.sram_ctrl_alert_test.3710552413 Mar 12 02:59:53 PM PDT 24 Mar 12 02:59:54 PM PDT 24 35274740 ps
T143 /workspace/coverage/default/44.sram_ctrl_bijection.2002402918 Mar 12 03:03:43 PM PDT 24 Mar 12 03:04:24 PM PDT 24 1895425480 ps
T137 /workspace/coverage/default/17.sram_ctrl_executable.3011848065 Mar 12 03:00:03 PM PDT 24 Mar 12 03:13:35 PM PDT 24 7270046280 ps
T101 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.325603129 Mar 12 03:04:10 PM PDT 24 Mar 12 03:07:54 PM PDT 24 6571420387 ps
T35 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.782735668 Mar 12 02:59:24 PM PDT 24 Mar 12 02:59:37 PM PDT 24 864927356 ps
T102 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3252194472 Mar 12 03:00:10 PM PDT 24 Mar 12 03:04:31 PM PDT 24 2648878305 ps
T103 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2602198092 Mar 12 02:59:51 PM PDT 24 Mar 12 03:02:33 PM PDT 24 3519727832 ps
T104 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1386325180 Mar 12 03:00:14 PM PDT 24 Mar 12 03:06:39 PM PDT 24 62168821662 ps
T117 /workspace/coverage/default/23.sram_ctrl_multiple_keys.4278806972 Mar 12 03:00:31 PM PDT 24 Mar 12 03:24:44 PM PDT 24 4359345629 ps
T6 /workspace/coverage/default/46.sram_ctrl_lc_escalation.2986160297 Mar 12 03:04:14 PM PDT 24 Mar 12 03:04:19 PM PDT 24 518388615 ps
T118 /workspace/coverage/default/32.sram_ctrl_ram_cfg.3033581464 Mar 12 03:02:03 PM PDT 24 Mar 12 03:02:05 PM PDT 24 63445376 ps
T33 /workspace/coverage/default/33.sram_ctrl_stress_all.2083787209 Mar 12 03:02:19 PM PDT 24 Mar 12 03:35:31 PM PDT 24 64120282877 ps
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T119 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4097763084 Mar 12 02:59:51 PM PDT 24 Mar 12 03:05:22 PM PDT 24 15403058463 ps
T147 /workspace/coverage/default/8.sram_ctrl_max_throughput.1277866020 Mar 12 02:59:39 PM PDT 24 Mar 12 03:01:40 PM PDT 24 477603493 ps
T36 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2760559762 Mar 12 03:01:23 PM PDT 24 Mar 12 03:03:40 PM PDT 24 2678390901 ps
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T148 /workspace/coverage/default/9.sram_ctrl_ram_cfg.346571401 Mar 12 02:59:43 PM PDT 24 Mar 12 02:59:43 PM PDT 24 48568349 ps
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T19 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2276333174 Mar 12 03:00:41 PM PDT 24 Mar 12 03:06:27 PM PDT 24 1903072044 ps
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T150 /workspace/coverage/default/3.sram_ctrl_smoke.2858949132 Mar 12 02:59:20 PM PDT 24 Mar 12 02:59:27 PM PDT 24 137227403 ps
T151 /workspace/coverage/default/18.sram_ctrl_smoke.3241779331 Mar 12 03:00:07 PM PDT 24 Mar 12 03:00:49 PM PDT 24 441707609 ps
T20 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3251706469 Mar 12 03:00:22 PM PDT 24 Mar 12 03:15:24 PM PDT 24 7914880263 ps
T21 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1994646014 Mar 12 02:59:51 PM PDT 24 Mar 12 03:13:22 PM PDT 24 9828317828 ps
T67 /workspace/coverage/default/20.sram_ctrl_regwen.3227963914 Mar 12 03:00:27 PM PDT 24 Mar 12 03:27:30 PM PDT 24 36735284879 ps
T53 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1141027103 Mar 12 03:00:58 PM PDT 24 Mar 12 03:02:34 PM PDT 24 7474695820 ps
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T153 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3353581574 Mar 12 02:59:53 PM PDT 24 Mar 12 03:03:27 PM PDT 24 2365905617 ps
T154 /workspace/coverage/default/34.sram_ctrl_bijection.4190410049 Mar 12 03:02:24 PM PDT 24 Mar 12 03:03:24 PM PDT 24 4236405444 ps
T84 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1876799598 Mar 12 03:00:48 PM PDT 24 Mar 12 03:00:52 PM PDT 24 126123315 ps
T24 /workspace/coverage/default/20.sram_ctrl_alert_test.1119782849 Mar 12 03:00:26 PM PDT 24 Mar 12 03:00:27 PM PDT 24 12353741 ps
T141 /workspace/coverage/default/26.sram_ctrl_partial_access.3868964662 Mar 12 03:00:59 PM PDT 24 Mar 12 03:02:39 PM PDT 24 3005371928 ps
T155 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3639486056 Mar 12 03:03:36 PM PDT 24 Mar 12 03:11:23 PM PDT 24 73201431358 ps
T85 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.387614814 Mar 12 02:59:39 PM PDT 24 Mar 12 03:20:52 PM PDT 24 14580815949 ps
T156 /workspace/coverage/default/24.sram_ctrl_mem_walk.1451868933 Mar 12 03:00:48 PM PDT 24 Mar 12 03:00:59 PM PDT 24 1753544413 ps
T157 /workspace/coverage/default/14.sram_ctrl_multiple_keys.667953907 Mar 12 02:59:56 PM PDT 24 Mar 12 03:13:15 PM PDT 24 5169934348 ps
T158 /workspace/coverage/default/39.sram_ctrl_max_throughput.535130373 Mar 12 03:03:01 PM PDT 24 Mar 12 03:04:50 PM PDT 24 268361883 ps
T159 /workspace/coverage/default/6.sram_ctrl_partial_access.488757296 Mar 12 02:59:50 PM PDT 24 Mar 12 03:00:00 PM PDT 24 1072647647 ps
T160 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.229088655 Mar 12 03:00:27 PM PDT 24 Mar 12 03:06:24 PM PDT 24 37180587526 ps
T161 /workspace/coverage/default/12.sram_ctrl_max_throughput.1867122645 Mar 12 02:59:49 PM PDT 24 Mar 12 03:01:42 PM PDT 24 1266369012 ps
T162 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2405261380 Mar 12 03:01:23 PM PDT 24 Mar 12 03:04:59 PM PDT 24 19147083872 ps
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T86 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3005135712 Mar 12 02:59:53 PM PDT 24 Mar 12 03:11:47 PM PDT 24 6602010691 ps
T164 /workspace/coverage/default/34.sram_ctrl_lc_escalation.38484073 Mar 12 03:02:21 PM PDT 24 Mar 12 03:02:32 PM PDT 24 2666418183 ps
T54 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.191469887 Mar 12 02:59:51 PM PDT 24 Mar 12 03:02:33 PM PDT 24 3329296083 ps
T165 /workspace/coverage/default/16.sram_ctrl_bijection.2746576991 Mar 12 03:00:01 PM PDT 24 Mar 12 03:00:58 PM PDT 24 2945590166 ps
T166 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2287068149 Mar 12 03:03:28 PM PDT 24 Mar 12 03:03:29 PM PDT 24 277776883 ps
T167 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1910495768 Mar 12 02:59:50 PM PDT 24 Mar 12 03:08:05 PM PDT 24 44818120401 ps
T168 /workspace/coverage/default/7.sram_ctrl_partial_access.1021135568 Mar 12 02:59:40 PM PDT 24 Mar 12 03:01:56 PM PDT 24 641792342 ps
T169 /workspace/coverage/default/6.sram_ctrl_regwen.1666837407 Mar 12 02:59:43 PM PDT 24 Mar 12 03:01:53 PM PDT 24 2238417408 ps
T87 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2670970157 Mar 12 02:59:53 PM PDT 24 Mar 12 02:59:59 PM PDT 24 161461031 ps
T170 /workspace/coverage/default/5.sram_ctrl_smoke.1698641413 Mar 12 02:59:46 PM PDT 24 Mar 12 03:00:14 PM PDT 24 349673961 ps
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T172 /workspace/coverage/default/39.sram_ctrl_alert_test.4227511697 Mar 12 03:03:08 PM PDT 24 Mar 12 03:03:10 PM PDT 24 64172563 ps
T173 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3432275568 Mar 12 03:02:53 PM PDT 24 Mar 12 03:07:51 PM PDT 24 8576475765 ps
T174 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3130637327 Mar 12 02:59:36 PM PDT 24 Mar 12 03:00:41 PM PDT 24 133836211 ps
T175 /workspace/coverage/default/40.sram_ctrl_regwen.3656654503 Mar 12 03:03:12 PM PDT 24 Mar 12 03:04:44 PM PDT 24 1911644399 ps
T176 /workspace/coverage/default/35.sram_ctrl_alert_test.1325298069 Mar 12 03:02:30 PM PDT 24 Mar 12 03:02:31 PM PDT 24 14238175 ps
T88 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3307997690 Mar 12 03:01:13 PM PDT 24 Mar 12 03:01:17 PM PDT 24 69246794 ps
T177 /workspace/coverage/default/22.sram_ctrl_max_throughput.2115222903 Mar 12 03:00:47 PM PDT 24 Mar 12 03:02:40 PM PDT 24 136301316 ps
T178 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1297567017 Mar 12 03:03:30 PM PDT 24 Mar 12 03:06:02 PM PDT 24 8607043984 ps
T179 /workspace/coverage/default/5.sram_ctrl_mem_walk.1840069786 Mar 12 02:59:53 PM PDT 24 Mar 12 02:59:57 PM PDT 24 279264327 ps
T180 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2191177223 Mar 12 03:00:05 PM PDT 24 Mar 12 03:03:10 PM PDT 24 20045589444 ps
T181 /workspace/coverage/default/49.sram_ctrl_partial_access.269258997 Mar 12 03:04:42 PM PDT 24 Mar 12 03:07:31 PM PDT 24 1420803631 ps
T182 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3557368745 Mar 12 02:59:52 PM PDT 24 Mar 12 03:01:29 PM PDT 24 616005951 ps
T183 /workspace/coverage/default/0.sram_ctrl_alert_test.3925984785 Mar 12 02:59:23 PM PDT 24 Mar 12 02:59:24 PM PDT 24 12173121 ps
T184 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.550026614 Mar 12 03:03:02 PM PDT 24 Mar 12 03:04:13 PM PDT 24 5105079643 ps
T185 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1921197257 Mar 12 03:00:12 PM PDT 24 Mar 12 03:00:16 PM PDT 24 111772273 ps
T186 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2629644330 Mar 12 03:00:04 PM PDT 24 Mar 12 03:07:13 PM PDT 24 38705906067 ps
T187 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3518902102 Mar 12 03:03:08 PM PDT 24 Mar 12 03:03:16 PM PDT 24 224618674 ps
T188 /workspace/coverage/default/33.sram_ctrl_bijection.138955476 Mar 12 03:02:04 PM PDT 24 Mar 12 03:03:17 PM PDT 24 9070794128 ps
T189 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.713626971 Mar 12 03:00:39 PM PDT 24 Mar 12 03:03:25 PM PDT 24 2290690258 ps
T135 /workspace/coverage/default/0.sram_ctrl_stress_all.220879116 Mar 12 02:59:23 PM PDT 24 Mar 12 04:03:41 PM PDT 24 495379230918 ps
T190 /workspace/coverage/default/17.sram_ctrl_alert_test.2841068234 Mar 12 03:00:06 PM PDT 24 Mar 12 03:00:07 PM PDT 24 14449543 ps
T191 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1755599839 Mar 12 03:00:40 PM PDT 24 Mar 12 03:00:59 PM PDT 24 112855105 ps
T192 /workspace/coverage/default/0.sram_ctrl_max_throughput.1530365336 Mar 12 02:59:12 PM PDT 24 Mar 12 03:00:12 PM PDT 24 429083403 ps
T193 /workspace/coverage/default/38.sram_ctrl_max_throughput.3834998757 Mar 12 03:02:53 PM PDT 24 Mar 12 03:02:54 PM PDT 24 55884208 ps
T194 /workspace/coverage/default/15.sram_ctrl_mem_walk.2475848774 Mar 12 03:00:00 PM PDT 24 Mar 12 03:00:06 PM PDT 24 817828532 ps
T195 /workspace/coverage/default/48.sram_ctrl_multiple_keys.132499361 Mar 12 03:04:27 PM PDT 24 Mar 12 03:14:38 PM PDT 24 6994993204 ps
T196 /workspace/coverage/default/25.sram_ctrl_ram_cfg.1611623014 Mar 12 03:00:49 PM PDT 24 Mar 12 03:00:50 PM PDT 24 51246046 ps
T197 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2431066240 Mar 12 03:00:29 PM PDT 24 Mar 12 03:00:41 PM PDT 24 214289663 ps
T198 /workspace/coverage/default/13.sram_ctrl_executable.2560017410 Mar 12 02:59:51 PM PDT 24 Mar 12 03:01:50 PM PDT 24 2815194515 ps
T199 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3410836386 Mar 12 02:59:53 PM PDT 24 Mar 12 03:09:57 PM PDT 24 3833206745 ps
T200 /workspace/coverage/default/2.sram_ctrl_bijection.3683190367 Mar 12 02:59:21 PM PDT 24 Mar 12 02:59:47 PM PDT 24 1189861750 ps
T55 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1691977234 Mar 12 03:00:39 PM PDT 24 Mar 12 03:04:07 PM PDT 24 12410100307 ps
T201 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2089488910 Mar 12 02:59:48 PM PDT 24 Mar 12 02:59:54 PM PDT 24 160803952 ps
T202 /workspace/coverage/default/17.sram_ctrl_lc_escalation.811172546 Mar 12 03:00:04 PM PDT 24 Mar 12 03:00:08 PM PDT 24 1236698530 ps
T203 /workspace/coverage/default/47.sram_ctrl_executable.3036468894 Mar 12 03:04:26 PM PDT 24 Mar 12 03:11:33 PM PDT 24 15144762079 ps
T136 /workspace/coverage/default/30.sram_ctrl_regwen.1156646382 Mar 12 03:01:40 PM PDT 24 Mar 12 03:16:23 PM PDT 24 62841046872 ps
T204 /workspace/coverage/default/3.sram_ctrl_multiple_keys.3810951857 Mar 12 02:59:38 PM PDT 24 Mar 12 03:24:22 PM PDT 24 19943661805 ps
T139 /workspace/coverage/default/28.sram_ctrl_stress_all.251930112 Mar 12 03:01:33 PM PDT 24 Mar 12 03:32:56 PM PDT 24 29647249661 ps
T205 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1490880898 Mar 12 03:04:26 PM PDT 24 Mar 12 03:10:10 PM PDT 24 3735918220 ps
T206 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.398570042 Mar 12 03:03:10 PM PDT 24 Mar 12 03:11:09 PM PDT 24 21890992373 ps
T207 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.626977764 Mar 12 03:01:14 PM PDT 24 Mar 12 03:01:58 PM PDT 24 116869858 ps
T208 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1952432289 Mar 12 03:00:43 PM PDT 24 Mar 12 03:01:49 PM PDT 24 230062079 ps
T209 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3172682494 Mar 12 03:01:45 PM PDT 24 Mar 12 03:04:26 PM PDT 24 620417218 ps
T210 /workspace/coverage/default/44.sram_ctrl_multiple_keys.59194875 Mar 12 03:03:44 PM PDT 24 Mar 12 03:18:36 PM PDT 24 3413170823 ps
T211 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1421458629 Mar 12 03:00:03 PM PDT 24 Mar 12 03:00:07 PM PDT 24 389166110 ps
T212 /workspace/coverage/default/21.sram_ctrl_max_throughput.1933457564 Mar 12 03:00:42 PM PDT 24 Mar 12 03:01:06 PM PDT 24 90934351 ps
T213 /workspace/coverage/default/41.sram_ctrl_executable.668492688 Mar 12 03:03:28 PM PDT 24 Mar 12 03:09:18 PM PDT 24 10357085749 ps
T214 /workspace/coverage/default/13.sram_ctrl_ram_cfg.134044315 Mar 12 02:59:56 PM PDT 24 Mar 12 02:59:59 PM PDT 24 197087732 ps
T215 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4259560796 Mar 12 03:04:00 PM PDT 24 Mar 12 03:04:53 PM PDT 24 258419425 ps
T216 /workspace/coverage/default/16.sram_ctrl_smoke.2316953046 Mar 12 03:00:13 PM PDT 24 Mar 12 03:00:55 PM PDT 24 494110477 ps
T217 /workspace/coverage/default/44.sram_ctrl_partial_access.1959484342 Mar 12 03:03:43 PM PDT 24 Mar 12 03:03:56 PM PDT 24 715692365 ps
T218 /workspace/coverage/default/47.sram_ctrl_mem_walk.259441818 Mar 12 03:04:32 PM PDT 24 Mar 12 03:04:42 PM PDT 24 1830809610 ps
T56 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3130842796 Mar 12 02:59:48 PM PDT 24 Mar 12 03:03:32 PM PDT 24 2926095740 ps
T219 /workspace/coverage/default/12.sram_ctrl_partial_access.2059685840 Mar 12 02:59:50 PM PDT 24 Mar 12 03:00:01 PM PDT 24 399471015 ps
T220 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2751138243 Mar 12 02:59:11 PM PDT 24 Mar 12 02:59:20 PM PDT 24 1342263072 ps
T221 /workspace/coverage/default/17.sram_ctrl_mem_walk.2277417788 Mar 12 03:00:05 PM PDT 24 Mar 12 03:00:11 PM PDT 24 1318921708 ps
T222 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3668799496 Mar 12 03:03:19 PM PDT 24 Mar 12 03:07:02 PM PDT 24 69034608389 ps
T57 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1060424946 Mar 12 03:03:55 PM PDT 24 Mar 12 03:07:13 PM PDT 24 3328767492 ps
T223 /workspace/coverage/default/35.sram_ctrl_multiple_keys.4031606421 Mar 12 03:02:19 PM PDT 24 Mar 12 03:14:55 PM PDT 24 2511811976 ps
T224 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1196575928 Mar 12 03:04:08 PM PDT 24 Mar 12 03:04:11 PM PDT 24 230263090 ps
T225 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2760212768 Mar 12 03:03:52 PM PDT 24 Mar 12 03:03:54 PM PDT 24 153503609 ps
T226 /workspace/coverage/default/17.sram_ctrl_multiple_keys.403942648 Mar 12 03:00:01 PM PDT 24 Mar 12 03:01:58 PM PDT 24 1277878506 ps
T227 /workspace/coverage/default/37.sram_ctrl_ram_cfg.671011501 Mar 12 03:02:54 PM PDT 24 Mar 12 03:02:55 PM PDT 24 26090762 ps
T228 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.388093729 Mar 12 03:04:44 PM PDT 24 Mar 12 03:18:26 PM PDT 24 2701880400 ps
T229 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.324840602 Mar 12 03:00:39 PM PDT 24 Mar 12 03:04:45 PM PDT 24 47115979299 ps
T58 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1444749317 Mar 12 03:04:34 PM PDT 24 Mar 12 03:07:26 PM PDT 24 414843619 ps
T230 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1158028329 Mar 12 03:03:02 PM PDT 24 Mar 12 03:20:01 PM PDT 24 57562740796 ps
T231 /workspace/coverage/default/31.sram_ctrl_alert_test.105124741 Mar 12 03:01:55 PM PDT 24 Mar 12 03:01:57 PM PDT 24 47219261 ps
T232 /workspace/coverage/default/2.sram_ctrl_smoke.4254313108 Mar 12 02:59:17 PM PDT 24 Mar 12 03:00:17 PM PDT 24 278277985 ps
T233 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3152191278 Mar 12 03:03:52 PM PDT 24 Mar 12 03:12:18 PM PDT 24 39971799031 ps
T234 /workspace/coverage/default/23.sram_ctrl_ram_cfg.3998293809 Mar 12 03:00:40 PM PDT 24 Mar 12 03:00:41 PM PDT 24 38526613 ps
T235 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1979083526 Mar 12 03:03:36 PM PDT 24 Mar 12 03:03:40 PM PDT 24 44076429 ps
T236 /workspace/coverage/default/38.sram_ctrl_alert_test.2749339106 Mar 12 03:03:01 PM PDT 24 Mar 12 03:03:01 PM PDT 24 15654121 ps
T237 /workspace/coverage/default/7.sram_ctrl_executable.1645991776 Mar 12 02:59:38 PM PDT 24 Mar 12 03:13:24 PM PDT 24 28653637245 ps
T238 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1397416045 Mar 12 03:00:43 PM PDT 24 Mar 12 03:20:15 PM PDT 24 15289582952 ps
T239 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4079928984 Mar 12 02:59:47 PM PDT 24 Mar 12 03:01:38 PM PDT 24 547526238 ps
T240 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1408464182 Mar 12 03:01:12 PM PDT 24 Mar 12 03:01:20 PM PDT 24 765186622 ps
T241 /workspace/coverage/default/32.sram_ctrl_regwen.3461617468 Mar 12 03:02:02 PM PDT 24 Mar 12 03:09:27 PM PDT 24 1301088270 ps
T242 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3689146923 Mar 12 03:00:18 PM PDT 24 Mar 12 03:00:20 PM PDT 24 184674643 ps
T243 /workspace/coverage/default/16.sram_ctrl_lc_escalation.1533550492 Mar 12 03:00:02 PM PDT 24 Mar 12 03:00:08 PM PDT 24 2121405696 ps
T59 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1506537551 Mar 12 03:00:29 PM PDT 24 Mar 12 03:02:59 PM PDT 24 1042587417 ps
T140 /workspace/coverage/default/24.sram_ctrl_regwen.1976985572 Mar 12 03:00:43 PM PDT 24 Mar 12 03:21:33 PM PDT 24 17764040307 ps
T244 /workspace/coverage/default/45.sram_ctrl_executable.2623721948 Mar 12 03:04:00 PM PDT 24 Mar 12 03:19:44 PM PDT 24 3829766513 ps
T245 /workspace/coverage/default/43.sram_ctrl_partial_access.734541252 Mar 12 03:05:00 PM PDT 24 Mar 12 03:05:06 PM PDT 24 169973545 ps
T246 /workspace/coverage/default/45.sram_ctrl_alert_test.1916564957 Mar 12 03:03:59 PM PDT 24 Mar 12 03:04:00 PM PDT 24 105467158 ps
T247 /workspace/coverage/default/10.sram_ctrl_lc_escalation.379598015 Mar 12 02:59:49 PM PDT 24 Mar 12 02:59:55 PM PDT 24 442953296 ps
T248 /workspace/coverage/default/19.sram_ctrl_mem_walk.3598320176 Mar 12 03:00:18 PM PDT 24 Mar 12 03:00:24 PM PDT 24 221751639 ps
T249 /workspace/coverage/default/24.sram_ctrl_partial_access.4142417574 Mar 12 03:00:43 PM PDT 24 Mar 12 03:03:50 PM PDT 24 541136016 ps
T250 /workspace/coverage/default/12.sram_ctrl_alert_test.1942761239 Mar 12 03:00:00 PM PDT 24 Mar 12 03:00:01 PM PDT 24 46868619 ps
T251 /workspace/coverage/default/33.sram_ctrl_regwen.3519746193 Mar 12 03:02:11 PM PDT 24 Mar 12 03:30:14 PM PDT 24 73120563498 ps
T252 /workspace/coverage/default/37.sram_ctrl_partial_access.131790946 Mar 12 03:03:53 PM PDT 24 Mar 12 03:04:02 PM PDT 24 505833853 ps
T253 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2843233935 Mar 12 03:01:22 PM PDT 24 Mar 12 03:01:27 PM PDT 24 159055921 ps
T254 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1742553993 Mar 12 02:59:43 PM PDT 24 Mar 12 02:59:45 PM PDT 24 1418568262 ps
T255 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1700732805 Mar 12 03:00:17 PM PDT 24 Mar 12 03:09:09 PM PDT 24 48594608726 ps
T256 /workspace/coverage/default/43.sram_ctrl_smoke.513851197 Mar 12 03:03:38 PM PDT 24 Mar 12 03:03:56 PM PDT 24 992450100 ps
T257 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.4121013701 Mar 12 03:00:49 PM PDT 24 Mar 12 03:06:36 PM PDT 24 1920810416 ps
T258 /workspace/coverage/default/3.sram_ctrl_mem_walk.2041948026 Mar 12 02:59:37 PM PDT 24 Mar 12 02:59:47 PM PDT 24 668804228 ps
T259 /workspace/coverage/default/16.sram_ctrl_stress_all.1724839965 Mar 12 03:00:00 PM PDT 24 Mar 12 03:17:19 PM PDT 24 78355561167 ps
T260 /workspace/coverage/default/41.sram_ctrl_smoke.2268528226 Mar 12 03:03:18 PM PDT 24 Mar 12 03:05:49 PM PDT 24 735747316 ps
T261 /workspace/coverage/default/16.sram_ctrl_regwen.2007333432 Mar 12 02:59:57 PM PDT 24 Mar 12 03:14:44 PM PDT 24 2716134449 ps
T262 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1145707805 Mar 12 03:04:45 PM PDT 24 Mar 12 03:04:46 PM PDT 24 40205627 ps
T263 /workspace/coverage/default/28.sram_ctrl_max_throughput.762376819 Mar 12 03:01:22 PM PDT 24 Mar 12 03:03:47 PM PDT 24 259636871 ps
T264 /workspace/coverage/default/17.sram_ctrl_bijection.1924308398 Mar 12 03:00:01 PM PDT 24 Mar 12 03:00:33 PM PDT 24 2003914455 ps
T265 /workspace/coverage/default/7.sram_ctrl_max_throughput.1735682864 Mar 12 02:59:42 PM PDT 24 Mar 12 02:59:52 PM PDT 24 78738770 ps
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T301 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3436871613 Mar 12 03:04:33 PM PDT 24 Mar 12 03:08:58 PM PDT 24 24481843139 ps
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T306 /workspace/coverage/default/21.sram_ctrl_regwen.3137536562 Mar 12 03:00:41 PM PDT 24 Mar 12 03:20:46 PM PDT 24 15538810565 ps
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