Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42179116	1			T1	43954		T2	7174		T3	1250
triple_byte_access	2474355	1			T1	828		T2	163		T3	1130
halfword_access	3712954	1			T1	1289		T2	203		T3	1683
byte_access	4958110	1			T1	1786		T2	281		T3	2341
zero_access	1248162	1			T1	433		T2	74		T3	573

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27231798

1

T1

24356

T2

3930

T3

3548

auto[1]

27340899

1

T1

23934

T2

3965

T3

3429

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21035816	1			T1	22105		T2	3585		T3	643
auto[0]	triple_byte_access	1234337	1			T1	423		T2	77		T3	578
auto[0]	halfword_access	1853250	1			T1	683		T2	97		T3	836
auto[0]	byte_access	2479315	1			T1	928		T2	141		T3	1192
auto[0]	zero_access	629080	1			T1	217		T2	30		T3	299
auto[1]	word_access	21143300	1			T1	21849		T2	3589		T3	607
auto[1]	triple_byte_access	1240018	1			T1	405		T2	86		T3	552
auto[1]	halfword_access	1859704	1			T1	606		T2	106		T3	847
auto[1]	byte_access	2478795	1			T1	858		T2	140		T3	1149
auto[1]	zero_access	619082	1			T1	216		T2	44		T3	274