Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14078863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60448204

1

T1

1131

T2

3071

T3

10000

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37140163	1			T1	3014		T2	1024		T3	4980
values[0x0]	17289351	1			T1	1078		T2	987		T3	2485
values[0x1]	20097553	1			T1	2113		T2	1060		T3	2535

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7017993	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67509074

1

T1

3693

T2

3071

T3

10000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	316553	1			T2	7		T3	33		T11	64
valid_sources[0x01]	298542	1			T2	7		T3	43		T11	73
valid_sources[0x02]	324929	1			T2	15		T3	50		T11	52
valid_sources[0x03]	353633	1			T2	16		T3	41		T11	50
valid_sources[0x04]	285981	1			T2	11		T3	21		T11	66
valid_sources[0x05]	256248	1			T2	7		T3	46		T11	64
valid_sources[0x06]	302060	1			T2	21		T3	24		T11	66
valid_sources[0x07]	323892	1			T2	11		T3	62		T11	56
valid_sources[0x08]	279556	1			T2	14		T3	36		T11	50
valid_sources[0x09]	264104	1			T2	21		T3	48		T11	56
valid_sources[0x0a]	274858	1			T2	11		T3	44		T11	51
valid_sources[0x0b]	263215	1			T2	12		T3	22		T11	49
valid_sources[0x0c]	395962	1			T2	9		T3	31		T11	73
valid_sources[0x0d]	287561	1			T2	11		T3	31		T11	58
valid_sources[0x0e]	289732	1			T2	15		T3	54		T11	61
valid_sources[0x0f]	283627	1			T2	11		T3	39		T11	56
valid_sources[0x10]	341571	1			T2	8		T3	39		T11	57
valid_sources[0x11]	322988	1			T2	11		T3	39		T11	41
valid_sources[0x12]	295310	1			T2	14		T3	23		T11	41
valid_sources[0x13]	297154	1			T2	7		T3	48		T11	48
valid_sources[0x14]	279739	1			T2	14		T3	49		T11	59
valid_sources[0x15]	339996	1			T2	15		T3	47		T11	57
valid_sources[0x16]	342466	1			T2	7		T3	35		T11	61
valid_sources[0x17]	277000	1			T2	11		T3	37		T11	73
valid_sources[0x18]	298550	1			T2	16		T3	50		T11	65
valid_sources[0x19]	274542	1			T2	8		T3	27		T11	65
valid_sources[0x1a]	266262	1			T2	13		T3	30		T11	62
valid_sources[0x1b]	262894	1			T2	25		T3	49		T11	54
valid_sources[0x1c]	285330	1			T2	8		T3	50		T11	52
valid_sources[0x1d]	286392	1			T2	15		T3	43		T11	50
valid_sources[0x1e]	287983	1			T2	10		T3	51		T11	53
valid_sources[0x1f]	293713	1			T2	14		T3	48		T11	63
valid_sources[0x20]	269057	1			T2	19		T3	34		T11	56
valid_sources[0x21]	281301	1			T2	29		T3	36		T11	44
valid_sources[0x22]	275937	1			T2	13		T3	37		T11	63
valid_sources[0x23]	260874	1			T2	13		T3	39		T11	59
valid_sources[0x24]	256554	1			T2	5		T3	32		T11	51
valid_sources[0x25]	308143	1			T2	10		T3	38		T11	58
valid_sources[0x26]	332935	1			T2	11		T3	41		T11	57
valid_sources[0x27]	297850	1			T2	8		T3	37		T11	61
valid_sources[0x28]	279183	1			T2	11		T3	40		T11	70
valid_sources[0x29]	263523	1			T2	20		T3	54		T11	48
valid_sources[0x2a]	265321	1			T2	11		T3	32		T11	58
valid_sources[0x2b]	338052	1			T2	13		T3	43		T11	44
valid_sources[0x2c]	288448	1			T2	20		T3	34		T11	58
valid_sources[0x2d]	274255	1			T2	17		T3	44		T11	55
valid_sources[0x2e]	277817	1			T2	9		T3	40		T11	51
valid_sources[0x2f]	278621	1			T2	11		T3	39		T11	57
valid_sources[0x30]	272981	1			T2	23		T3	38		T11	58
valid_sources[0x31]	270893	1			T2	13		T3	40		T11	62
valid_sources[0x32]	282987	1			T2	7		T3	51		T11	54
valid_sources[0x33]	309799	1			T2	13		T3	39		T11	45
valid_sources[0x34]	268344	1			T2	8		T3	24		T11	59
valid_sources[0x35]	279959	1			T2	12		T3	48		T11	47
valid_sources[0x36]	306877	1			T2	6		T3	22		T11	47
valid_sources[0x37]	285156	1			T2	9		T3	38		T11	59
valid_sources[0x38]	284379	1			T2	12		T3	42		T11	44
valid_sources[0x39]	273689	1			T2	15		T3	28		T11	54
valid_sources[0x3a]	254860	1			T2	12		T3	33		T11	64
valid_sources[0x3b]	321711	1			T2	5		T3	29		T11	57
valid_sources[0x3c]	269845	1			T2	9		T3	45		T11	63
valid_sources[0x3d]	295062	1			T2	20		T3	47		T11	50
valid_sources[0x3e]	255283	1			T2	10		T3	32		T11	47
valid_sources[0x3f]	359392	1			T2	10		T3	28		T11	62
valid_sources[0x40]	272714	1			T2	14		T3	31		T11	64
valid_sources[0x41]	272283	1			T2	18		T3	43		T11	61
valid_sources[0x42]	278761	1			T2	12		T3	39		T11	41
valid_sources[0x43]	326037	1			T2	11		T3	30		T11	48
valid_sources[0x44]	269653	1			T2	12		T3	40		T11	63
valid_sources[0x45]	331779	1			T2	12		T3	51		T11	54
valid_sources[0x46]	338331	1			T2	6		T3	44		T11	59
valid_sources[0x47]	288551	1			T2	12		T3	27		T11	63
valid_sources[0x48]	306922	1			T2	14		T3	39		T11	52
valid_sources[0x49]	301704	1			T2	25		T3	40		T11	47
valid_sources[0x4a]	279766	1			T2	13		T3	30		T11	50
valid_sources[0x4b]	260409	1			T2	13		T3	39		T11	36
valid_sources[0x4c]	297602	1			T2	14		T3	49		T11	52
valid_sources[0x4d]	270886	1			T2	5		T3	34		T11	50
valid_sources[0x4e]	296820	1			T2	7		T3	22		T11	54
valid_sources[0x4f]	298262	1			T2	13		T3	50		T11	57
valid_sources[0x50]	287782	1			T2	7		T3	31		T11	56
valid_sources[0x51]	265748	1			T2	15		T3	42		T11	43
valid_sources[0x52]	277075	1			T2	17		T3	33		T11	57
valid_sources[0x53]	374665	1			T2	15		T3	25		T11	66
valid_sources[0x54]	298787	1			T2	18		T3	26		T11	48
valid_sources[0x55]	275807	1			T2	14		T3	50		T11	47
valid_sources[0x56]	312247	1			T2	15		T3	35		T11	54
valid_sources[0x57]	310002	1			T2	15		T3	30		T11	59
valid_sources[0x58]	278468	1			T2	7		T3	27		T11	57
valid_sources[0x59]	263381	1			T2	9		T3	30		T11	53
valid_sources[0x5a]	271245	1			T2	10		T3	50		T11	51
valid_sources[0x5b]	287941	1			T2	8		T3	47		T11	63
valid_sources[0x5c]	268847	1			T2	13		T3	38		T11	59
valid_sources[0x5d]	266873	1			T1	10		T2	1		T3	55
valid_sources[0x5e]	283896	1			T2	12		T3	35		T11	56
valid_sources[0x5f]	268821	1			T2	10		T3	47		T11	60
valid_sources[0x60]	353318	1			T2	10		T3	33		T11	67
valid_sources[0x61]	282763	1			T2	8		T3	25		T11	41
valid_sources[0x62]	298430	1			T2	9		T3	56		T11	48
valid_sources[0x63]	291959	1			T2	13		T3	57		T11	58
valid_sources[0x64]	373928	1			T2	23		T3	48		T11	58
valid_sources[0x65]	290933	1			T2	12		T3	23		T11	50
valid_sources[0x66]	255864	1			T2	13		T3	42		T11	64
valid_sources[0x67]	282330	1			T2	16		T3	32		T11	52
valid_sources[0x68]	370016	1			T2	14		T3	24		T11	45
valid_sources[0x69]	263867	1			T2	13		T3	29		T11	66
valid_sources[0x6a]	259958	1			T2	11		T3	42		T11	57
valid_sources[0x6b]	300311	1			T1	1		T2	13		T3	30
valid_sources[0x6c]	276989	1			T2	10		T3	37		T11	45
valid_sources[0x6d]	309714	1			T2	10		T3	38		T11	44
valid_sources[0x6e]	296961	1			T2	16		T3	46		T11	64
valid_sources[0x6f]	287120	1			T2	21		T3	29		T11	46
valid_sources[0x70]	340280	1			T2	12		T3	49		T11	50
valid_sources[0x71]	348875	1			T2	12		T3	36		T11	67
valid_sources[0x72]	325338	1			T2	8		T3	31		T11	57
valid_sources[0x73]	273906	1			T2	14		T3	35		T11	50
valid_sources[0x74]	281124	1			T2	9		T3	39		T11	47
valid_sources[0x75]	286315	1			T2	7		T3	32		T11	53
valid_sources[0x76]	308987	1			T2	7		T3	36		T11	59
valid_sources[0x77]	286123	1			T2	5		T3	38		T11	53
valid_sources[0x78]	332356	1			T2	5		T3	39		T11	60
valid_sources[0x79]	280309	1			T2	3		T3	48		T11	63
valid_sources[0x7a]	269909	1			T2	15		T3	45		T11	57
valid_sources[0x7b]	272934	1			T2	11		T3	43		T11	42
valid_sources[0x7c]	310819	1			T2	12		T3	38		T11	60
valid_sources[0x7d]	296237	1			T2	5		T3	42		T11	67
valid_sources[0x7e]	322936	1			T2	15		T3	32		T11	53
valid_sources[0x7f]	259259	1			T2	3		T3	50		T11	67
valid_sources[0x80]	294225	1			T2	8		T3	49		T11	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30105966

1

T1

557

T2

1024

T3

4980

values[0x0]

all_enables

biggest_size

15174559

1

T1

305

T2

987

T3

2485

values[0x1]

all_enables

biggest_size

15167679

1

T1

269

T2

1060

T3

2535

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149509

1

T10

1

T12

4

T4

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53296	1			T4	58		T5	24		T7	34
values[0x0]	63713	1			T10	1		T11	4		T12	7
values[0x1]	67601	1			T1	2		T3	2		T10	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157967

1

T1

1

T3

1

T10

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	583	1			T18	5		T140	1		T28	3
valid_sources[0x01]	730	1			T11	1		T4	1		T5	1
valid_sources[0x02]	497	1			T4	4		T18	6		T28	1
valid_sources[0x03]	538	1			T18	1		T8	4		T138	1
valid_sources[0x04]	574	1			T5	1		T18	5		T20	2
valid_sources[0x05]	630	1			T4	2		T18	10		T28	2
valid_sources[0x06]	659	1			T5	1		T18	10		T140	1
valid_sources[0x07]	605	1			T18	2		T34	1		T28	1
valid_sources[0x08]	582	1			T18	7		T51	1		T8	1
valid_sources[0x09]	613	1			T18	4		T8	1		T28	3
valid_sources[0x0a]	1069	1			T18	5		T28	2		T29	14
valid_sources[0x0b]	831	1			T18	3		T8	1		T140	2
valid_sources[0x0c]	1048	1			T18	13		T140	1		T28	2
valid_sources[0x0d]	715	1			T18	6		T140	1		T145	4
valid_sources[0x0e]	688	1			T18	2		T29	8		T139	3
valid_sources[0x0f]	616	1			T18	1		T28	1		T29	12
valid_sources[0x10]	896	1			T18	4		T146	16		T53	1
valid_sources[0x11]	557	1			T18	7		T28	2		T29	8
valid_sources[0x12]	851	1			T18	4		T8	5		T147	1
valid_sources[0x13]	600	1			T4	3		T5	2		T18	5
valid_sources[0x14]	733	1			T18	9		T135	1		T145	2
valid_sources[0x15]	719	1			T18	10		T8	1		T29	5
valid_sources[0x16]	768	1			T4	5		T5	1		T18	4
valid_sources[0x17]	802	1			T18	4		T140	1		T100	1
valid_sources[0x18]	603	1			T18	7		T28	6		T29	13
valid_sources[0x19]	623	1			T18	2		T148	1		T140	1
valid_sources[0x1a]	749	1			T18	2		T27	4		T28	4
valid_sources[0x1b]	764	1			T18	5		T50	1		T29	12
valid_sources[0x1c]	616	1			T18	4		T54	1		T28	2
valid_sources[0x1d]	467	1			T18	8		T97	4		T29	6
valid_sources[0x1e]	775	1			T18	4		T28	1		T29	17
valid_sources[0x1f]	587	1			T18	5		T53	1		T28	6
valid_sources[0x20]	554	1			T18	2		T28	2		T29	21
valid_sources[0x21]	606	1			T5	1		T18	5		T54	1
valid_sources[0x22]	686	1			T18	2		T41	1		T98	1
valid_sources[0x23]	608	1			T18	6		T148	1		T28	7
valid_sources[0x24]	665	1			T18	6		T28	4		T29	11
valid_sources[0x25]	585	1			T18	2		T8	1		T149	2
valid_sources[0x26]	626	1			T5	2		T18	1		T29	11
valid_sources[0x27]	542	1			T18	2		T28	3		T29	8
valid_sources[0x28]	747	1			T4	2		T18	7		T27	1
valid_sources[0x29]	681	1			T5	1		T18	5		T148	1
valid_sources[0x2a]	1158	1			T5	4		T18	11		T150	1
valid_sources[0x2b]	681	1			T18	2		T28	1		T29	10
valid_sources[0x2c]	931	1			T4	1		T18	6		T136	2
valid_sources[0x2d]	990	1			T4	2		T18	3		T151	1
valid_sources[0x2e]	834	1			T5	1		T18	7		T41	1
valid_sources[0x2f]	597	1			T4	1		T18	2		T147	1
valid_sources[0x30]	897	1			T18	4		T54	1		T138	1
valid_sources[0x31]	610	1			T18	2		T8	1		T140	1
valid_sources[0x32]	682	1			T18	7		T29	5		T139	2
valid_sources[0x33]	759	1			T4	1		T5	1		T16	6
valid_sources[0x34]	875	1			T18	6		T54	1		T28	6
valid_sources[0x35]	821	1			T18	4		T8	1		T29	8
valid_sources[0x36]	550	1			T4	1		T18	3		T29	9
valid_sources[0x37]	732	1			T5	1		T18	7		T54	1
valid_sources[0x38]	594	1			T11	1		T18	5		T28	2
valid_sources[0x39]	867	1			T5	1		T18	1		T152	1
valid_sources[0x3a]	624	1			T18	11		T27	2		T147	1
valid_sources[0x3b]	710	1			T18	4		T28	1		T29	14
valid_sources[0x3c]	736	1			T5	1		T18	7		T27	1
valid_sources[0x3d]	542	1			T4	2		T5	1		T18	2
valid_sources[0x3e]	772	1			T5	2		T18	4		T51	1
valid_sources[0x3f]	765	1			T4	1		T5	2		T18	4
valid_sources[0x40]	828	1			T11	1		T18	11		T52	2
valid_sources[0x41]	803	1			T18	3		T52	1		T28	6
valid_sources[0x42]	958	1			T18	1		T97	1		T54	1
valid_sources[0x43]	803	1			T18	3		T153	7		T28	12
valid_sources[0x44]	773	1			T18	1		T137	1		T28	5
valid_sources[0x45]	558	1			T4	1		T18	7		T41	1
valid_sources[0x46]	698	1			T4	3		T5	1		T18	6
valid_sources[0x47]	529	1			T4	2		T18	5		T52	1
valid_sources[0x48]	749	1			T5	4		T28	5		T29	15
valid_sources[0x49]	677	1			T4	3		T18	10		T41	1
valid_sources[0x4a]	631	1			T18	4		T136	6		T28	12
valid_sources[0x4b]	481	1			T4	5		T18	1		T8	4
valid_sources[0x4c]	605	1			T11	1		T18	6		T52	1
valid_sources[0x4d]	664	1			T18	4		T147	2		T135	1
valid_sources[0x4e]	856	1			T18	4		T98	1		T137	2
valid_sources[0x4f]	712	1			T22	2		T142	2		T28	1
valid_sources[0x50]	799	1			T4	1		T5	1		T18	3
valid_sources[0x51]	866	1			T4	3		T18	6		T52	1
valid_sources[0x52]	601	1			T18	3		T29	9		T42	1
valid_sources[0x53]	818	1			T5	5		T18	3		T28	3
valid_sources[0x54]	629	1			T18	2		T8	2		T28	1
valid_sources[0x55]	943	1			T18	1		T27	6		T148	1
valid_sources[0x56]	868	1			T18	4		T28	1		T29	16
valid_sources[0x57]	562	1			T5	1		T18	1		T29	5
valid_sources[0x58]	649	1			T4	5		T18	1		T28	3
valid_sources[0x59]	554	1			T5	5		T18	3		T8	1
valid_sources[0x5a]	937	1			T18	8		T8	2		T28	1
valid_sources[0x5b]	718	1			T18	2		T140	1		T54	1
valid_sources[0x5c]	851	1			T18	2		T28	2		T29	17
valid_sources[0x5d]	832	1			T18	6		T154	1		T28	1
valid_sources[0x5e]	605	1			T18	2		T28	1		T29	10
valid_sources[0x5f]	599	1			T18	5		T135	2		T28	6
valid_sources[0x60]	796	1			T4	1		T52	2		T28	4
valid_sources[0x61]	776	1			T1	2		T4	3		T18	5
valid_sources[0x62]	718	1			T4	1		T18	5		T28	1
valid_sources[0x63]	634	1			T18	5		T67	1		T147	2
valid_sources[0x64]	581	1			T18	4		T145	1		T28	2
valid_sources[0x65]	651	1			T18	3		T8	1		T140	1
valid_sources[0x66]	526	1			T3	2		T5	3		T18	6
valid_sources[0x67]	615	1			T5	1		T18	3		T67	1
valid_sources[0x68]	778	1			T11	1		T4	1		T18	5
valid_sources[0x69]	829	1			T18	4		T150	1		T28	2
valid_sources[0x6a]	592	1			T18	6		T8	2		T28	1
valid_sources[0x6b]	696	1			T4	2		T5	1		T18	2
valid_sources[0x6c]	1069	1			T28	3		T29	14		T155	81
valid_sources[0x6d]	652	1			T18	6		T37	6		T138	1
valid_sources[0x6e]	524	1			T12	3		T18	2		T156	1
valid_sources[0x6f]	654	1			T18	6		T27	1		T147	1
valid_sources[0x70]	689	1			T18	4		T67	1		T28	3
valid_sources[0x71]	1064	1			T5	2		T18	8		T67	1
valid_sources[0x72]	552	1			T18	3		T140	1		T29	10
valid_sources[0x73]	597	1			T18	4		T151	1		T145	1
valid_sources[0x74]	907	1			T4	4		T18	3		T41	1
valid_sources[0x75]	779	1			T18	2		T8	4		T148	1
valid_sources[0x76]	763	1			T18	2		T153	2		T22	1
valid_sources[0x77]	603	1			T12	1		T18	1		T8	6
valid_sources[0x78]	809	1			T5	2		T18	3		T28	6
valid_sources[0x79]	881	1			T4	2		T5	1		T18	4
valid_sources[0x7a]	991	1			T18	7		T28	6		T29	14
valid_sources[0x7b]	751	1			T4	2		T18	4		T27	3
valid_sources[0x7c]	803	1			T4	1		T18	2		T9	80
valid_sources[0x7d]	665	1			T4	1		T18	5		T38	1
valid_sources[0x7e]	720	1			T5	2		T18	6		T30	1
valid_sources[0x7f]	720	1			T51	1		T66	1		T8	1
valid_sources[0x80]	809	1			T18	3		T140	1		T29	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40741

1

T4

35

T5

10

T7

13

values[0x0]

all_enables

biggest_size

55559

1

T12

3

T4

13

T5

10

values[0x1]

all_enables

biggest_size

53209

1

T10

1

T12

1

T4

15