Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13781789

1

T1

5074

T4

19808

T5

13568

full_word

55300257

1

T1

1131

T2

3071

T3

10000

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69081736	1			T1	6205		T2	3071		T3	10000
auto[TlIntgErrCmd]	99	1			T102	7		T103	9		T104	4
auto[TlIntgErrData]	103	1			T102	2		T103	2		T104	6
auto[TlIntgErrBoth]	108	1			T102	1		T103	9		T104	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31604866

1

T1

3014

T2

1024

T3

4980

auto[1]

37477180

1

T1

3191

T2

2047

T3

5020

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6570080	1			T1	2457		T4	7523		T5	5050
auto[TlIntgErrNone]	partial	auto[1]	7211429	1			T1	2617		T4	12285		T5	8518
auto[TlIntgErrNone]	full_word	auto[0]	25034655	1			T1	557		T2	1024		T3	4980
auto[TlIntgErrNone]	full_word	auto[1]	30265572	1			T1	574		T2	2047		T3	5020
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T102	4		T103	6		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T102	3		T103	3		T104	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T104	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T104	1		T131	2		T132	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T102	1		T103	1		T104	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T102	1		T104	3		T123	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T104	1		T132	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T103	1		T104	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T103	5		T104	3		T122	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T102	1		T103	4		T104	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T104	1		T129	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T128	1		T133	1		T134	1