Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	608100	1			T1	1		T6	305		T7	2674
auto[1]	10851778	1			T1	4		T3	4980		T4	706
auto[2]	515941	1			T1	2		T6	280		T7	2405
auto[3]	10775582	1			T1	3		T3	5019		T4	715

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14841340	1			T3	9999		T4	997		T5	9189
auto[1]	2170716	1			T1	2		T4	201		T5	951
auto[2]	2164295	1			T1	1		T4	192		T5	935
auto[3]	3575050	1			T1	7		T4	31		T5	69

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8799439

1

T1

10

T3

9988

T4

1419

auto[1]

13951962

1

T3

11

T4

2

T5

15

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	247280	1			T6	8		T7	2215		T18	111
auto[0]	auto[0]	auto[1]	25408	1			T6	50		T7	217		T18	14
auto[0]	auto[0]	auto[2]	25393	1			T6	43		T7	224		T18	12
auto[0]	auto[0]	auto[3]	7676	1			T1	1		T6	204		T7	16
auto[0]	auto[1]	auto[0]	3364875	1			T3	4975		T4	498		T5	4613
auto[0]	auto[1]	auto[1]	352541	1			T1	2		T4	136		T5	434
auto[0]	auto[1]	auto[2]	338163	1			T4	52		T5	446		T6	37
auto[0]	auto[1]	auto[3]	74332	1			T1	2		T4	19		T5	36
auto[0]	auto[2]	auto[0]	215062	1			T6	7		T7	2070		T18	91
auto[0]	auto[2]	auto[1]	22053	1			T6	31		T7	171		T18	14
auto[0]	auto[2]	auto[2]	20587	1			T6	42		T7	144		T18	8
auto[0]	auto[2]	auto[3]	6239	1			T1	2		T6	200		T7	18
auto[0]	auto[3]	auto[0]	3337906	1			T3	5013		T4	497		T5	4563
auto[0]	auto[3]	auto[1]	334614	1			T4	65		T5	515		T6	13
auto[0]	auto[3]	auto[2]	348998	1			T1	1		T4	140		T5	489
auto[0]	auto[3]	auto[3]	78312	1			T1	2		T4	12		T5	33
auto[1]	auto[0]	auto[0]	10251	1			T27	1		T66	1		T34	497
auto[1]	auto[0]	auto[1]	44906	1			T7	1		T34	2172		T121	3
auto[1]	auto[0]	auto[2]	45087	1			T7	1		T34	2184		T8	1
auto[1]	auto[0]	auto[3]	202099	1			T34	9617		T8	1		T73	3
auto[1]	auto[1]	auto[0]	3829357	1			T3	5		T4	1		T5	3
auto[1]	auto[1]	auto[1]	692549	1			T5	2		T16	7932		T17	1
auto[1]	auto[1]	auto[2]	664127	1			T16	8463		T19	1		T49	1
auto[1]	auto[1]	auto[3]	1535834	1			T16	777		T34	11302		T36	1
auto[1]	auto[2]	auto[0]	8799	1			T7	2		T27	1		T66	1
auto[1]	auto[2]	auto[1]	39359	1			T34	1283		T142	1		T121	1
auto[1]	auto[2]	auto[2]	37043	1			T34	2388		T121	1		T143	1
auto[1]	auto[2]	auto[3]	166799	1			T34	10599		T141	10815		T144	10507
auto[1]	auto[3]	auto[0]	3827810	1			T3	6		T4	1		T5	10
auto[1]	auto[3]	auto[1]	659286	1			T16	8707		T17	2		T19	1
auto[1]	auto[3]	auto[2]	684897	1			T16	7797		T21	2		T34	2813
auto[1]	auto[3]	auto[3]	1503759	1			T16	807		T49	1		T50	1