Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	309885157	144371	0	0
ctrl_regwen_rd_A	309885157	5781	0	0
exec_rd_A	309885157	5372	0	0
exec_regwen_rd_A	309885157	5881	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309885157	144371	0	0
T18	93406	1653	0	0
T19	12994	0	0	0
T20	21050	0	0	0
T21	269374	0	0	0
T27	107393	0	0	0
T28	0	994	0	0
T29	0	3588	0	0
T30	2612	0	0	0
T42	0	4533	0	0
T43	0	1139	0	0
T44	0	586	0	0
T45	0	4756	0	0
T46	0	1537	0	0
T47	0	3140	0	0
T48	0	3881	0	0
T49	8671	0	0	0
T50	8906	0	0	0
T51	674705	0	0	0
T52	45895	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309885157	5781	0	0
T42	248439	1027	0	0
T44	0	88	0	0
T76	5761	0	0	0
T105	0	204	0	0
T106	0	538	0	0
T107	0	183	0	0
T108	0	734	0	0
T109	0	161	0	0
T110	0	386	0	0
T111	0	539	0	0
T112	0	198	0	0
T113	5400	0	0	0
T114	840659	0	0	0
T115	44393	0	0	0
T116	47668	0	0	0
T117	9648	0	0	0
T118	556737	0	0	0
T119	356154	0	0	0
T120	5141	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309885157	5372	0	0
T42	248439	929	0	0
T44	0	110	0	0
T76	5761	0	0	0
T105	0	191	0	0
T106	0	544	0	0
T107	0	216	0	0
T108	0	663	0	0
T109	0	179	0	0
T110	0	328	0	0
T111	0	415	0	0
T112	0	145	0	0
T113	5400	0	0	0
T114	840659	0	0	0
T115	44393	0	0	0
T116	47668	0	0	0
T117	9648	0	0	0
T118	556737	0	0	0
T119	356154	0	0	0
T120	5141	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309885157	5881	0	0
T42	248439	1121	0	0
T44	0	82	0	0
T76	5761	0	0	0
T105	0	251	0	0
T106	0	562	0	0
T107	0	156	0	0
T108	0	669	0	0
T109	0	193	0	0
T110	0	313	0	0
T111	0	564	0	0
T112	0	209	0	0
T113	5400	0	0	0
T114	840659	0	0	0
T115	44393	0	0	0
T116	47668	0	0	0
T117	9648	0	0	0
T118	556737	0	0	0
T119	356154	0	0	0
T120	5141	0	0	0