Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14052859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58330267

1

T2

189658

T4

175263

T6

22528

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36079050	1			T2	104116		T4	96183		T6	11264
values[0x0]	16743876	1			T2	50072		T4	46440		T6	5552
values[0x1]	19560200	1			T2	54525		T4	49952		T6	5712

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7002224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65380902

1

T2

199370

T4

183864

T6

22528

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	255826	1			T2	811		T6	76		T13	14
valid_sources[0x01]	327034	1			T2	766		T6	82		T13	45
valid_sources[0x02]	257763	1			T2	916		T6	80		T13	34
valid_sources[0x03]	299309	1			T2	814		T6	88		T13	27
valid_sources[0x04]	269930	1			T2	886		T6	82		T13	45
valid_sources[0x05]	274824	1			T2	832		T6	75		T13	14
valid_sources[0x06]	275437	1			T2	823		T6	74		T13	21
valid_sources[0x07]	275829	1			T2	963		T6	85		T13	24
valid_sources[0x08]	290059	1			T2	848		T6	87		T13	15
valid_sources[0x09]	254354	1			T2	758		T6	101		T13	21
valid_sources[0x0a]	311645	1			T2	969		T4	41		T6	82
valid_sources[0x0b]	306462	1			T2	864		T6	74		T13	21
valid_sources[0x0c]	302690	1			T2	870		T4	3495		T6	68
valid_sources[0x0d]	274624	1			T2	712		T6	88		T13	35
valid_sources[0x0e]	377944	1			T2	720		T6	89		T13	36
valid_sources[0x0f]	303484	1			T2	739		T4	1064		T6	88
valid_sources[0x10]	250634	1			T2	739		T6	71		T13	32
valid_sources[0x11]	283159	1			T2	758		T4	2559		T6	85
valid_sources[0x12]	242303	1			T2	769		T6	96		T13	25
valid_sources[0x13]	336078	1			T2	853		T6	82		T13	28
valid_sources[0x14]	268881	1			T2	831		T6	104		T13	24
valid_sources[0x15]	260169	1			T2	890		T6	106		T13	16
valid_sources[0x16]	265892	1			T2	931		T6	62		T13	19
valid_sources[0x17]	266570	1			T2	760		T6	75		T13	32
valid_sources[0x18]	254984	1			T2	795		T6	102		T13	22
valid_sources[0x19]	265306	1			T2	812		T6	64		T13	35
valid_sources[0x1a]	263528	1			T2	753		T6	93		T13	22
valid_sources[0x1b]	257305	1			T2	785		T6	81		T13	16
valid_sources[0x1c]	279514	1			T2	839		T4	5054		T6	90
valid_sources[0x1d]	236656	1			T2	749		T6	86		T13	46
valid_sources[0x1e]	237548	1			T2	802		T6	72		T13	19
valid_sources[0x1f]	265392	1			T2	843		T6	109		T13	29
valid_sources[0x20]	366431	1			T2	837		T6	89		T13	5
valid_sources[0x21]	286724	1			T2	833		T6	85		T13	17
valid_sources[0x22]	263279	1			T2	681		T6	120		T13	8
valid_sources[0x23]	306663	1			T2	810		T6	93		T13	30
valid_sources[0x24]	287327	1			T2	818		T6	86		T13	19
valid_sources[0x25]	275503	1			T2	789		T6	98		T13	27
valid_sources[0x26]	296420	1			T2	825		T6	100		T13	21
valid_sources[0x27]	263947	1			T2	810		T4	2498		T6	72
valid_sources[0x28]	258973	1			T2	753		T4	36		T6	77
valid_sources[0x29]	245170	1			T2	930		T6	104		T13	6
valid_sources[0x2a]	295575	1			T2	901		T6	80		T13	26
valid_sources[0x2b]	272392	1			T2	814		T6	105		T13	19
valid_sources[0x2c]	304370	1			T2	984		T4	55		T6	101
valid_sources[0x2d]	266693	1			T2	993		T6	99		T13	36
valid_sources[0x2e]	273552	1			T2	716		T6	72		T13	28
valid_sources[0x2f]	313498	1			T2	939		T6	93		T13	32
valid_sources[0x30]	316323	1			T2	739		T6	88		T13	37
valid_sources[0x31]	254729	1			T2	853		T6	78		T13	12
valid_sources[0x32]	233758	1			T2	957		T6	87		T13	24
valid_sources[0x33]	256679	1			T2	912		T6	99		T13	7
valid_sources[0x34]	317396	1			T2	924		T6	91		T13	22
valid_sources[0x35]	257133	1			T2	676		T6	89		T13	33
valid_sources[0x36]	239526	1			T2	910		T6	104		T13	32
valid_sources[0x37]	272180	1			T2	1001		T6	76		T13	11
valid_sources[0x38]	242339	1			T2	722		T6	85		T13	9
valid_sources[0x39]	249165	1			T2	891		T6	83		T13	17
valid_sources[0x3a]	254211	1			T2	815		T6	106		T13	27
valid_sources[0x3b]	347614	1			T2	847		T6	65		T13	19
valid_sources[0x3c]	278260	1			T2	701		T6	103		T13	40
valid_sources[0x3d]	338748	1			T2	730		T6	82		T13	30
valid_sources[0x3e]	340518	1			T2	941		T6	116		T13	18
valid_sources[0x3f]	365463	1			T2	813		T6	86		T13	16
valid_sources[0x40]	272841	1			T2	825		T6	97		T13	21
valid_sources[0x41]	289863	1			T2	678		T6	111		T13	6
valid_sources[0x42]	268297	1			T2	752		T6	92		T13	28
valid_sources[0x43]	256520	1			T2	743		T6	90		T13	30
valid_sources[0x44]	257517	1			T2	728		T6	78		T13	50
valid_sources[0x45]	308583	1			T2	629		T6	80		T13	21
valid_sources[0x46]	398673	1			T2	855		T6	79		T12	10240
valid_sources[0x47]	277643	1			T2	841		T6	102		T13	27
valid_sources[0x48]	292473	1			T2	906		T6	94		T13	11
valid_sources[0x49]	249907	1			T2	840		T6	78		T13	26
valid_sources[0x4a]	306164	1			T2	817		T6	101		T13	19
valid_sources[0x4b]	253571	1			T2	887		T4	26		T6	79
valid_sources[0x4c]	269371	1			T2	716		T6	95		T13	37
valid_sources[0x4d]	379365	1			T2	860		T6	88		T13	22
valid_sources[0x4e]	276426	1			T2	782		T6	91		T13	29
valid_sources[0x4f]	257140	1			T2	837		T6	95		T13	31
valid_sources[0x50]	282477	1			T2	709		T6	64		T13	17
valid_sources[0x51]	267264	1			T2	694		T6	99		T13	15
valid_sources[0x52]	282610	1			T2	794		T6	87		T13	22
valid_sources[0x53]	272593	1			T2	670		T6	100		T13	20
valid_sources[0x54]	258271	1			T2	830		T6	93		T13	24
valid_sources[0x55]	259334	1			T2	689		T6	98		T13	28
valid_sources[0x56]	355766	1			T2	952		T6	116		T13	18
valid_sources[0x57]	250561	1			T2	1036		T6	82		T13	27
valid_sources[0x58]	305671	1			T2	877		T6	93		T13	27
valid_sources[0x59]	271775	1			T2	861		T6	88		T13	31
valid_sources[0x5a]	262983	1			T2	731		T6	105		T13	38
valid_sources[0x5b]	260451	1			T2	721		T6	110		T13	30
valid_sources[0x5c]	279866	1			T2	760		T6	63		T13	11
valid_sources[0x5d]	286483	1			T2	768		T6	67		T13	16
valid_sources[0x5e]	287179	1			T2	789		T6	69		T13	18
valid_sources[0x5f]	418717	1			T2	785		T6	103		T13	23
valid_sources[0x60]	259016	1			T2	825		T6	91		T13	32
valid_sources[0x61]	249300	1			T2	835		T6	98		T13	16
valid_sources[0x62]	292008	1			T2	907		T4	22288		T6	84
valid_sources[0x63]	265085	1			T2	850		T6	87		T13	36
valid_sources[0x64]	266067	1			T2	761		T6	76		T13	38
valid_sources[0x65]	238349	1			T2	765		T6	69		T13	26
valid_sources[0x66]	252382	1			T2	774		T6	128		T13	35
valid_sources[0x67]	279307	1			T2	1036		T6	80		T13	20
valid_sources[0x68]	252972	1			T2	825		T6	120		T13	23
valid_sources[0x69]	289285	1			T2	852		T6	61		T13	7
valid_sources[0x6a]	267960	1			T2	915		T6	77		T13	24
valid_sources[0x6b]	240145	1			T2	695		T6	85		T13	13
valid_sources[0x6c]	246734	1			T2	896		T4	89		T6	93
valid_sources[0x6d]	325611	1			T2	742		T6	100		T5	2066
valid_sources[0x6e]	293699	1			T2	785		T4	2306		T6	83
valid_sources[0x6f]	270468	1			T2	810		T6	101		T13	19
valid_sources[0x70]	316709	1			T2	924		T6	95		T13	23
valid_sources[0x71]	251878	1			T2	704		T6	114		T13	13
valid_sources[0x72]	249699	1			T2	839		T4	64		T6	98
valid_sources[0x73]	367538	1			T2	959		T4	57396		T6	92
valid_sources[0x74]	294166	1			T2	683		T4	74		T6	107
valid_sources[0x75]	241006	1			T2	739		T6	84		T13	23
valid_sources[0x76]	309895	1			T2	669		T6	63		T13	16
valid_sources[0x77]	238118	1			T2	910		T6	81		T13	25
valid_sources[0x78]	277656	1			T2	984		T4	170		T6	91
valid_sources[0x79]	343020	1			T2	698		T6	97		T13	16
valid_sources[0x7a]	270866	1			T2	902		T6	89		T13	16
valid_sources[0x7b]	317427	1			T2	828		T6	91		T13	30
valid_sources[0x7c]	295023	1			T2	871		T6	88		T13	30
valid_sources[0x7d]	281866	1			T2	773		T6	66		T13	21
valid_sources[0x7e]	300886	1			T2	822		T6	67		T13	25
valid_sources[0x7f]	289638	1			T2	734		T6	94		T13	13
valid_sources[0x80]	319378	1			T2	742		T6	90		T13	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29057441

1

T2

94562

T4

87670

T6

11264

values[0x0]

all_enables

biggest_size

14632441

1

T2

47293

T4

43759

T6

5552

values[0x1]

all_enables

biggest_size

14640385

1

T2

47803

T4

43834

T6

5712

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

137460

1

T2

7

T4

10

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49929	1			T17	8		T21	2		T8	13
values[0x0]	58626	1			T2	15		T3	1		T4	18
values[0x1]	62434	1			T1	1		T2	21		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25663	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145326

1

T2

10

T4

11

T11

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	892	1			T2	1		T29	9		T30	18
valid_sources[0x01]	584	1			T15	1		T29	12		T57	1
valid_sources[0x02]	719	1			T29	12		T9	2		T30	14
valid_sources[0x03]	614	1			T14	1		T29	20		T30	18
valid_sources[0x04]	540	1			T2	2		T29	2		T30	10
valid_sources[0x05]	842	1			T15	1		T29	17		T10	1
valid_sources[0x06]	984	1			T29	14		T30	16		T31	9
valid_sources[0x07]	866	1			T29	13		T30	15		T31	8
valid_sources[0x08]	659	1			T29	8		T10	1		T30	16
valid_sources[0x09]	892	1			T29	6		T30	25		T31	7
valid_sources[0x0a]	948	1			T29	3		T30	15		T31	9
valid_sources[0x0b]	549	1			T29	10		T30	19		T31	10
valid_sources[0x0c]	584	1			T2	2		T17	1		T29	16
valid_sources[0x0d]	793	1			T17	1		T29	18		T58	1
valid_sources[0x0e]	532	1			T2	1		T29	5		T30	13
valid_sources[0x0f]	784	1			T29	9		T10	1		T30	20
valid_sources[0x10]	626	1			T29	6		T30	16		T31	5
valid_sources[0x11]	550	1			T15	1		T29	21		T30	15
valid_sources[0x12]	732	1			T29	4		T30	14		T148	13
valid_sources[0x13]	479	1			T6	1		T29	14		T10	1
valid_sources[0x14]	750	1			T29	22		T57	1		T30	24
valid_sources[0x15]	516	1			T29	14		T53	1		T10	2
valid_sources[0x16]	595	1			T29	12		T53	2		T10	3
valid_sources[0x17]	748	1			T6	1		T17	1		T29	21
valid_sources[0x18]	829	1			T29	12		T9	1		T30	11
valid_sources[0x19]	549	1			T29	26		T10	4		T30	14
valid_sources[0x1a]	454	1			T29	24		T30	15		T31	12
valid_sources[0x1b]	589	1			T29	12		T10	1		T30	18
valid_sources[0x1c]	953	1			T29	6		T30	30		T31	9
valid_sources[0x1d]	788	1			T17	3		T29	26		T30	28
valid_sources[0x1e]	550	1			T29	20		T30	13		T31	11
valid_sources[0x1f]	628	1			T29	13		T30	15		T143	12
valid_sources[0x20]	599	1			T29	12		T30	14		T31	16
valid_sources[0x21]	519	1			T6	1		T15	1		T29	10
valid_sources[0x22]	535	1			T15	1		T29	22		T9	1
valid_sources[0x23]	826	1			T29	18		T9	1		T30	21
valid_sources[0x24]	542	1			T15	1		T29	10		T30	26
valid_sources[0x25]	570	1			T29	13		T57	1		T30	13
valid_sources[0x26]	602	1			T29	20		T53	1		T30	16
valid_sources[0x27]	566	1			T29	7		T9	1		T30	12
valid_sources[0x28]	600	1			T17	2		T29	5		T30	14
valid_sources[0x29]	620	1			T29	14		T9	2		T10	1
valid_sources[0x2a]	558	1			T2	1		T15	1		T29	18
valid_sources[0x2b]	562	1			T2	2		T61	4		T29	8
valid_sources[0x2c]	887	1			T6	1		T29	9		T30	10
valid_sources[0x2d]	635	1			T29	10		T30	19		T31	6
valid_sources[0x2e]	673	1			T29	10		T27	1		T30	17
valid_sources[0x2f]	587	1			T29	16		T9	3		T53	1
valid_sources[0x30]	622	1			T15	1		T29	8		T10	2
valid_sources[0x31]	511	1			T12	1		T29	8		T30	19
valid_sources[0x32]	643	1			T29	7		T9	1		T30	10
valid_sources[0x33]	575	1			T29	11		T9	1		T10	1
valid_sources[0x34]	544	1			T3	1		T29	21		T10	3
valid_sources[0x35]	526	1			T2	2		T29	4		T9	1
valid_sources[0x36]	716	1			T29	12		T57	2		T10	1
valid_sources[0x37]	477	1			T6	1		T29	15		T10	1
valid_sources[0x38]	662	1			T11	3		T29	5		T9	1
valid_sources[0x39]	800	1			T29	6		T9	1		T30	13
valid_sources[0x3a]	691	1			T11	1		T29	21		T10	1
valid_sources[0x3b]	520	1			T29	2		T10	3		T30	16
valid_sources[0x3c]	598	1			T29	18		T10	1		T30	17
valid_sources[0x3d]	576	1			T29	10		T9	2		T10	3
valid_sources[0x3e]	549	1			T29	10		T30	17		T31	6
valid_sources[0x3f]	841	1			T17	1		T20	1		T29	13
valid_sources[0x40]	1021	1			T29	15		T30	16		T31	11
valid_sources[0x41]	1187	1			T29	10		T9	4		T10	2
valid_sources[0x42]	720	1			T29	11		T30	14		T31	9
valid_sources[0x43]	564	1			T15	1		T97	1		T29	20
valid_sources[0x44]	512	1			T17	1		T29	17		T9	1
valid_sources[0x45]	808	1			T29	15		T30	21		T31	17
valid_sources[0x46]	703	1			T29	9		T30	16		T31	9
valid_sources[0x47]	556	1			T17	1		T15	1		T9	1
valid_sources[0x48]	561	1			T17	1		T14	1		T15	1
valid_sources[0x49]	777	1			T21	1		T29	32		T30	19
valid_sources[0x4a]	562	1			T4	8		T8	4		T29	11
valid_sources[0x4b]	533	1			T29	18		T9	4		T53	1
valid_sources[0x4c]	516	1			T29	5		T9	2		T30	24
valid_sources[0x4d]	481	1			T62	1		T29	16		T30	17
valid_sources[0x4e]	899	1			T29	14		T30	12		T31	9
valid_sources[0x4f]	595	1			T29	9		T10	1		T30	25
valid_sources[0x50]	533	1			T29	17		T30	18		T31	14
valid_sources[0x51]	513	1			T29	13		T30	13		T31	12
valid_sources[0x52]	704	1			T29	32		T10	3		T30	15
valid_sources[0x53]	671	1			T17	1		T29	16		T9	2
valid_sources[0x54]	684	1			T19	4		T21	1		T29	17
valid_sources[0x55]	1051	1			T29	10		T30	13		T31	5
valid_sources[0x56]	675	1			T29	13		T9	2		T30	17
valid_sources[0x57]	437	1			T6	1		T15	1		T29	12
valid_sources[0x58]	912	1			T2	5		T29	9		T9	1
valid_sources[0x59]	523	1			T2	1		T29	13		T30	7
valid_sources[0x5a]	721	1			T29	14		T30	14		T31	12
valid_sources[0x5b]	912	1			T8	7		T29	22		T9	1
valid_sources[0x5c]	913	1			T29	8		T30	16		T31	3
valid_sources[0x5d]	514	1			T29	9		T10	1		T30	24
valid_sources[0x5e]	578	1			T29	11		T9	1		T10	2
valid_sources[0x5f]	653	1			T29	15		T30	15		T31	6
valid_sources[0x60]	605	1			T2	1		T29	12		T58	1
valid_sources[0x61]	856	1			T2	1		T29	36		T30	12
valid_sources[0x62]	521	1			T15	1		T29	19		T30	10
valid_sources[0x63]	530	1			T29	8		T27	1		T30	20
valid_sources[0x64]	1303	1			T19	1		T29	18		T30	22
valid_sources[0x65]	612	1			T29	14		T10	1		T30	24
valid_sources[0x66]	670	1			T29	21		T9	1		T10	1
valid_sources[0x67]	847	1			T15	1		T29	20		T30	24
valid_sources[0x68]	572	1			T17	1		T29	7		T9	1
valid_sources[0x69]	834	1			T29	13		T9	1		T10	7
valid_sources[0x6a]	611	1			T16	1		T29	8		T30	18
valid_sources[0x6b]	545	1			T21	1		T29	13		T30	15
valid_sources[0x6c]	705	1			T29	19		T27	1		T30	20
valid_sources[0x6d]	723	1			T2	1		T3	1		T29	7
valid_sources[0x6e]	495	1			T18	1		T29	20		T30	14
valid_sources[0x6f]	673	1			T11	1		T29	7		T9	3
valid_sources[0x70]	589	1			T17	2		T29	4		T9	1
valid_sources[0x71]	540	1			T29	15		T9	1		T30	21
valid_sources[0x72]	531	1			T29	3		T53	1		T10	1
valid_sources[0x73]	618	1			T29	7		T27	1		T10	2
valid_sources[0x74]	547	1			T29	12		T30	15		T103	1
valid_sources[0x75]	582	1			T29	11		T9	1		T30	16
valid_sources[0x76]	657	1			T29	17		T30	13		T31	5
valid_sources[0x77]	611	1			T6	1		T17	1		T29	4
valid_sources[0x78]	731	1			T29	20		T9	2		T30	21
valid_sources[0x79]	760	1			T29	5		T9	1		T30	18
valid_sources[0x7a]	691	1			T4	6		T29	12		T30	26
valid_sources[0x7b]	523	1			T8	2		T29	8		T9	2
valid_sources[0x7c]	910	1			T29	14		T10	1		T30	15
valid_sources[0x7d]	526	1			T2	1		T29	8		T9	4
valid_sources[0x7e]	789	1			T29	21		T30	15		T31	11
valid_sources[0x7f]	679	1			T29	13		T10	2		T30	19
valid_sources[0x80]	857	1			T29	11		T9	2		T30	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37909

1

T17

5

T21

1

T8

6

values[0x0]

all_enables

biggest_size

50764

1

T2

4

T4

5

T6

2

values[0x1]

all_enables

biggest_size

48787

1

T2

3

T4

5

T11

1