Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13728541

1

T2

19055

T4

17312

T5

756

full_word

53176227

1

T2

189658

T4

175263

T6

22528

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66904438	1			T2	208713		T4	192575		T6	22528
auto[TlIntgErrCmd]	122	1			T111	8		T112	4		T113	9
auto[TlIntgErrData]	101	1			T111	6		T112	3		T113	3
auto[TlIntgErrBoth]	107	1			T111	6		T112	3		T113	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30522967

1

T2

104116

T4

96183

T6

11264

auto[1]

36381801

1

T2

104597

T4

96392

T6

11264

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6551113	1			T2	9554		T4	8513		T5	388
auto[TlIntgErrNone]	partial	auto[1]	7177131	1			T2	9501		T4	8799		T5	368
auto[TlIntgErrNone]	full_word	auto[0]	23971706	1			T2	94562		T4	87670		T6	11264
auto[TlIntgErrNone]	full_word	auto[1]	29204488	1			T2	95096		T4	87593		T6	11264
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T111	1		T112	1		T113	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T111	6		T112	2		T113	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T111	1		T134	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T112	1		T134	1		T138	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T111	2		T113	1		T134	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T111	3		T112	3		T113	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T111	1		T133	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T113	1		T134	1		T135	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T111	4		T112	2		T113	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T111	2		T112	1		T113	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T134	1		T135	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T132	1		T140	1		T138	1