Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	648213	1			T14	750		T15	1279		T16	26169
auto[1]	10363486	1			T2	67054		T4	44442		T5	2063
auto[2]	545442	1			T14	560		T15	1181		T16	22432
auto[3]	10277453	1			T2	67405		T4	44613		T5	2069

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13594368	1			T2	110952		T4	73811		T5	2777
auto[1]	2143292	1			T2	11338		T4	7297		T5	599
auto[2]	2137529	1			T2	11054		T4	7208		T5	614
auto[3]	3959405	1			T2	1115		T4	739		T5	142

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8298154

1

T2

134346

T4

88954

T5

4129

auto[1]

13536440

1

T2

113

T4

101

T5

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	296090	1			T14	20		T15	1028		T44	3778
auto[0]	auto[0]	auto[1]	30018	1			T14	115		T15	122		T44	359
auto[0]	auto[0]	auto[2]	29826	1			T14	108		T15	118		T44	324
auto[0]	auto[0]	auto[3]	6502	1			T14	506		T15	11		T16	4
auto[0]	auto[1]	auto[0]	3109383	1			T2	55128		T4	36904		T5	1375
auto[0]	auto[1]	auto[1]	329878	1			T2	5783		T4	3611		T5	298
auto[0]	auto[1]	auto[2]	315844	1			T2	5505		T4	3528		T5	312
auto[0]	auto[1]	auto[3]	79915	1			T2	580		T4	351		T5	76
auto[0]	auto[2]	auto[0]	252886	1			T14	20		T15	991		T44	3572
auto[0]	auto[2]	auto[1]	25650	1			T14	110		T15	116		T44	327
auto[0]	auto[2]	auto[2]	24547	1			T14	78		T15	66		T16	3
auto[0]	auto[2]	auto[3]	5122	1			T14	352		T15	8		T16	2
auto[0]	auto[3]	auto[0]	3070881	1			T2	55730		T4	36822		T5	1400
auto[0]	auto[3]	auto[1]	311200	1			T2	5550		T4	3679		T5	300
auto[0]	auto[3]	auto[2]	326394	1			T2	5535		T4	3671		T5	302
auto[0]	auto[3]	auto[3]	84018	1			T2	535		T4	388		T5	66
auto[1]	auto[0]	auto[0]	9553	1			T16	823		T44	4		T145	1
auto[1]	auto[0]	auto[1]	42259	1			T16	3830		T144	3416		T141	1
auto[1]	auto[0]	auto[2]	42202	1			T16	3909		T44	1		T45	1
auto[1]	auto[0]	auto[3]	191763	1			T14	1		T16	17603		T78	3
auto[1]	auto[1]	auto[0]	3423590	1			T2	49		T4	40		T5	2
auto[1]	auto[1]	auto[1]	698289	1			T2	3		T4	2		T19	3
auto[1]	auto[1]	auto[2]	672714	1			T2	6		T4	6		T21	1
auto[1]	auto[1]	auto[3]	1733873	1			T14	1		T61	514		T94	1
auto[1]	auto[2]	auto[0]	8923	1			T16	815		T44	2		T45	5
auto[1]	auto[2]	auto[1]	38415	1			T16	3533		T45	1		T60	1
auto[1]	auto[2]	auto[2]	34560	1			T16	3236		T44	2		T45	3
auto[1]	auto[2]	auto[3]	155339	1			T16	14843		T144	13005		T146	2
auto[1]	auto[3]	auto[0]	3423062	1			T2	45		T4	45		T19	19
auto[1]	auto[3]	auto[1]	667583	1			T2	2		T4	5		T5	1
auto[1]	auto[3]	auto[2]	691442	1			T2	8		T4	3		T61	5312
auto[1]	auto[3]	auto[3]	1702873	1			T19	1		T61	528		T97	9622