Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	319639304	126838	0	0
ctrl_regwen_rd_A	319639304	4055	0	0
exec_rd_A	319639304	3952	0	0
exec_regwen_rd_A	319639304	4357	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319639304	126838	0	0
T9	481168	0	0	0
T27	148981	0	0	0
T29	116502	4100	0	0
T30	0	5321	0	0
T31	0	2763	0	0
T46	0	807	0	0
T47	0	2378	0	0
T48	0	3340	0	0
T49	0	3179	0	0
T50	0	3148	0	0
T51	0	3992	0	0
T52	0	4821	0	0
T53	238681	0	0	0
T54	29979	0	0	0
T55	232154	0	0	0
T56	7548	0	0	0
T57	280993	0	0	0
T58	21895	0	0	0
T59	67399	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319639304	4055	0	0
T47	157214	373	0	0
T50	0	583	0	0
T83	6801	0	0	0
T111	0	79	0	0
T114	0	145	0	0
T115	0	210	0	0
T116	0	501	0	0
T117	0	74	0	0
T118	0	210	0	0
T119	0	275	0	0
T120	0	28	0	0
T121	132671	0	0	0
T122	1213	0	0	0
T123	49012	0	0	0
T124	254726	0	0	0
T125	77844	0	0	0
T126	99152	0	0	0
T127	43775	0	0	0
T128	157638	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319639304	3952	0	0
T47	157214	309	0	0
T50	0	384	0	0
T83	6801	0	0	0
T111	0	85	0	0
T114	0	104	0	0
T115	0	320	0	0
T116	0	503	0	0
T117	0	86	0	0
T118	0	173	0	0
T119	0	336	0	0
T120	0	32	0	0
T121	132671	0	0	0
T122	1213	0	0	0
T123	49012	0	0	0
T124	254726	0	0	0
T125	77844	0	0	0
T126	99152	0	0	0
T127	43775	0	0	0
T128	157638	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319639304	4357	0	0
T47	157214	423	0	0
T50	0	503	0	0
T83	6801	0	0	0
T111	0	87	0	0
T114	0	123	0	0
T115	0	214	0	0
T116	0	599	0	0
T117	0	98	0	0
T118	0	198	0	0
T119	0	381	0	0
T120	0	40	0	0
T121	132671	0	0	0
T122	1213	0	0	0
T123	49012	0	0	0
T124	254726	0	0	0
T125	77844	0	0	0
T126	99152	0	0	0
T127	43775	0	0	0
T128	157638	0	0	0