| T798 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1497302434 |
|
|
Mar 19 01:26:52 PM PDT 24 |
Mar 19 01:30:54 PM PDT 24 |
9028935670 ps |
| T799 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1456261478 |
|
|
Mar 19 01:25:06 PM PDT 24 |
Mar 19 01:30:20 PM PDT 24 |
54463853123 ps |
| T800 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2466091982 |
|
|
Mar 19 01:22:11 PM PDT 24 |
Mar 19 01:22:13 PM PDT 24 |
28756202 ps |
| T801 |
/workspace/coverage/default/34.sram_ctrl_executable.928246056 |
|
|
Mar 19 01:26:08 PM PDT 24 |
Mar 19 01:45:35 PM PDT 24 |
16812268683 ps |
| T802 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1291416952 |
|
|
Mar 19 01:22:45 PM PDT 24 |
Mar 19 01:22:51 PM PDT 24 |
1116286697 ps |
| T803 |
/workspace/coverage/default/40.sram_ctrl_bijection.2040465617 |
|
|
Mar 19 01:27:06 PM PDT 24 |
Mar 19 01:28:00 PM PDT 24 |
1486192496 ps |
| T804 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2179886388 |
|
|
Mar 19 01:24:16 PM PDT 24 |
Mar 19 01:24:58 PM PDT 24 |
406541629 ps |
| T805 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2684540759 |
|
|
Mar 19 01:24:37 PM PDT 24 |
Mar 19 01:32:16 PM PDT 24 |
18275131257 ps |
| T806 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4060336944 |
|
|
Mar 19 01:28:02 PM PDT 24 |
Mar 19 01:28:03 PM PDT 24 |
28633398 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_bijection.219916322 |
|
|
Mar 19 01:28:10 PM PDT 24 |
Mar 19 01:29:13 PM PDT 24 |
5813680984 ps |
| T808 |
/workspace/coverage/default/4.sram_ctrl_stress_all.512423777 |
|
|
Mar 19 01:21:21 PM PDT 24 |
Mar 19 02:00:46 PM PDT 24 |
98141345757 ps |
| T809 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2018504813 |
|
|
Mar 19 01:25:21 PM PDT 24 |
Mar 19 02:18:35 PM PDT 24 |
26133519884 ps |
| T810 |
/workspace/coverage/default/32.sram_ctrl_executable.3817692925 |
|
|
Mar 19 01:25:41 PM PDT 24 |
Mar 19 01:42:07 PM PDT 24 |
2741617567 ps |
| T811 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.818252581 |
|
|
Mar 19 01:21:35 PM PDT 24 |
Mar 19 01:21:45 PM PDT 24 |
567199375 ps |
| T812 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1847349577 |
|
|
Mar 19 01:22:09 PM PDT 24 |
Mar 19 01:22:10 PM PDT 24 |
32336169 ps |
| T813 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3209766046 |
|
|
Mar 19 01:25:16 PM PDT 24 |
Mar 19 01:48:38 PM PDT 24 |
12566986259 ps |
| T814 |
/workspace/coverage/default/17.sram_ctrl_smoke.3053414690 |
|
|
Mar 19 01:22:47 PM PDT 24 |
Mar 19 01:23:00 PM PDT 24 |
200266115 ps |
| T815 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1807916741 |
|
|
Mar 19 01:27:27 PM PDT 24 |
Mar 19 01:27:29 PM PDT 24 |
14902158 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.951290025 |
|
|
Mar 19 01:21:07 PM PDT 24 |
Mar 19 01:21:12 PM PDT 24 |
154669282 ps |
| T817 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1851233598 |
|
|
Mar 19 01:28:09 PM PDT 24 |
Mar 19 01:49:09 PM PDT 24 |
3702983870 ps |
| T818 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.1648845769 |
|
|
Mar 19 01:24:20 PM PDT 24 |
Mar 19 01:24:29 PM PDT 24 |
2058943280 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1284415534 |
|
|
Mar 19 01:21:23 PM PDT 24 |
Mar 19 01:21:52 PM PDT 24 |
459978800 ps |
| T820 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2543948052 |
|
|
Mar 19 01:21:48 PM PDT 24 |
Mar 19 01:22:09 PM PDT 24 |
965568251 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1081021566 |
|
|
Mar 19 01:25:35 PM PDT 24 |
Mar 19 01:28:07 PM PDT 24 |
6449284380 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_stress_all.712245950 |
|
|
Mar 19 01:21:28 PM PDT 24 |
Mar 19 01:43:38 PM PDT 24 |
33533780531 ps |
| T823 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.188027427 |
|
|
Mar 19 01:24:04 PM PDT 24 |
Mar 19 01:24:15 PM PDT 24 |
922775484 ps |
| T824 |
/workspace/coverage/default/32.sram_ctrl_smoke.944943857 |
|
|
Mar 19 01:25:37 PM PDT 24 |
Mar 19 01:25:51 PM PDT 24 |
279741302 ps |
| T825 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4058993213 |
|
|
Mar 19 01:26:38 PM PDT 24 |
Mar 19 01:26:47 PM PDT 24 |
1033912846 ps |
| T826 |
/workspace/coverage/default/27.sram_ctrl_executable.3999201895 |
|
|
Mar 19 01:24:38 PM PDT 24 |
Mar 19 01:39:26 PM PDT 24 |
3010800341 ps |
| T827 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2050596005 |
|
|
Mar 19 01:25:15 PM PDT 24 |
Mar 19 01:33:37 PM PDT 24 |
20155609559 ps |
| T828 |
/workspace/coverage/default/1.sram_ctrl_smoke.78057753 |
|
|
Mar 19 01:21:07 PM PDT 24 |
Mar 19 01:21:19 PM PDT 24 |
207765289 ps |
| T829 |
/workspace/coverage/default/47.sram_ctrl_executable.1932030944 |
|
|
Mar 19 01:28:44 PM PDT 24 |
Mar 19 01:29:29 PM PDT 24 |
4641534579 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1023041310 |
|
|
Mar 19 01:21:31 PM PDT 24 |
Mar 19 01:27:57 PM PDT 24 |
9612712059 ps |
| T831 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1221902244 |
|
|
Mar 19 01:21:21 PM PDT 24 |
Mar 19 01:21:22 PM PDT 24 |
31165083 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3412278582 |
|
|
Mar 19 01:27:21 PM PDT 24 |
Mar 19 01:29:06 PM PDT 24 |
262428686 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1228427084 |
|
|
Mar 19 01:24:56 PM PDT 24 |
Mar 19 01:34:16 PM PDT 24 |
17147227365 ps |
| T834 |
/workspace/coverage/default/22.sram_ctrl_bijection.3913593849 |
|
|
Mar 19 01:23:34 PM PDT 24 |
Mar 19 01:23:58 PM PDT 24 |
409735872 ps |
| T835 |
/workspace/coverage/default/19.sram_ctrl_regwen.4004455792 |
|
|
Mar 19 01:23:07 PM PDT 24 |
Mar 19 01:44:19 PM PDT 24 |
6894536194 ps |
| T836 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4080194857 |
|
|
Mar 19 01:27:25 PM PDT 24 |
Mar 19 01:27:33 PM PDT 24 |
625506996 ps |
| T837 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3034937484 |
|
|
Mar 19 01:25:20 PM PDT 24 |
Mar 19 01:26:21 PM PDT 24 |
1870063117 ps |
| T838 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1941428789 |
|
|
Mar 19 01:23:58 PM PDT 24 |
Mar 19 01:24:46 PM PDT 24 |
131118516 ps |
| T839 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.67467664 |
|
|
Mar 19 01:25:55 PM PDT 24 |
Mar 19 01:30:27 PM PDT 24 |
1361595215 ps |
| T840 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1902596152 |
|
|
Mar 19 01:24:38 PM PDT 24 |
Mar 19 01:24:43 PM PDT 24 |
67180764 ps |
| T841 |
/workspace/coverage/default/45.sram_ctrl_smoke.1539144708 |
|
|
Mar 19 01:28:12 PM PDT 24 |
Mar 19 01:28:50 PM PDT 24 |
90035997 ps |
| T842 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1080058907 |
|
|
Mar 19 01:28:04 PM PDT 24 |
Mar 19 01:28:14 PM PDT 24 |
2360191032 ps |
| T843 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3388983379 |
|
|
Mar 19 01:22:13 PM PDT 24 |
Mar 19 01:33:31 PM PDT 24 |
4293395749 ps |
| T844 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1819312038 |
|
|
Mar 19 01:26:51 PM PDT 24 |
Mar 19 01:30:34 PM PDT 24 |
879133754 ps |
| T119 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2388988116 |
|
|
Mar 19 01:23:12 PM PDT 24 |
Mar 19 01:24:42 PM PDT 24 |
6332219772 ps |
| T845 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.305390780 |
|
|
Mar 19 01:28:38 PM PDT 24 |
Mar 19 01:29:03 PM PDT 24 |
302897753 ps |
| T846 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2693193238 |
|
|
Mar 19 01:25:53 PM PDT 24 |
Mar 19 01:29:10 PM PDT 24 |
2693929025 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1175304203 |
|
|
Mar 19 01:22:15 PM PDT 24 |
Mar 19 01:22:20 PM PDT 24 |
144315706 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2803172769 |
|
|
Mar 19 01:24:12 PM PDT 24 |
Mar 19 01:29:15 PM PDT 24 |
26153215843 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2872487366 |
|
|
Mar 19 01:28:24 PM PDT 24 |
Mar 19 01:28:25 PM PDT 24 |
23872437 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_executable.1591472773 |
|
|
Mar 19 01:21:03 PM PDT 24 |
Mar 19 01:41:54 PM PDT 24 |
31387045531 ps |
| T851 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3334187869 |
|
|
Mar 19 01:24:01 PM PDT 24 |
Mar 19 01:24:13 PM PDT 24 |
215310111 ps |
| T852 |
/workspace/coverage/default/2.sram_ctrl_regwen.2131315677 |
|
|
Mar 19 01:21:17 PM PDT 24 |
Mar 19 01:37:24 PM PDT 24 |
5324471891 ps |
| T853 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2307108877 |
|
|
Mar 19 01:23:34 PM PDT 24 |
Mar 19 01:23:35 PM PDT 24 |
19049067 ps |
| T854 |
/workspace/coverage/default/31.sram_ctrl_executable.3219126881 |
|
|
Mar 19 01:25:33 PM PDT 24 |
Mar 19 01:29:18 PM PDT 24 |
2917610637 ps |
| T855 |
/workspace/coverage/default/44.sram_ctrl_executable.2048119440 |
|
|
Mar 19 01:28:10 PM PDT 24 |
Mar 19 01:34:17 PM PDT 24 |
2096704300 ps |
| T856 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3361339384 |
|
|
Mar 19 01:25:46 PM PDT 24 |
Mar 19 01:25:49 PM PDT 24 |
160442341 ps |
| T857 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.951721525 |
|
|
Mar 19 01:22:11 PM PDT 24 |
Mar 19 01:22:17 PM PDT 24 |
379212339 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2931667844 |
|
|
Mar 19 01:26:07 PM PDT 24 |
Mar 19 01:26:17 PM PDT 24 |
1032736139 ps |
| T859 |
/workspace/coverage/default/14.sram_ctrl_smoke.2302146754 |
|
|
Mar 19 01:22:15 PM PDT 24 |
Mar 19 01:22:21 PM PDT 24 |
266741267 ps |
| T860 |
/workspace/coverage/default/10.sram_ctrl_regwen.3161937252 |
|
|
Mar 19 01:21:56 PM PDT 24 |
Mar 19 01:49:16 PM PDT 24 |
12948606451 ps |
| T861 |
/workspace/coverage/default/26.sram_ctrl_smoke.4006342059 |
|
|
Mar 19 01:24:19 PM PDT 24 |
Mar 19 01:24:38 PM PDT 24 |
254518751 ps |
| T862 |
/workspace/coverage/default/0.sram_ctrl_regwen.2734809407 |
|
|
Mar 19 01:21:03 PM PDT 24 |
Mar 19 01:32:05 PM PDT 24 |
3642370353 ps |
| T863 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.923000880 |
|
|
Mar 19 01:21:13 PM PDT 24 |
Mar 19 01:21:47 PM PDT 24 |
97558667 ps |
| T864 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2269420790 |
|
|
Mar 19 01:28:09 PM PDT 24 |
Mar 19 01:30:19 PM PDT 24 |
2773328956 ps |
| T865 |
/workspace/coverage/default/29.sram_ctrl_executable.1056932607 |
|
|
Mar 19 01:25:05 PM PDT 24 |
Mar 19 01:52:02 PM PDT 24 |
13701749932 ps |
| T866 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.76377506 |
|
|
Mar 19 01:21:24 PM PDT 24 |
Mar 19 01:21:25 PM PDT 24 |
45766004 ps |
| T867 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.971452513 |
|
|
Mar 19 01:21:28 PM PDT 24 |
Mar 19 01:22:34 PM PDT 24 |
280972853 ps |
| T868 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3707825995 |
|
|
Mar 19 01:23:27 PM PDT 24 |
Mar 19 02:32:54 PM PDT 24 |
45437743548 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3650838190 |
|
|
Mar 19 01:28:48 PM PDT 24 |
Mar 19 01:29:22 PM PDT 24 |
143580697 ps |
| T870 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2275549207 |
|
|
Mar 19 01:23:27 PM PDT 24 |
Mar 19 01:29:45 PM PDT 24 |
32547069549 ps |
| T871 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.4010126954 |
|
|
Mar 19 01:22:28 PM PDT 24 |
Mar 19 01:22:32 PM PDT 24 |
146254696 ps |
| T872 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3375539757 |
|
|
Mar 19 01:26:03 PM PDT 24 |
Mar 19 01:55:46 PM PDT 24 |
78851646876 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1904744892 |
|
|
Mar 19 01:22:08 PM PDT 24 |
Mar 19 01:31:01 PM PDT 24 |
9177693707 ps |
| T874 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1024311750 |
|
|
Mar 19 01:22:42 PM PDT 24 |
Mar 19 01:22:54 PM PDT 24 |
527001172 ps |
| T875 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2207720351 |
|
|
Mar 19 01:26:55 PM PDT 24 |
Mar 19 01:27:26 PM PDT 24 |
453763336 ps |
| T876 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1870070377 |
|
|
Mar 19 01:21:54 PM PDT 24 |
Mar 19 01:42:22 PM PDT 24 |
16463328289 ps |
| T877 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.4116480637 |
|
|
Mar 19 01:21:18 PM PDT 24 |
Mar 19 01:25:21 PM PDT 24 |
2786206136 ps |
| T878 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2676884459 |
|
|
Mar 19 01:21:43 PM PDT 24 |
Mar 19 01:21:46 PM PDT 24 |
229097562 ps |
| T879 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1799908561 |
|
|
Mar 19 01:28:44 PM PDT 24 |
Mar 19 01:28:44 PM PDT 24 |
40398117 ps |
| T880 |
/workspace/coverage/default/42.sram_ctrl_bijection.2105241020 |
|
|
Mar 19 01:27:31 PM PDT 24 |
Mar 19 01:28:04 PM PDT 24 |
8232541742 ps |
| T881 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1744732673 |
|
|
Mar 19 01:27:06 PM PDT 24 |
Mar 19 01:27:31 PM PDT 24 |
230460961 ps |
| T882 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2322209359 |
|
|
Mar 19 01:21:50 PM PDT 24 |
Mar 19 01:39:37 PM PDT 24 |
9357819931 ps |
| T883 |
/workspace/coverage/default/47.sram_ctrl_bijection.4275800983 |
|
|
Mar 19 01:28:39 PM PDT 24 |
Mar 19 01:29:04 PM PDT 24 |
498020214 ps |
| T884 |
/workspace/coverage/default/48.sram_ctrl_bijection.128422025 |
|
|
Mar 19 01:28:50 PM PDT 24 |
Mar 19 01:30:01 PM PDT 24 |
4608244723 ps |
| T885 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.622165827 |
|
|
Mar 19 01:21:46 PM PDT 24 |
Mar 19 01:21:55 PM PDT 24 |
444674629 ps |
| T886 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1423909503 |
|
|
Mar 19 01:26:26 PM PDT 24 |
Mar 19 01:26:34 PM PDT 24 |
134462228 ps |
| T84 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1997993052 |
|
|
Mar 19 01:25:21 PM PDT 24 |
Mar 19 01:25:25 PM PDT 24 |
158079116 ps |
| T887 |
/workspace/coverage/default/39.sram_ctrl_regwen.3946887788 |
|
|
Mar 19 01:27:01 PM PDT 24 |
Mar 19 01:40:02 PM PDT 24 |
5252500402 ps |
| T888 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3114915563 |
|
|
Mar 19 01:27:56 PM PDT 24 |
Mar 19 01:32:29 PM PDT 24 |
40694600384 ps |
| T889 |
/workspace/coverage/default/25.sram_ctrl_stress_all.794331974 |
|
|
Mar 19 01:24:16 PM PDT 24 |
Mar 19 02:19:55 PM PDT 24 |
69038788340 ps |
| T890 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1936000526 |
|
|
Mar 19 01:21:20 PM PDT 24 |
Mar 19 01:23:06 PM PDT 24 |
495926662 ps |
| T891 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.43253629 |
|
|
Mar 19 01:26:39 PM PDT 24 |
Mar 19 01:44:06 PM PDT 24 |
3423377906 ps |
| T892 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.570765150 |
|
|
Mar 19 01:27:57 PM PDT 24 |
Mar 19 01:28:07 PM PDT 24 |
74091452 ps |
| T893 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3840514816 |
|
|
Mar 19 01:26:38 PM PDT 24 |
Mar 19 01:26:40 PM PDT 24 |
73952619 ps |
| T894 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1257655112 |
|
|
Mar 19 01:22:14 PM PDT 24 |
Mar 19 01:26:45 PM PDT 24 |
2252026471 ps |
| T895 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2559596507 |
|
|
Mar 19 01:27:26 PM PDT 24 |
Mar 19 01:31:54 PM PDT 24 |
3218693107 ps |
| T896 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.768563496 |
|
|
Mar 19 01:21:44 PM PDT 24 |
Mar 19 01:21:45 PM PDT 24 |
27762137 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_regwen.916716564 |
|
|
Mar 19 01:25:34 PM PDT 24 |
Mar 19 01:42:31 PM PDT 24 |
8874381483 ps |
| T898 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2267410880 |
|
|
Mar 19 01:22:52 PM PDT 24 |
Mar 19 01:22:57 PM PDT 24 |
123521216 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.757030716 |
|
|
Mar 19 01:22:41 PM PDT 24 |
Mar 19 01:25:32 PM PDT 24 |
1352164005 ps |
| T900 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.234675301 |
|
|
Mar 19 01:25:20 PM PDT 24 |
Mar 19 01:26:44 PM PDT 24 |
448767455 ps |
| T901 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3789526935 |
|
|
Mar 19 01:25:14 PM PDT 24 |
Mar 19 02:19:36 PM PDT 24 |
37793561906 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2841797148 |
|
|
Mar 19 01:23:57 PM PDT 24 |
Mar 19 02:11:22 PM PDT 24 |
17675913526 ps |
| T903 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.4183615367 |
|
|
Mar 19 01:26:52 PM PDT 24 |
Mar 19 01:54:22 PM PDT 24 |
3036574246 ps |
| T904 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.695948433 |
|
|
Mar 19 01:28:24 PM PDT 24 |
Mar 19 01:29:39 PM PDT 24 |
121075561 ps |
| T905 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3446245843 |
|
|
Mar 19 01:29:02 PM PDT 24 |
Mar 19 01:29:03 PM PDT 24 |
119011458 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1073100633 |
|
|
Mar 19 01:26:10 PM PDT 24 |
Mar 19 01:26:15 PM PDT 24 |
159314045 ps |
| T907 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4037769335 |
|
|
Mar 19 01:28:55 PM PDT 24 |
Mar 19 01:42:53 PM PDT 24 |
53332564336 ps |
| T908 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.40084543 |
|
|
Mar 19 01:23:07 PM PDT 24 |
Mar 19 01:23:09 PM PDT 24 |
444872652 ps |
| T909 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2556994763 |
|
|
Mar 19 01:21:16 PM PDT 24 |
Mar 19 02:26:12 PM PDT 24 |
47789480062 ps |
| T910 |
/workspace/coverage/default/4.sram_ctrl_bijection.780748244 |
|
|
Mar 19 01:21:19 PM PDT 24 |
Mar 19 01:22:09 PM PDT 24 |
808504574 ps |
| T911 |
/workspace/coverage/default/9.sram_ctrl_regwen.2406470886 |
|
|
Mar 19 01:21:42 PM PDT 24 |
Mar 19 01:45:02 PM PDT 24 |
16126614168 ps |
| T912 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2915537959 |
|
|
Mar 19 01:23:58 PM PDT 24 |
Mar 19 01:24:03 PM PDT 24 |
50255662 ps |
| T913 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1616577225 |
|
|
Mar 19 01:21:25 PM PDT 24 |
Mar 19 01:21:26 PM PDT 24 |
42764563 ps |
| T914 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3982236974 |
|
|
Mar 19 01:22:37 PM PDT 24 |
Mar 19 01:22:42 PM PDT 24 |
893770900 ps |
| T915 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3079092375 |
|
|
Mar 19 01:21:17 PM PDT 24 |
Mar 19 01:21:26 PM PDT 24 |
1757260935 ps |
| T916 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.872257260 |
|
|
Mar 19 01:28:20 PM PDT 24 |
Mar 19 01:35:57 PM PDT 24 |
4251951371 ps |
| T917 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2857512248 |
|
|
Mar 19 01:27:11 PM PDT 24 |
Mar 19 01:32:22 PM PDT 24 |
14657091390 ps |
| T918 |
/workspace/coverage/default/31.sram_ctrl_stress_all.503116353 |
|
|
Mar 19 01:25:32 PM PDT 24 |
Mar 19 01:54:57 PM PDT 24 |
53360069029 ps |
| T919 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3383535864 |
|
|
Mar 19 01:24:51 PM PDT 24 |
Mar 19 02:56:38 PM PDT 24 |
59466292836 ps |
| T920 |
/workspace/coverage/default/45.sram_ctrl_regwen.3581846090 |
|
|
Mar 19 01:28:18 PM PDT 24 |
Mar 19 01:34:01 PM PDT 24 |
2150464722 ps |
| T921 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4247813111 |
|
|
Mar 19 01:26:32 PM PDT 24 |
Mar 19 01:29:18 PM PDT 24 |
1749868929 ps |
| T922 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3734313656 |
|
|
Mar 19 01:22:49 PM PDT 24 |
Mar 19 01:22:50 PM PDT 24 |
46703956 ps |
| T923 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.591592883 |
|
|
Mar 19 01:21:16 PM PDT 24 |
Mar 19 01:24:50 PM PDT 24 |
4460230045 ps |
| T924 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1127195701 |
|
|
Mar 19 01:21:14 PM PDT 24 |
Mar 19 01:21:15 PM PDT 24 |
15650575 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3190452640 |
|
|
Mar 19 01:22:45 PM PDT 24 |
Mar 19 01:27:01 PM PDT 24 |
2822703447 ps |
| T926 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3010864168 |
|
|
Mar 19 01:27:34 PM PDT 24 |
Mar 19 01:32:14 PM PDT 24 |
42616504351 ps |
| T927 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2507250816 |
|
|
Mar 19 01:25:51 PM PDT 24 |
Mar 19 01:27:58 PM PDT 24 |
2337319944 ps |
| T928 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.889703342 |
|
|
Mar 19 01:24:35 PM PDT 24 |
Mar 19 01:26:15 PM PDT 24 |
227617915 ps |
| T929 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2621843029 |
|
|
Mar 19 01:23:00 PM PDT 24 |
Mar 19 01:24:41 PM PDT 24 |
19365255798 ps |
| T930 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3996349085 |
|
|
Mar 19 01:28:21 PM PDT 24 |
Mar 19 01:32:55 PM PDT 24 |
14766718705 ps |
| T931 |
/workspace/coverage/default/6.sram_ctrl_smoke.3478331229 |
|
|
Mar 19 01:21:28 PM PDT 24 |
Mar 19 01:24:01 PM PDT 24 |
1294759836 ps |
| T932 |
/workspace/coverage/default/24.sram_ctrl_alert_test.988892364 |
|
|
Mar 19 01:24:10 PM PDT 24 |
Mar 19 01:24:10 PM PDT 24 |
14468314 ps |
| T933 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.468893982 |
|
|
Mar 19 01:22:03 PM PDT 24 |
Mar 19 01:24:47 PM PDT 24 |
565841423 ps |
| T934 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.393816489 |
|
|
Mar 19 01:27:51 PM PDT 24 |
Mar 19 01:35:01 PM PDT 24 |
39796724805 ps |
| T935 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1466114634 |
|
|
Mar 19 01:21:19 PM PDT 24 |
Mar 19 01:35:27 PM PDT 24 |
1965465055 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.519769299 |
|
|
Mar 19 01:22:03 PM PDT 24 |
Mar 19 01:25:12 PM PDT 24 |
4168432521 ps |
| T937 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1024903263 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
52759157 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3860510020 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
647351277 ps |
| T63 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1279894955 |
|
|
Mar 19 01:01:09 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
1170472537 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.438191131 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:47 PM PDT 24 |
55753810 ps |
| T120 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3998419211 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
161019792 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.556372534 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:45 PM PDT 24 |
30199931 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2885903171 |
|
|
Mar 19 01:00:53 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
1923868809 ps |
| T99 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2329550889 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
21302860 ps |
| T65 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2784360018 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
21023641 ps |
| T938 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3106760510 |
|
|
Mar 19 01:00:58 PM PDT 24 |
Mar 19 01:01:03 PM PDT 24 |
47105046 ps |
| T108 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3585672113 |
|
|
Mar 19 01:00:51 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
36468681 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.858035333 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:46 PM PDT 24 |
13991598 ps |
| T66 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2307335905 |
|
|
Mar 19 01:00:53 PM PDT 24 |
Mar 19 01:00:55 PM PDT 24 |
54234662 ps |
| T100 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3531777660 |
|
|
Mar 19 01:01:15 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
46252411 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2457493667 |
|
|
Mar 19 01:01:13 PM PDT 24 |
Mar 19 01:01:15 PM PDT 24 |
197080036 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1869591102 |
|
|
Mar 19 01:01:14 PM PDT 24 |
Mar 19 01:01:18 PM PDT 24 |
412403158 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1575912242 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:55 PM PDT 24 |
26531997 ps |
| T939 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3123006149 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:08 PM PDT 24 |
144567274 ps |
| T940 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.473409482 |
|
|
Mar 19 01:01:16 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
38683123 ps |
| T941 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1273150261 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:09 PM PDT 24 |
70309138 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2915248450 |
|
|
Mar 19 01:01:06 PM PDT 24 |
Mar 19 01:01:07 PM PDT 24 |
16677324 ps |
| T942 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3007297135 |
|
|
Mar 19 01:00:47 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
19760360 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.591914853 |
|
|
Mar 19 01:00:53 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
2363351780 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.681755825 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
210303193 ps |
| T72 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3742773756 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
12824012 ps |
| T101 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.556188652 |
|
|
Mar 19 01:01:15 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
13957733 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2776471799 |
|
|
Mar 19 01:01:18 PM PDT 24 |
Mar 19 01:01:19 PM PDT 24 |
44992894 ps |
| T102 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1479761654 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
17514240 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3851783021 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
15094192 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2316486463 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
23028902 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1258502615 |
|
|
Mar 19 01:00:45 PM PDT 24 |
Mar 19 01:00:47 PM PDT 24 |
182337469 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.953372240 |
|
|
Mar 19 01:00:51 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
72877946 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2523448309 |
|
|
Mar 19 01:01:08 PM PDT 24 |
Mar 19 01:01:11 PM PDT 24 |
18264749 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1365904313 |
|
|
Mar 19 01:01:13 PM PDT 24 |
Mar 19 01:01:16 PM PDT 24 |
170693119 ps |
| T74 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.786646382 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
80845517 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1698286351 |
|
|
Mar 19 01:00:42 PM PDT 24 |
Mar 19 01:00:43 PM PDT 24 |
91783802 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3370223007 |
|
|
Mar 19 01:01:10 PM PDT 24 |
Mar 19 01:01:13 PM PDT 24 |
93542278 ps |
| T134 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.856340686 |
|
|
Mar 19 01:01:15 PM PDT 24 |
Mar 19 01:01:18 PM PDT 24 |
169611890 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.30971151 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
35431008 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2709487354 |
|
|
Mar 19 01:01:01 PM PDT 24 |
Mar 19 01:01:06 PM PDT 24 |
651400689 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3754466282 |
|
|
Mar 19 01:01:14 PM PDT 24 |
Mar 19 01:01:16 PM PDT 24 |
42897495 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.924187058 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:06 PM PDT 24 |
37578353 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1791152939 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:45 PM PDT 24 |
17431870 ps |
| T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2199568294 |
|
|
Mar 19 01:01:10 PM PDT 24 |
Mar 19 01:01:11 PM PDT 24 |
34255964 ps |
| T956 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.762102973 |
|
|
Mar 19 01:01:10 PM PDT 24 |
Mar 19 01:01:11 PM PDT 24 |
24177875 ps |
| T76 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2651602418 |
|
|
Mar 19 01:01:03 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
297564768 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2641963085 |
|
|
Mar 19 01:01:01 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
30514992 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2526088943 |
|
|
Mar 19 01:01:06 PM PDT 24 |
Mar 19 01:01:10 PM PDT 24 |
409412328 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1904347827 |
|
|
Mar 19 01:00:51 PM PDT 24 |
Mar 19 01:00:52 PM PDT 24 |
31057772 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4091174851 |
|
|
Mar 19 01:00:47 PM PDT 24 |
Mar 19 01:00:50 PM PDT 24 |
524712486 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3122038348 |
|
|
Mar 19 01:00:48 PM PDT 24 |
Mar 19 01:00:49 PM PDT 24 |
29092414 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.659021509 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
33101238 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3592752426 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
14735145 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1165277914 |
|
|
Mar 19 01:01:15 PM PDT 24 |
Mar 19 01:01:20 PM PDT 24 |
100521356 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.234601204 |
|
|
Mar 19 01:01:06 PM PDT 24 |
Mar 19 01:01:08 PM PDT 24 |
27388460 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3579657004 |
|
|
Mar 19 01:00:57 PM PDT 24 |
Mar 19 01:01:02 PM PDT 24 |
67523585 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1900807521 |
|
|
Mar 19 01:01:13 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
140245178 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4024097183 |
|
|
Mar 19 01:00:50 PM PDT 24 |
Mar 19 01:00:51 PM PDT 24 |
25716318 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1460298136 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:45 PM PDT 24 |
192662143 ps |
| T967 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.458120497 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:45 PM PDT 24 |
29493474 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3856848259 |
|
|
Mar 19 01:00:49 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
458174512 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3489928690 |
|
|
Mar 19 01:01:16 PM PDT 24 |
Mar 19 01:01:18 PM PDT 24 |
471189912 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3685529624 |
|
|
Mar 19 01:01:11 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
21174767 ps |
| T131 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1830369027 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:15 PM PDT 24 |
133416297 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4051898482 |
|
|
Mar 19 01:01:14 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
171658248 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2777559265 |
|
|
Mar 19 01:01:09 PM PDT 24 |
Mar 19 01:01:11 PM PDT 24 |
61138841 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3094149037 |
|
|
Mar 19 01:00:45 PM PDT 24 |
Mar 19 01:00:50 PM PDT 24 |
88646754 ps |
| T140 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1365327309 |
|
|
Mar 19 01:00:45 PM PDT 24 |
Mar 19 01:00:47 PM PDT 24 |
220088315 ps |
| T135 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1753307788 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
657948471 ps |
| T973 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3343020135 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
95327158 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.541418165 |
|
|
Mar 19 01:00:45 PM PDT 24 |
Mar 19 01:00:46 PM PDT 24 |
60491663 ps |
| T138 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2609992417 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
908391807 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1484731884 |
|
|
Mar 19 01:01:14 PM PDT 24 |
Mar 19 01:01:19 PM PDT 24 |
1578088685 ps |
| T976 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.843556522 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:16 PM PDT 24 |
36662384 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1553280780 |
|
|
Mar 19 01:01:11 PM PDT 24 |
Mar 19 01:01:13 PM PDT 24 |
55724686 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2137341488 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:04 PM PDT 24 |
24308976 ps |
| T137 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1863061816 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
118834725 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.221497127 |
|
|
Mar 19 01:00:53 PM PDT 24 |
Mar 19 01:00:57 PM PDT 24 |
351180050 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2751022874 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:49 PM PDT 24 |
680773149 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1845415547 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:55 PM PDT 24 |
507820933 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.501425817 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:47 PM PDT 24 |
657473962 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4061634265 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
439147396 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1613979914 |
|
|
Mar 19 01:00:45 PM PDT 24 |
Mar 19 01:00:47 PM PDT 24 |
1558063918 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4024950741 |
|
|
Mar 19 01:00:46 PM PDT 24 |
Mar 19 01:00:50 PM PDT 24 |
2598820208 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.579806477 |
|
|
Mar 19 01:01:14 PM PDT 24 |
Mar 19 01:01:15 PM PDT 24 |
53758616 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1321792368 |
|
|
Mar 19 01:00:49 PM PDT 24 |
Mar 19 01:00:50 PM PDT 24 |
31073918 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.695216221 |
|
|
Mar 19 01:01:11 PM PDT 24 |
Mar 19 01:01:17 PM PDT 24 |
421826190 ps |
| T136 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2348115465 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:08 PM PDT 24 |
196241242 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1148855252 |
|
|
Mar 19 01:01:15 PM PDT 24 |
Mar 19 01:01:21 PM PDT 24 |
1865813252 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.504331649 |
|
|
Mar 19 01:00:51 PM PDT 24 |
Mar 19 01:00:55 PM PDT 24 |
454782358 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3086957194 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
23447028 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4243164687 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:58 PM PDT 24 |
89055667 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3060219977 |
|
|
Mar 19 01:00:43 PM PDT 24 |
Mar 19 01:00:46 PM PDT 24 |
146030527 ps |
| T139 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.768671818 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:08 PM PDT 24 |
510962633 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2531869848 |
|
|
Mar 19 01:00:43 PM PDT 24 |
Mar 19 01:00:44 PM PDT 24 |
78476387 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3853082802 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:55 PM PDT 24 |
14893101 ps |
| T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3097424888 |
|
|
Mar 19 01:00:53 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
1217724565 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1136220754 |
|
|
Mar 19 01:00:50 PM PDT 24 |
Mar 19 01:00:51 PM PDT 24 |
51964615 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1365967559 |
|
|
Mar 19 01:01:11 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
46279088 ps |
| T90 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.822817861 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:54 PM PDT 24 |
209565342 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2724533625 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:45 PM PDT 24 |
23639371 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3961152656 |
|
|
Mar 19 01:01:01 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
1407538906 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1833353789 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:06 PM PDT 24 |
787614282 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.928619809 |
|
|
Mar 19 01:01:01 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
559907569 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3005151597 |
|
|
Mar 19 01:01:04 PM PDT 24 |
Mar 19 01:01:05 PM PDT 24 |
42047814 ps |
| T91 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1095539755 |
|
|
Mar 19 01:01:12 PM PDT 24 |
Mar 19 01:01:14 PM PDT 24 |
32928096 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2015537676 |
|
|
Mar 19 01:01:02 PM PDT 24 |
Mar 19 01:01:07 PM PDT 24 |
1519900201 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2610545712 |
|
|
Mar 19 01:00:54 PM PDT 24 |
Mar 19 01:00:56 PM PDT 24 |
1052609446 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3603844105 |
|
|
Mar 19 01:00:52 PM PDT 24 |
Mar 19 01:00:53 PM PDT 24 |
28893424 ps |