Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.39	100.00	97.77	100.00	100.00	99.71	99.70	98.52

Total test records in report: 1025

T1003	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.263684524	Mar 19 01:01:02 PM PDT 24	Mar 19 01:01:06 PM PDT 24	284527456 ps
T1004	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.189053357	Mar 19 01:01:13 PM PDT 24	Mar 19 01:01:15 PM PDT 24	11914919 ps
T1005	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2419943834	Mar 19 01:01:15 PM PDT 24	Mar 19 01:01:18 PM PDT 24	318079835 ps
T1006	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.610117396	Mar 19 01:00:50 PM PDT 24	Mar 19 01:00:51 PM PDT 24	20877816 ps
T1007	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.642192203	Mar 19 01:00:46 PM PDT 24	Mar 19 01:00:47 PM PDT 24	25953365 ps
T92	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.913645105	Mar 19 01:01:10 PM PDT 24	Mar 19 01:01:13 PM PDT 24	2075598152 ps
T1008	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3911687643	Mar 19 01:01:03 PM PDT 24	Mar 19 01:01:05 PM PDT 24	48138412 ps
T93	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4033654169	Mar 19 01:01:03 PM PDT 24	Mar 19 01:01:06 PM PDT 24	419330866 ps
T1009	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2447983250	Mar 19 01:01:04 PM PDT 24	Mar 19 01:01:05 PM PDT 24	63684598 ps
T1010	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3704170766	Mar 19 01:01:02 PM PDT 24	Mar 19 01:01:05 PM PDT 24	39398317 ps
T1011	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3855695346	Mar 19 01:00:53 PM PDT 24	Mar 19 01:00:57 PM PDT 24	2617768585 ps
T1012	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3066351193	Mar 19 01:00:49 PM PDT 24	Mar 19 01:00:50 PM PDT 24	49892820 ps
T1013	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1284844197	Mar 19 01:01:13 PM PDT 24	Mar 19 01:01:15 PM PDT 24	281324673 ps
T1014	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1293084604	Mar 19 01:00:45 PM PDT 24	Mar 19 01:00:46 PM PDT 24	96331121 ps
T1015	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3581367320	Mar 19 01:00:54 PM PDT 24	Mar 19 01:00:55 PM PDT 24	47502410 ps
T1016	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3971288625	Mar 19 01:00:53 PM PDT 24	Mar 19 01:00:54 PM PDT 24	27196695 ps
T1017	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2478698987	Mar 19 01:01:03 PM PDT 24	Mar 19 01:01:04 PM PDT 24	120650240 ps
T1018	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4095174539	Mar 19 01:00:51 PM PDT 24	Mar 19 01:00:53 PM PDT 24	106399208 ps
T1019	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4008281036	Mar 19 01:01:03 PM PDT 24	Mar 19 01:01:04 PM PDT 24	31871991 ps
T1020	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2479950292	Mar 19 01:00:49 PM PDT 24	Mar 19 01:00:50 PM PDT 24	18176715 ps
T1021	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3916236886	Mar 19 01:01:02 PM PDT 24	Mar 19 01:01:07 PM PDT 24	38429222 ps
T1022	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3995639398	Mar 19 01:01:02 PM PDT 24	Mar 19 01:01:05 PM PDT 24	253609872 ps
T1023	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2088063432	Mar 19 01:01:12 PM PDT 24	Mar 19 01:01:15 PM PDT 24	606259501 ps
T1024	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.786151974	Mar 19 01:01:10 PM PDT 24	Mar 19 01:01:11 PM PDT 24	118677807 ps
T1025	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1269453756	Mar 19 01:01:15 PM PDT 24	Mar 19 01:01:20 PM PDT 24	544139820 ps

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.795457089
Short name	T2
Test name
Test status
Simulation time	3798341239 ps
CPU time	1674.68 seconds
Started	Mar 19 01:27:11 PM PDT 24
Finished	Mar 19 01:55:23 PM PDT 24
Peak memory	374244 kb
Host	smart-9f8121af-496d-4568-b700-e505f7c2f799
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795457089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sram_ctrl_access_during_key_req.795457089
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2572771534
Short name	T29
Test name
Test status
Simulation time	4660159978 ps
CPU time	317.14 seconds
Started	Mar 19 01:21:37 PM PDT 24
Finished	Mar 19 01:26:55 PM PDT 24
Peak memory	342724 kb
Host	smart-558ea8c5-6754-46fd-8d85-b2ba3dc397c1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2572771534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2572771534
Directory	/workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all.3812313935
Short name	T60
Test name
Test status
Simulation time	53408875094 ps
CPU time	2447.92 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 02:02:26 PM PDT 24
Peak memory	376716 kb
Host	smart-e1594133-a3dd-4e1e-ad2c-7423df8e994b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812313935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.3812313935
Directory	/workspace/7.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.990729702
Short name	T15
Test name
Test status
Simulation time	14416917619 ps
CPU time	641.61 seconds
Started	Mar 19 01:28:02 PM PDT 24
Finished	Mar 19 01:38:44 PM PDT 24
Peak memory	354916 kb
Host	smart-b272bfa1-e62d-4d01-9645-04104b139cd2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990729702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.990729702
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3860510020
Short name	T111
Test name
Test status
Simulation time	647351277 ps
CPU time	2.18 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:48 PM PDT 24
Peak memory	202128 kb
Host	smart-5431983b-ef3e-43b3-a32e-c2ac01f88d6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860510020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3860510020
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_sec_cm.1736441680
Short name	T24
Test name
Test status
Simulation time	377145695 ps
CPU time	2.53 seconds
Started	Mar 19 01:21:08 PM PDT 24
Finished	Mar 19 01:21:10 PM PDT 24
Peak memory	222148 kb
Host	smart-7667e377-ab1a-496d-a242-40431a7b94df
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736441680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1736441680
Directory	/workspace/0.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2314838212
Short name	T97
Test name
Test status
Simulation time	16047852781 ps
CPU time	391.03 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:27:59 PM PDT 24
Peak memory	203280 kb
Host	smart-a7800797-7562-4599-aad4-b8554c76a623
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314838212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.2314838212
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.3863867021
Short name	T162
Test name
Test status
Simulation time	15649208 ps
CPU time	0.63 seconds
Started	Mar 19 01:25:45 PM PDT 24
Finished	Mar 19 01:25:47 PM PDT 24
Peak memory	202128 kb
Host	smart-d43fde17-78ea-4dab-b463-d6956eabeb02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863867021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3863867021
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1279894955
Short name	T63
Test name
Test status
Simulation time	1170472537 ps
CPU time	3.35 seconds
Started	Mar 19 01:01:09 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	202188 kb
Host	smart-84f9ce69-2639-4f0c-9731-07158bc9c966
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279894955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1279894955
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.611497042
Short name	T16
Test name
Test status
Simulation time	37492301512 ps
CPU time	360.24 seconds
Started	Mar 19 01:24:01 PM PDT 24
Finished	Mar 19 01:30:02 PM PDT 24
Peak memory	203312 kb
Host	smart-a46c1642-2d77-409c-8f38-e9c5589b9c17
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611497042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.611497042
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.856340686
Short name	T134
Test name
Test status
Simulation time	169611890 ps
CPU time	2.24 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:18 PM PDT 24
Peak memory	202112 kb
Host	smart-bc5eb0e7-1242-445b-9d64-e5922de0ddb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856340686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.856340686
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.4149459162
Short name	T168
Test name
Test status
Simulation time	106101117 ps
CPU time	0.9 seconds
Started	Mar 19 01:22:25 PM PDT 24
Finished	Mar 19 01:22:27 PM PDT 24
Peak memory	203304 kb
Host	smart-605ebe57-e13d-46cd-9b99-daa7395a77d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149459162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.4149459162
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2912970379
Short name	T47
Test name
Test status
Simulation time	1604235296 ps
CPU time	139.09 seconds
Started	Mar 19 01:27:06 PM PDT 24
Finished	Mar 19 01:29:47 PM PDT 24
Peak memory	342060 kb
Host	smart-599ee171-e253-4b02-bc14-76f738ee294b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2912970379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2912970379
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4051898482
Short name	T132
Test name
Test status
Simulation time	171658248 ps
CPU time	2.03 seconds
Started	Mar 19 01:01:14 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	202080 kb
Host	smart-9c49cbac-47bb-4407-b8a0-6f88cc1afd6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051898482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.4051898482
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all.3627271626
Short name	T287
Test name
Test status
Simulation time	11291664191 ps
CPU time	1498.59 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:48:31 PM PDT 24
Peak memory	374136 kb
Host	smart-d96c41f3-292f-4284-86b0-e2bdf2f77e4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627271626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.3627271626
Directory	/workspace/21.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.501425817
Short name	T87
Test name
Test status
Simulation time	657473962 ps
CPU time	3.41 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	202160 kb
Host	smart-611f7484-952d-4069-a67a-502d238cc214
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501425817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.501425817
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.588381285
Short name	T199
Test name
Test status
Simulation time	17992354640 ps
CPU time	977.65 seconds
Started	Mar 19 01:22:23 PM PDT 24
Finished	Mar 19 01:38:41 PM PDT 24
Peak memory	375028 kb
Host	smart-d07599ef-53b1-4ea6-84e1-4a8ee92a7f8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588381285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.588381285
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1698286351
Short name	T75
Test name
Test status
Simulation time	91783802 ps
CPU time	0.73 seconds
Started	Mar 19 01:00:42 PM PDT 24
Finished	Mar 19 01:00:43 PM PDT 24
Peak memory	201812 kb
Host	smart-a4cebd4d-c005-48cc-a7cd-cb88581f09f1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698286351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1698286351
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1258502615
Short name	T946
Test name
Test status
Simulation time	182337469 ps
CPU time	1.47 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	202008 kb
Host	smart-7552dd68-5699-488f-9270-b21540973ba1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258502615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1258502615
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3007297135
Short name	T942
Test name
Test status
Simulation time	19760360 ps
CPU time	0.71 seconds
Started	Mar 19 01:00:47 PM PDT 24
Finished	Mar 19 01:00:48 PM PDT 24
Peak memory	201892 kb
Host	smart-18b289cf-62ae-4259-ab90-298ae9632fcf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007297135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3007297135
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2531869848
Short name	T990
Test name
Test status
Simulation time	78476387 ps
CPU time	1.11 seconds
Started	Mar 19 01:00:43 PM PDT 24
Finished	Mar 19 01:00:44 PM PDT 24
Peak memory	210180 kb
Host	smart-a5cbe62f-cb47-4158-a921-d1f297ffbf7a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531869848 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2531869848
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.642192203
Short name	T1007
Test name
Test status
Simulation time	25953365 ps
CPU time	0.64 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	201916 kb
Host	smart-c9308ef3-5ae7-403f-997c-dd0f152c074a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642192203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.sram_ctrl_csr_rw.642192203
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.556372534
Short name	T64
Test name
Test status
Simulation time	30199931 ps
CPU time	0.7 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:45 PM PDT 24
Peak memory	202052 kb
Host	smart-3112ab6f-801f-49cf-bd37-37f60e0d677b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556372534 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.556372534
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3856848259
Short name	T968
Test name
Test status
Simulation time	458174512 ps
CPU time	4.18 seconds
Started	Mar 19 01:00:49 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	201436 kb
Host	smart-8cc52338-6cb8-433b-8140-938b1188132e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856848259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3856848259
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2724533625
Short name	T995
Test name
Test status
Simulation time	23639371 ps
CPU time	0.75 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:45 PM PDT 24
Peak memory	201916 kb
Host	smart-429d5d23-c0a6-4a98-b55f-e8f5a2b5bc96
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724533625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2724533625
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.681755825
Short name	T71
Test name
Test status
Simulation time	210303193 ps
CPU time	1.85 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:48 PM PDT 24
Peak memory	202000 kb
Host	smart-37fb07fa-e49a-4f49-8e84-900d66bbe1b8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681755825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.681755825
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1321792368
Short name	T983
Test name
Test status
Simulation time	31073918 ps
CPU time	0.69 seconds
Started	Mar 19 01:00:49 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	201892 kb
Host	smart-1025d2f4-64bc-4125-a199-8cb99b448ce8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321792368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.1321792368
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1293084604
Short name	T1014
Test name
Test status
Simulation time	96331121 ps
CPU time	1.12 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:46 PM PDT 24
Peak memory	210196 kb
Host	smart-367410bd-b4a5-47b8-800b-54bebecb8046
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293084604 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1293084604
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3122038348
Short name	T85
Test name
Test status
Simulation time	29092414 ps
CPU time	0.69 seconds
Started	Mar 19 01:00:48 PM PDT 24
Finished	Mar 19 01:00:49 PM PDT 24
Peak memory	201892 kb
Host	smart-4cc779f8-b4b6-44e1-b576-098409938efa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122038348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3122038348
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4061634265
Short name	T88
Test name
Test status
Simulation time	439147396 ps
CPU time	3.11 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:48 PM PDT 24
Peak memory	202172 kb
Host	smart-343b78c5-a67a-4065-a17b-bfe6fc3443a5
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061634265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4061634265
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.541418165
Short name	T974
Test name
Test status
Simulation time	60491663 ps
CPU time	0.73 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:46 PM PDT 24
Peak memory	202000 kb
Host	smart-dbe2e7c8-7f8a-40a4-8e3b-def5b4d4cf95
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541418165 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.541418165
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3094149037
Short name	T972
Test name
Test status
Simulation time	88646754 ps
CPU time	4.06 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	202180 kb
Host	smart-f71750a9-231e-4463-bb55-add4c677c3da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094149037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.3094149037
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1365327309
Short name	T140
Test name
Test status
Simulation time	220088315 ps
CPU time	2.34 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	202184 kb
Host	smart-bd2a5828-9909-4ad1-a3c5-38d5e0234f86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365327309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1365327309
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1024903263
Short name	T937
Test name
Test status
Simulation time	52759157 ps
CPU time	1.39 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	210392 kb
Host	smart-1a9fcc9d-37ad-40c0-9a3a-839a2431b50d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024903263 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1024903263
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2478698987
Short name	T1017
Test name
Test status
Simulation time	120650240 ps
CPU time	0.65 seconds
Started	Mar 19 01:01:03 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201792 kb
Host	smart-6cf2fb09-df50-4114-8ca1-68ecffc6d6dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478698987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.2478698987
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2526088943
Short name	T958
Test name
Test status
Simulation time	409412328 ps
CPU time	1.86 seconds
Started	Mar 19 01:01:06 PM PDT 24
Finished	Mar 19 01:01:10 PM PDT 24
Peak memory	202020 kb
Host	smart-495e24f2-256b-4ac1-95e3-086533dd376e
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526088943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2526088943
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2137341488
Short name	T978
Test name
Test status
Simulation time	24308976 ps
CPU time	0.69 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201956 kb
Host	smart-2212e37e-156f-447e-8711-4aae76ee1b94
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137341488 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2137341488
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.234601204
Short name	T963
Test name
Test status
Simulation time	27388460 ps
CPU time	2.21 seconds
Started	Mar 19 01:01:06 PM PDT 24
Finished	Mar 19 01:01:08 PM PDT 24
Peak memory	201580 kb
Host	smart-6ae83d4b-e8a2-494a-be0d-d3851430dcdd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234601204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.234601204
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2348115465
Short name	T136
Test name
Test status
Simulation time	196241242 ps
CPU time	1.75 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:08 PM PDT 24
Peak memory	202148 kb
Host	smart-5ff498d5-36cf-4ad1-aef3-458bb7d7e861
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348115465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.2348115465
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.659021509
Short name	T960
Test name
Test status
Simulation time	33101238 ps
CPU time	0.64 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201896 kb
Host	smart-14a84939-e059-42ca-ad8e-f0a78dc19e90
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659021509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.659021509
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3995639398
Short name	T1022
Test name
Test status
Simulation time	253609872 ps
CPU time	2.01 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202016 kb
Host	smart-86dbe0d4-fcd2-410e-834e-051ea93a146c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995639398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3995639398
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2447983250
Short name	T1009
Test name
Test status
Simulation time	63684598 ps
CPU time	0.79 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	201992 kb
Host	smart-1805b686-292c-46f6-83bf-76d8333f0c7c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447983250 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2447983250
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1273150261
Short name	T941
Test name
Test status
Simulation time	70309138 ps
CPU time	2.66 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:09 PM PDT 24
Peak memory	202156 kb
Host	smart-6084d95a-bacf-40dc-8d08-e3a380f12b61
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273150261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1273150261
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3961152656
Short name	T996
Test name
Test status
Simulation time	1407538906 ps
CPU time	2.98 seconds
Started	Mar 19 01:01:01 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202100 kb
Host	smart-4f5fd66a-de12-4707-8958-5cdb254ba500
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961152656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.3961152656
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3911687643
Short name	T1008
Test name
Test status
Simulation time	48138412 ps
CPU time	1.6 seconds
Started	Mar 19 01:01:03 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	211368 kb
Host	smart-223306ba-bbab-4e60-abdc-3a086bfc5e0f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911687643 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3911687643
Directory	/workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4008281036
Short name	T1019
Test name
Test status
Simulation time	31871991 ps
CPU time	0.71 seconds
Started	Mar 19 01:01:03 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201932 kb
Host	smart-f1098ff6-81c3-4b5d-b3dd-9fda79fc7da7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008281036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.4008281036
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.928619809
Short name	T998
Test name
Test status
Simulation time	559907569 ps
CPU time	2.1 seconds
Started	Mar 19 01:01:01 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202044 kb
Host	smart-266df87a-f9c6-47a1-82c5-1c04a4aae52c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928619809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.928619809
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3005151597
Short name	T999
Test name
Test status
Simulation time	42047814 ps
CPU time	0.72 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	201928 kb
Host	smart-77780e3b-3ae8-4a85-a96e-0b39cb685ef6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005151597 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3005151597
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2709487354
Short name	T951
Test name
Test status
Simulation time	651400689 ps
CPU time	4.82 seconds
Started	Mar 19 01:01:01 PM PDT 24
Finished	Mar 19 01:01:06 PM PDT 24
Peak memory	202168 kb
Host	smart-5e57b734-b73b-4ba3-848e-e02b09f9e0f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709487354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.2709487354
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.768671818
Short name	T139
Test name
Test status
Simulation time	510962633 ps
CPU time	2.13 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:08 PM PDT 24
Peak memory	202104 kb
Host	smart-1b45db09-d9db-43f7-a6ca-9cce0d5aaaff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768671818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.sram_ctrl_tl_intg_err.768671818
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2777559265
Short name	T971
Test name
Test status
Simulation time	61138841 ps
CPU time	1.23 seconds
Started	Mar 19 01:01:09 PM PDT 24
Finished	Mar 19 01:01:11 PM PDT 24
Peak memory	210296 kb
Host	smart-eda82a4d-6069-463e-9ee4-a05dc660217b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777559265 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2777559265
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.786646382
Short name	T74
Test name
Test status
Simulation time	80845517 ps
CPU time	0.69 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	201888 kb
Host	smart-6fe18fda-3fbc-4776-b28e-4bb23a01d92d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786646382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_csr_rw.786646382
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2015537676
Short name	T1000
Test name
Test status
Simulation time	1519900201 ps
CPU time	3.37 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:07 PM PDT 24
Peak memory	202152 kb
Host	smart-a172a0a8-b13b-43c1-af30-cfaef1f85d9d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015537676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2015537676
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1365967559
Short name	T994
Test name
Test status
Simulation time	46279088 ps
CPU time	0.82 seconds
Started	Mar 19 01:01:11 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	202000 kb
Host	smart-9feaf728-b893-4302-ada3-2f0dffc7b073
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365967559 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1365967559
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3086957194
Short name	T987
Test name
Test status
Simulation time	23447028 ps
CPU time	1.72 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202132 kb
Host	smart-c97a56b3-b669-455c-8130-5ef568bb579e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086957194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3086957194
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.263684524
Short name	T1003
Test name
Test status
Simulation time	284527456 ps
CPU time	2.58 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:06 PM PDT 24
Peak memory	202116 kb
Host	smart-20983a95-4789-4ba8-9b94-1879a5259a7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263684524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.263684524
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2199568294
Short name	T955
Test name
Test status
Simulation time	34255964 ps
CPU time	1.12 seconds
Started	Mar 19 01:01:10 PM PDT 24
Finished	Mar 19 01:01:11 PM PDT 24
Peak memory	210476 kb
Host	smart-047ef601-07ca-4d76-a560-b82c5aa3c4d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199568294 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2199568294
Directory	/workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1095539755
Short name	T91
Test name
Test status
Simulation time	32928096 ps
CPU time	0.65 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	200976 kb
Host	smart-8a74a3f5-afc0-443c-b821-6dc6dc1573e9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095539755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.1095539755
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3531777660
Short name	T100
Test name
Test status
Simulation time	46252411 ps
CPU time	0.69 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	201896 kb
Host	smart-8792eaa2-7eb8-434e-a0e7-6c49c8407e0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531777660 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3531777660
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1484731884
Short name	T975
Test name
Test status
Simulation time	1578088685 ps
CPU time	4.69 seconds
Started	Mar 19 01:01:14 PM PDT 24
Finished	Mar 19 01:01:19 PM PDT 24
Peak memory	210336 kb
Host	smart-69235da5-0c8d-4ad9-ae1d-d5ff47e1fd34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484731884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1484731884
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1365904313
Short name	T113
Test name
Test status
Simulation time	170693119 ps
CPU time	2.34 seconds
Started	Mar 19 01:01:13 PM PDT 24
Finished	Mar 19 01:01:16 PM PDT 24
Peak memory	202068 kb
Host	smart-76d8203a-2826-4c12-8601-32f88d8e70a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365904313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1365904313
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3489928690
Short name	T969
Test name
Test status
Simulation time	471189912 ps
CPU time	1.55 seconds
Started	Mar 19 01:01:16 PM PDT 24
Finished	Mar 19 01:01:18 PM PDT 24
Peak memory	210492 kb
Host	smart-f1281288-df60-4ecb-b97e-0f5cd44d0df4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489928690 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3489928690
Directory	/workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3754466282
Short name	T952
Test name
Test status
Simulation time	42897495 ps
CPU time	0.71 seconds
Started	Mar 19 01:01:14 PM PDT 24
Finished	Mar 19 01:01:16 PM PDT 24
Peak memory	201924 kb
Host	smart-d2fd6bc0-45fb-47fc-a8f6-041cfd7849b8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754466282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3754466282
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1869591102
Short name	T67
Test name
Test status
Simulation time	412403158 ps
CPU time	3.09 seconds
Started	Mar 19 01:01:14 PM PDT 24
Finished	Mar 19 01:01:18 PM PDT 24
Peak memory	202120 kb
Host	smart-4d4e27e9-df6b-455a-8bca-c5cb1c4567c4
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869591102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1869591102
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.30971151
Short name	T950
Test name
Test status
Simulation time	35431008 ps
CPU time	0.74 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	201980 kb
Host	smart-e9ac91f3-13b6-4a93-9ae6-a3f939e3ecfd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30971151 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.30971151
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1148855252
Short name	T985
Test name
Test status
Simulation time	1865813252 ps
CPU time	4.65 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:21 PM PDT 24
Peak memory	202140 kb
Host	smart-08ce62db-de76-4921-b728-dfa98594ca6a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148855252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.1148855252
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2088063432
Short name	T1023
Test name
Test status
Simulation time	606259501 ps
CPU time	2.22 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	202104 kb
Host	smart-7a89b209-53ff-41b1-bfbc-64f2bf6cb9a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088063432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.2088063432
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.473409482
Short name	T940
Test name
Test status
Simulation time	38683123 ps
CPU time	0.93 seconds
Started	Mar 19 01:01:16 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	202028 kb
Host	smart-95947cd4-c26a-470a-a11c-117a9644deae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473409482 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.473409482
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2523448309
Short name	T948
Test name
Test status
Simulation time	18264749 ps
CPU time	0.63 seconds
Started	Mar 19 01:01:08 PM PDT 24
Finished	Mar 19 01:01:11 PM PDT 24
Peak memory	201880 kb
Host	smart-b397f0be-9588-4865-bc11-42ce578284b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523448309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.2523448309
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.913645105
Short name	T92
Test name
Test status
Simulation time	2075598152 ps
CPU time	2.99 seconds
Started	Mar 19 01:01:10 PM PDT 24
Finished	Mar 19 01:01:13 PM PDT 24
Peak memory	202084 kb
Host	smart-93f252ae-8d16-4674-9fe1-e77be76a0d72
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913645105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.913645105
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3685529624
Short name	T970
Test name
Test status
Simulation time	21174767 ps
CPU time	0.73 seconds
Started	Mar 19 01:01:11 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	201904 kb
Host	smart-a989e3b9-bf64-4ed1-8625-cfb3b08ccf89
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685529624 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3685529624
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3370223007
Short name	T949
Test name
Test status
Simulation time	93542278 ps
CPU time	2.7 seconds
Started	Mar 19 01:01:10 PM PDT 24
Finished	Mar 19 01:01:13 PM PDT 24
Peak memory	202284 kb
Host	smart-0f808dda-1576-435f-9698-82a61170b2d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370223007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.3370223007
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2419943834
Short name	T1005
Test name
Test status
Simulation time	318079835 ps
CPU time	1.45 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:18 PM PDT 24
Peak memory	202136 kb
Host	smart-d4f7b2bf-a999-4bca-954b-2b16f8a8545a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419943834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2419943834
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.786151974
Short name	T1024
Test name
Test status
Simulation time	118677807 ps
CPU time	1.22 seconds
Started	Mar 19 01:01:10 PM PDT 24
Finished	Mar 19 01:01:11 PM PDT 24
Peak memory	211276 kb
Host	smart-59c05432-023e-42e6-bb22-9df2920023f3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786151974 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.786151974
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3742773756
Short name	T72
Test name
Test status
Simulation time	12824012 ps
CPU time	0.68 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	201860 kb
Host	smart-163bfd3f-55c0-4521-8a46-ad609d0e00a6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742773756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3742773756
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2457493667
Short name	T110
Test name
Test status
Simulation time	197080036 ps
CPU time	1.82 seconds
Started	Mar 19 01:01:13 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	202036 kb
Host	smart-4608c97a-0da0-480c-a388-bbd6b8c127c3
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457493667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2457493667
Directory	/workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2784360018
Short name	T65
Test name
Test status
Simulation time	21023641 ps
CPU time	0.77 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:14 PM PDT 24
Peak memory	202012 kb
Host	smart-9213e242-878f-41db-8c34-2ad862254bb9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784360018 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2784360018
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1165277914
Short name	T962
Test name
Test status
Simulation time	100521356 ps
CPU time	3.67 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:20 PM PDT 24
Peak memory	202128 kb
Host	smart-0793faa3-dcb8-47ab-aa52-8e7aa2d771ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165277914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1165277914
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.843556522
Short name	T976
Test name
Test status
Simulation time	36662384 ps
CPU time	2.45 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:16 PM PDT 24
Peak memory	210388 kb
Host	smart-22909434-3a89-4568-818d-dd9ecb8c8983
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843556522 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.843556522
Directory	/workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.189053357
Short name	T1004
Test name
Test status
Simulation time	11914919 ps
CPU time	0.66 seconds
Started	Mar 19 01:01:13 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	201940 kb
Host	smart-9749d253-56d5-402c-a33e-424f77e4541c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189053357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.189053357
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1269453756
Short name	T1025
Test name
Test status
Simulation time	544139820 ps
CPU time	3.34 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:20 PM PDT 24
Peak memory	202176 kb
Host	smart-ef825ae2-2af6-4d95-8aeb-d78d387a23eb
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269453756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1269453756
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.556188652
Short name	T101
Test name
Test status
Simulation time	13957733 ps
CPU time	0.75 seconds
Started	Mar 19 01:01:15 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	201972 kb
Host	smart-c93dcfaa-5b50-4520-9b7f-24596068f737
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556188652 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.556188652
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.695216221
Short name	T984
Test name
Test status
Simulation time	421826190 ps
CPU time	3.79 seconds
Started	Mar 19 01:01:11 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	202136 kb
Host	smart-5ee7953c-16f2-43f6-b945-e827af3d01e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695216221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.695216221
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1830369027
Short name	T131
Test name
Test status
Simulation time	133416297 ps
CPU time	1.59 seconds
Started	Mar 19 01:01:12 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	202068 kb
Host	smart-67584aec-a28d-4d9f-ad11-6d1a80200ffd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830369027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.1830369027
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1900807521
Short name	T965
Test name
Test status
Simulation time	140245178 ps
CPU time	2.06 seconds
Started	Mar 19 01:01:13 PM PDT 24
Finished	Mar 19 01:01:17 PM PDT 24
Peak memory	212560 kb
Host	smart-91d98084-2909-46ec-a11e-a1eca9ac8889
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900807521 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1900807521
Directory	/workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.762102973
Short name	T956
Test name
Test status
Simulation time	24177875 ps
CPU time	0.63 seconds
Started	Mar 19 01:01:10 PM PDT 24
Finished	Mar 19 01:01:11 PM PDT 24
Peak memory	202168 kb
Host	smart-e2e77ad8-8dc8-48a0-8f22-e1f1acdd177a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762102973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.762102973
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1284844197
Short name	T1013
Test name
Test status
Simulation time	281324673 ps
CPU time	2.01 seconds
Started	Mar 19 01:01:13 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	202032 kb
Host	smart-9d441cb8-449f-43bc-bc30-b8f5a4f8f041
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284844197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1284844197
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.579806477
Short name	T982
Test name
Test status
Simulation time	53758616 ps
CPU time	0.77 seconds
Started	Mar 19 01:01:14 PM PDT 24
Finished	Mar 19 01:01:15 PM PDT 24
Peak memory	201988 kb
Host	smart-561c8a25-10fb-48a9-b427-a37b53ee5f8f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579806477 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.579806477
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1553280780
Short name	T977
Test name
Test status
Simulation time	55724686 ps
CPU time	1.84 seconds
Started	Mar 19 01:01:11 PM PDT 24
Finished	Mar 19 01:01:13 PM PDT 24
Peak memory	202104 kb
Host	smart-55529953-3886-48e6-9cfe-ae7346e4a0fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553280780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1553280780
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3066351193
Short name	T1012
Test name
Test status
Simulation time	49892820 ps
CPU time	0.72 seconds
Started	Mar 19 01:00:49 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	200888 kb
Host	smart-dad695e9-bc55-4fb9-bd0e-8407875a6ea2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066351193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3066351193
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4091174851
Short name	T77
Test name
Test status
Simulation time	524712486 ps
CPU time	2.3 seconds
Started	Mar 19 01:00:47 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	202020 kb
Host	smart-67b79140-f065-4eb9-8c72-0e56e90c7b43
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091174851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.4091174851
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2479950292
Short name	T1020
Test name
Test status
Simulation time	18176715 ps
CPU time	0.69 seconds
Started	Mar 19 01:00:49 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	201856 kb
Host	smart-13088181-2ab9-46fc-b469-3ab3310bec0c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479950292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2479950292
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.458120497
Short name	T967
Test name
Test status
Simulation time	29493474 ps
CPU time	1.01 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:45 PM PDT 24
Peak memory	210220 kb
Host	smart-e8205a25-cf59-42b6-b015-bd09346a9672
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458120497 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.458120497
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.858035333
Short name	T109
Test name
Test status
Simulation time	13991598 ps
CPU time	0.66 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:46 PM PDT 24
Peak memory	201956 kb
Host	smart-3587551c-1368-466b-8407-085c8760313f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858035333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.858035333
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1613979914
Short name	T981
Test name
Test status
Simulation time	1558063918 ps
CPU time	2.31 seconds
Started	Mar 19 01:00:45 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	202032 kb
Host	smart-499e05ca-cad2-4c5d-8369-a5e5c551eada
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613979914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1613979914
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.438191131
Short name	T98
Test name
Test status
Simulation time	55753810 ps
CPU time	0.72 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:47 PM PDT 24
Peak memory	201928 kb
Host	smart-afd22600-2f03-40d0-8e18-08eebdc4de91
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438191131 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.438191131
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3060219977
Short name	T989
Test name
Test status
Simulation time	146030527 ps
CPU time	3.26 seconds
Started	Mar 19 01:00:43 PM PDT 24
Finished	Mar 19 01:00:46 PM PDT 24
Peak memory	202156 kb
Host	smart-277b7a68-0b3b-48c0-95b6-9337ae51ad47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060219977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.3060219977
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1460298136
Short name	T133
Test name
Test status
Simulation time	192662143 ps
CPU time	1.48 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:45 PM PDT 24
Peak memory	202092 kb
Host	smart-2dc00f4b-fe9f-4f93-b863-980cab5987f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460298136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.1460298136
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2776471799
Short name	T943
Test name
Test status
Simulation time	44992894 ps
CPU time	0.69 seconds
Started	Mar 19 01:01:18 PM PDT 24
Finished	Mar 19 01:01:19 PM PDT 24
Peak memory	201860 kb
Host	smart-145e902c-9eea-4c81-952b-c32619b90a6b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776471799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.2776471799
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4095174539
Short name	T1018
Test name
Test status
Simulation time	106399208 ps
CPU time	1.24 seconds
Started	Mar 19 01:00:51 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	202100 kb
Host	smart-2f18baf8-5f53-4b43-b5ff-b5a7ceabdf94
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095174539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.4095174539
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1791152939
Short name	T954
Test name
Test status
Simulation time	17431870 ps
CPU time	0.65 seconds
Started	Mar 19 01:00:44 PM PDT 24
Finished	Mar 19 01:00:45 PM PDT 24
Peak memory	201772 kb
Host	smart-ba802963-ed9e-4a42-8ffc-75ac02ca37a3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791152939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1791152939
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3579657004
Short name	T964
Test name
Test status
Simulation time	67523585 ps
CPU time	2.78 seconds
Started	Mar 19 01:00:57 PM PDT 24
Finished	Mar 19 01:01:02 PM PDT 24
Peak memory	211464 kb
Host	smart-aacbe9cb-ee9e-4877-8275-fbd4cfe898e8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579657004 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3579657004
Directory	/workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3971288625
Short name	T1016
Test name
Test status
Simulation time	27196695 ps
CPU time	0.64 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:54 PM PDT 24
Peak memory	201852 kb
Host	smart-457770a5-4e8b-41c6-bea9-e36d15441bf4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971288625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.3971288625
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4024950741
Short name	T89
Test name
Test status
Simulation time	2598820208 ps
CPU time	3.38 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:50 PM PDT 24
Peak memory	202244 kb
Host	smart-1349b1b0-34ff-4fa9-97a8-48cbbe8e8a6b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024950741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.4024950741
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4024097183
Short name	T966
Test name
Test status
Simulation time	25716318 ps
CPU time	0.72 seconds
Started	Mar 19 01:00:50 PM PDT 24
Finished	Mar 19 01:00:51 PM PDT 24
Peak memory	201952 kb
Host	smart-d42cf3b6-8fd2-4a51-9112-46ffd872dffa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024097183 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.4024097183
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2751022874
Short name	T980
Test name
Test status
Simulation time	680773149 ps
CPU time	2.75 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:49 PM PDT 24
Peak memory	202140 kb
Host	smart-d21f269c-727e-450b-8b65-7e21aa81f1a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751022874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2751022874
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1753307788
Short name	T135
Test name
Test status
Simulation time	657948471 ps
CPU time	2.38 seconds
Started	Mar 19 01:00:46 PM PDT 24
Finished	Mar 19 01:00:48 PM PDT 24
Peak memory	202064 kb
Host	smart-da883457-2017-49a8-b691-439c64dc07cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753307788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.1753307788
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.953372240
Short name	T947
Test name
Test status
Simulation time	72877946 ps
CPU time	0.75 seconds
Started	Mar 19 01:00:51 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	201940 kb
Host	smart-3220d685-9e04-4e94-b6ce-bb7dbfffeefd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953372240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.953372240
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2307335905
Short name	T66
Test name
Test status
Simulation time	54234662 ps
CPU time	1.21 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	201944 kb
Host	smart-0f6f984f-bb92-4e87-8cb7-c96f10201fac
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307335905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2307335905
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1575912242
Short name	T68
Test name
Test status
Simulation time	26531997 ps
CPU time	0.66 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	201920 kb
Host	smart-2c78d1b9-37a5-4bab-b3dd-5b1c609700f2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575912242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1575912242
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1904347827
Short name	T959
Test name
Test status
Simulation time	31057772 ps
CPU time	1.02 seconds
Started	Mar 19 01:00:51 PM PDT 24
Finished	Mar 19 01:00:52 PM PDT 24
Peak memory	210184 kb
Host	smart-91254c25-9177-49e8-a460-874dd305a919
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904347827 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1904347827
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3853082802
Short name	T991
Test name
Test status
Simulation time	14893101 ps
CPU time	0.65 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	201876 kb
Host	smart-e4dd4834-5fd4-44a9-910d-0351cff49e1e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853082802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3853082802
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3855695346
Short name	T1011
Test name
Test status
Simulation time	2617768585 ps
CPU time	3.64 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:57 PM PDT 24
Peak memory	202328 kb
Host	smart-6601d104-bd7f-4ef8-bfcd-00112a38687c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855695346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3855695346
Directory	/workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1136220754
Short name	T993
Test name
Test status
Simulation time	51964615 ps
CPU time	0.8 seconds
Started	Mar 19 01:00:50 PM PDT 24
Finished	Mar 19 01:00:51 PM PDT 24
Peak memory	202004 kb
Host	smart-afb334bd-452d-4318-91f6-667a4810d825
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136220754 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1136220754
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.504331649
Short name	T986
Test name
Test status
Simulation time	454782358 ps
CPU time	4.17 seconds
Started	Mar 19 01:00:51 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	202088 kb
Host	smart-1248ed81-71ca-4c21-b8e4-80661929b3b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504331649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.504331649
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2609992417
Short name	T138
Test name
Test status
Simulation time	908391807 ps
CPU time	2.49 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	202088 kb
Host	smart-822bb300-f000-45fb-8e50-f397be9e5d6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609992417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2609992417
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3343020135
Short name	T973
Test name
Test status
Simulation time	95327158 ps
CPU time	1.72 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	212840 kb
Host	smart-f809fcaa-4a30-49a7-a98b-a7d049ac4ad7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343020135 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3343020135
Directory	/workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.610117396
Short name	T1006
Test name
Test status
Simulation time	20877816 ps
CPU time	0.65 seconds
Started	Mar 19 01:00:50 PM PDT 24
Finished	Mar 19 01:00:51 PM PDT 24
Peak memory	201844 kb
Host	smart-ad1399f8-ebcb-4f8d-8c8d-1cde18b10000
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610117396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.610117396
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1845415547
Short name	T86
Test name
Test status
Simulation time	507820933 ps
CPU time	2.98 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	202192 kb
Host	smart-360644dd-a998-443f-a3eb-d57eb9e48ae1
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845415547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1845415547
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3851783021
Short name	T944
Test name
Test status
Simulation time	15094192 ps
CPU time	0.75 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	202016 kb
Host	smart-bf4c025f-69ef-4988-929c-4dda3c314697
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851783021 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3851783021
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3106760510
Short name	T938
Test name
Test status
Simulation time	47105046 ps
CPU time	4.14 seconds
Started	Mar 19 01:00:58 PM PDT 24
Finished	Mar 19 01:01:03 PM PDT 24
Peak memory	202140 kb
Host	smart-d3099d8a-a14f-48b6-b7bd-d3caf94b5643
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106760510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.3106760510
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2885903171
Short name	T112
Test name
Test status
Simulation time	1923868809 ps
CPU time	2.89 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	202036 kb
Host	smart-1bcb9ccd-5bf0-493d-b896-1048aaea758b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885903171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2885903171
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3998419211
Short name	T120
Test name
Test status
Simulation time	161019792 ps
CPU time	1.45 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	211480 kb
Host	smart-9fd85a42-3539-4655-b9fd-cb18ac2eeb56
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998419211 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3998419211
Directory	/workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3585672113
Short name	T108
Test name
Test status
Simulation time	36468681 ps
CPU time	0.69 seconds
Started	Mar 19 01:00:51 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	201872 kb
Host	smart-5a33e6bd-958d-458c-92c0-03d887b42633
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585672113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.3585672113
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.591914853
Short name	T70
Test name
Test status
Simulation time	2363351780 ps
CPU time	2.88 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	202248 kb
Host	smart-ea32184d-c4c5-4e71-9f5f-3199b4da4ab3
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591914853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.591914853
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3581367320
Short name	T1015
Test name
Test status
Simulation time	47502410 ps
CPU time	0.76 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:55 PM PDT 24
Peak memory	201980 kb
Host	smart-754b66ad-0634-445a-91d5-1cadd944e3f5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581367320 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3581367320
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.221497127
Short name	T979
Test name
Test status
Simulation time	351180050 ps
CPU time	3.42 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:57 PM PDT 24
Peak memory	202136 kb
Host	smart-cd5842da-4408-4d3b-98d1-b1275bbad094
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221497127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.221497127
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3097424888
Short name	T992
Test name
Test status
Simulation time	1217724565 ps
CPU time	2.25 seconds
Started	Mar 19 01:00:53 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	202060 kb
Host	smart-e3972ed9-b884-4358-b80a-5eb14d2e3282
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097424888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.3097424888
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2641963085
Short name	T957
Test name
Test status
Simulation time	30514992 ps
CPU time	1.21 seconds
Started	Mar 19 01:01:01 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	210180 kb
Host	smart-ad0cbb64-7030-4542-bfa5-d4a0313c23b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641963085 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2641963085
Directory	/workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3603844105
Short name	T1002
Test name
Test status
Simulation time	28893424 ps
CPU time	0.68 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	201260 kb
Host	smart-e7679462-129f-4433-a498-23025267f982
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603844105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3603844105
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.822817861
Short name	T90
Test name
Test status
Simulation time	209565342 ps
CPU time	1.92 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:54 PM PDT 24
Peak memory	202056 kb
Host	smart-577c9a4e-88b4-458b-8800-878d573cf09d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822817861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.822817861
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2329550889
Short name	T99
Test name
Test status
Simulation time	21302860 ps
CPU time	0.75 seconds
Started	Mar 19 01:00:52 PM PDT 24
Finished	Mar 19 01:00:53 PM PDT 24
Peak memory	201964 kb
Host	smart-c0a9f9cd-3a66-4cdd-a37c-8a9ccf7d855b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329550889 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2329550889
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4243164687
Short name	T988
Test name
Test status
Simulation time	89055667 ps
CPU time	3.07 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:58 PM PDT 24
Peak memory	202052 kb
Host	smart-e1fcfd8d-0717-4d7a-8516-e9d99ce97f98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243164687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.4243164687
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2610545712
Short name	T1001
Test name
Test status
Simulation time	1052609446 ps
CPU time	1.64 seconds
Started	Mar 19 01:00:54 PM PDT 24
Finished	Mar 19 01:00:56 PM PDT 24
Peak memory	202204 kb
Host	smart-7e592c4a-6365-4027-b551-b154b0d73008
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610545712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2610545712
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.924187058
Short name	T953
Test name
Test status
Simulation time	37578353 ps
CPU time	1.3 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:06 PM PDT 24
Peak memory	210236 kb
Host	smart-518de088-1fe7-4f64-8864-c9ffdffef7d8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924187058 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.924187058
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2316486463
Short name	T945
Test name
Test status
Simulation time	23028902 ps
CPU time	0.65 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201932 kb
Host	smart-6827b5d8-cd45-4554-832f-8f9cffdb7480
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316486463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2316486463
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2651602418
Short name	T76
Test name
Test status
Simulation time	297564768 ps
CPU time	1.88 seconds
Started	Mar 19 01:01:03 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202064 kb
Host	smart-4727f7cb-c2f0-4ae7-8448-2f2cabe009dc
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651602418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2651602418
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1479761654
Short name	T102
Test name
Test status
Simulation time	17514240 ps
CPU time	0.72 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201968 kb
Host	smart-6ef27bc6-1615-4e49-bbd6-eb74368ee852
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479761654 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1479761654
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3916236886
Short name	T1021
Test name
Test status
Simulation time	38429222 ps
CPU time	3.62 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:07 PM PDT 24
Peak memory	202096 kb
Host	smart-6dfad361-a8b4-42aa-bcab-58693652c4f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916236886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.3916236886
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1833353789
Short name	T997
Test name
Test status
Simulation time	787614282 ps
CPU time	2.47 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:06 PM PDT 24
Peak memory	202120 kb
Host	smart-6ba00516-a07b-4c4c-9f9f-1998df96fc8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833353789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.1833353789
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3704170766
Short name	T1010
Test name
Test status
Simulation time	39398317 ps
CPU time	1.42 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	211236 kb
Host	smart-001026e9-b302-4ce9-8b00-9b0bf519ee9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704170766 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3704170766
Directory	/workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2915248450
Short name	T69
Test name
Test status
Simulation time	16677324 ps
CPU time	0.67 seconds
Started	Mar 19 01:01:06 PM PDT 24
Finished	Mar 19 01:01:07 PM PDT 24
Peak memory	201316 kb
Host	smart-098e8125-4fae-45b0-84a1-da01f6467cc3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915248450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2915248450
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4033654169
Short name	T93
Test name
Test status
Simulation time	419330866 ps
CPU time	2.91 seconds
Started	Mar 19 01:01:03 PM PDT 24
Finished	Mar 19 01:01:06 PM PDT 24
Peak memory	202220 kb
Host	smart-c2b87c4f-cee1-4afa-a503-97692b62bb7b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033654169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.4033654169
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3592752426
Short name	T961
Test name
Test status
Simulation time	14735145 ps
CPU time	0.73 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:04 PM PDT 24
Peak memory	201960 kb
Host	smart-edbcf697-b9de-4af4-acf4-5feda7f35c11
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592752426 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3592752426
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3123006149
Short name	T939
Test name
Test status
Simulation time	144567274 ps
CPU time	2.13 seconds
Started	Mar 19 01:01:04 PM PDT 24
Finished	Mar 19 01:01:08 PM PDT 24
Peak memory	202172 kb
Host	smart-35d07822-e933-41b9-a5e1-156da6187cb0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123006149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3123006149
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1863061816
Short name	T137
Test name
Test status
Simulation time	118834725 ps
CPU time	1.55 seconds
Started	Mar 19 01:01:02 PM PDT 24
Finished	Mar 19 01:01:05 PM PDT 24
Peak memory	202164 kb
Host	smart-125dc1dc-0eaf-4303-930f-8c9d3b71011d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863061816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1863061816
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3704758844
Short name	T19
Test name
Test status
Simulation time	5122022202 ps
CPU time	536.85 seconds
Started	Mar 19 01:21:03 PM PDT 24
Finished	Mar 19 01:30:00 PM PDT 24
Peak memory	358688 kb
Host	smart-f9887e35-1deb-4873-936e-36494df35ff0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704758844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3704758844
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.3826971884
Short name	T425
Test name
Test status
Simulation time	12078717 ps
CPU time	0.65 seconds
Started	Mar 19 01:21:06 PM PDT 24
Finished	Mar 19 01:21:06 PM PDT 24
Peak memory	202068 kb
Host	smart-2449d491-285a-405b-91a3-704958c8c490
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826971884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3826971884
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.1129761008
Short name	T225
Test name
Test status
Simulation time	2507337705 ps
CPU time	22.37 seconds
Started	Mar 19 01:21:01 PM PDT 24
Finished	Mar 19 01:21:24 PM PDT 24
Peak memory	203340 kb
Host	smart-1398a6d7-9208-4c93-af3e-85838af17bcb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129761008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 1129761008
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.1591472773
Short name	T850
Test name
Test status
Simulation time	31387045531 ps
CPU time	1251.28 seconds
Started	Mar 19 01:21:03 PM PDT 24
Finished	Mar 19 01:41:54 PM PDT 24
Peak memory	373112 kb
Host	smart-097f1536-ab6d-4bd3-9048-7cfbb126113d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591472773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.1591472773
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.653798041
Short name	T759
Test name
Test status
Simulation time	428443175 ps
CPU time	2.4 seconds
Started	Mar 19 01:21:03 PM PDT 24
Finished	Mar 19 01:21:06 PM PDT 24
Peak memory	203240 kb
Host	smart-fa6dbdb8-3711-4622-9d56-8da7d3065408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653798041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.653798041
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.124989115
Short name	T546
Test name
Test status
Simulation time	437753494 ps
CPU time	70.42 seconds
Started	Mar 19 01:21:04 PM PDT 24
Finished	Mar 19 01:22:15 PM PDT 24
Peak memory	324888 kb
Host	smart-7771c7ed-9d2f-45f1-84e8-ceb5ee24edf3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124989115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.sram_ctrl_max_throughput.124989115
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.951290025
Short name	T816
Test name
Test status
Simulation time	154669282 ps
CPU time	5.03 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:21:12 PM PDT 24
Peak memory	211444 kb
Host	smart-89389bd7-d88c-461c-bf6d-2cc4aae85f93
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951290025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.951290025
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.4107804271
Short name	T624
Test name
Test status
Simulation time	498749068 ps
CPU time	5.1 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:21:12 PM PDT 24
Peak memory	203304 kb
Host	smart-b2606325-b0a1-457b-a410-18771803266d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107804271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.4107804271
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.3831519663
Short name	T600
Test name
Test status
Simulation time	2910337763 ps
CPU time	1306.26 seconds
Started	Mar 19 01:21:02 PM PDT 24
Finished	Mar 19 01:42:49 PM PDT 24
Peak memory	368960 kb
Host	smart-1d5437bd-668e-4e28-9405-aaace0b82534
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831519663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3831519663
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.3823345104
Short name	T160
Test name
Test status
Simulation time	261756459 ps
CPU time	12.82 seconds
Started	Mar 19 01:21:04 PM PDT 24
Finished	Mar 19 01:21:17 PM PDT 24
Peak memory	203092 kb
Host	smart-a02cc56d-8387-4bc9-9822-4bd0429dc949
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823345104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3823345104
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3542012635
Short name	T329
Test name
Test status
Simulation time	88879365189 ps
CPU time	591.85 seconds
Started	Mar 19 01:21:01 PM PDT 24
Finished	Mar 19 01:30:53 PM PDT 24
Peak memory	203360 kb
Host	smart-36e6619f-03ae-4067-9c2f-1f8c528e88cb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542012635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3542012635
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.1412170347
Short name	T736
Test name
Test status
Simulation time	79414388 ps
CPU time	0.79 seconds
Started	Mar 19 01:21:02 PM PDT 24
Finished	Mar 19 01:21:03 PM PDT 24
Peak memory	203260 kb
Host	smart-d27bcc85-bad7-43ec-8c6b-fdc5b47750c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412170347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1412170347
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.2734809407
Short name	T862
Test name
Test status
Simulation time	3642370353 ps
CPU time	661.86 seconds
Started	Mar 19 01:21:03 PM PDT 24
Finished	Mar 19 01:32:05 PM PDT 24
Peak memory	357912 kb
Host	smart-5c7ef5fc-ff2e-4ab1-9a08-1c9b8cd4993a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734809407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2734809407
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.2331166004
Short name	T308
Test name
Test status
Simulation time	99862311 ps
CPU time	2.02 seconds
Started	Mar 19 01:21:02 PM PDT 24
Finished	Mar 19 01:21:04 PM PDT 24
Peak memory	203120 kb
Host	smart-396a50a2-5704-428d-89ea-d2a7e0af2762
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331166004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2331166004
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all.3153141509
Short name	T643
Test name
Test status
Simulation time	6211230581 ps
CPU time	1527.01 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:46:34 PM PDT 24
Peak memory	376152 kb
Host	smart-3b4f214a-f93d-4461-b64a-967d72ffd4cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153141509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.3153141509
Directory	/workspace/0.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1987631711
Short name	T52
Test name
Test status
Simulation time	1240586823 ps
CPU time	338.13 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:26:46 PM PDT 24
Peak memory	378844 kb
Host	smart-9f08a1f4-7cf5-4fd4-a82b-30eca4649297
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1987631711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1987631711
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1068916749
Short name	T377
Test name
Test status
Simulation time	15658332638 ps
CPU time	165.42 seconds
Started	Mar 19 01:21:01 PM PDT 24
Finished	Mar 19 01:23:47 PM PDT 24
Peak memory	203304 kb
Host	smart-8ad82b13-6ad2-4664-b024-21f597dfba03
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068916749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.1068916749
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2801860114
Short name	T446
Test name
Test status
Simulation time	247277523 ps
CPU time	8.75 seconds
Started	Mar 19 01:21:02 PM PDT 24
Finished	Mar 19 01:21:12 PM PDT 24
Peak memory	241612 kb
Host	smart-eb46f8b2-82aa-4063-81a8-c5bc78024e90
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801860114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2801860114
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1916068274
Short name	T263
Test name
Test status
Simulation time	3998217379 ps
CPU time	883.88 seconds
Started	Mar 19 01:21:15 PM PDT 24
Finished	Mar 19 01:35:59 PM PDT 24
Peak memory	373120 kb
Host	smart-e582c00c-65e0-4976-b528-c6f005a69492
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916068274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.1916068274
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.1127195701
Short name	T924
Test name
Test status
Simulation time	15650575 ps
CPU time	0.68 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:21:15 PM PDT 24
Peak memory	202984 kb
Host	smart-a699f28b-d621-476e-af9f-1b63b1160ca3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127195701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1127195701
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.2271705861
Short name	T772
Test name
Test status
Simulation time	1639771706 ps
CPU time	17.43 seconds
Started	Mar 19 01:21:08 PM PDT 24
Finished	Mar 19 01:21:25 PM PDT 24
Peak memory	203112 kb
Host	smart-b20408ac-dba9-4b92-a3a0-bada97c7e201
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271705861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 2271705861
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_executable.1470300546
Short name	T478
Test name
Test status
Simulation time	937064726 ps
CPU time	339.46 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:26:53 PM PDT 24
Peak memory	369260 kb
Host	smart-2d90a035-927f-4f3f-9412-e3902ca3de8b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470300546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1470300546
Directory	/workspace/1.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.14281676
Short name	T466
Test name
Test status
Simulation time	466028154 ps
CPU time	6.68 seconds
Started	Mar 19 01:21:05 PM PDT 24
Finished	Mar 19 01:21:12 PM PDT 24
Peak memory	203264 kb
Host	smart-155f09fb-7d5c-4f62-85d3-fbb1ccc584a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14281676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escal ation.14281676
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.816837456
Short name	T607
Test name
Test status
Simulation time	523051079 ps
CPU time	29.72 seconds
Started	Mar 19 01:21:06 PM PDT 24
Finished	Mar 19 01:21:36 PM PDT 24
Peak memory	277924 kb
Host	smart-04a9c5d2-ecb6-4bc9-84d3-fd7fba54dff3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816837456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.sram_ctrl_max_throughput.816837456
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1795082254
Short name	T721
Test name
Test status
Simulation time	82221271 ps
CPU time	2.61 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:21:16 PM PDT 24
Peak memory	211540 kb
Host	smart-2feb31ac-3a06-4451-8895-fd7015956f64
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795082254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1795082254
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.4248728100
Short name	T260
Test name
Test status
Simulation time	1683192288 ps
CPU time	5.28 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:21:24 PM PDT 24
Peak memory	203260 kb
Host	smart-809cd786-5bcf-4a0b-9061-0fdd7cc67387
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248728100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.4248728100
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.1382989685
Short name	T489
Test name
Test status
Simulation time	10758679113 ps
CPU time	660.06 seconds
Started	Mar 19 01:21:06 PM PDT 24
Finished	Mar 19 01:32:06 PM PDT 24
Peak memory	374356 kb
Host	smart-4c70505f-d2e3-43fc-8234-b6fef737347b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382989685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.1382989685
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.1798316864
Short name	T693
Test name
Test status
Simulation time	658338036 ps
CPU time	131.09 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:23:19 PM PDT 24
Peak memory	368828 kb
Host	smart-5a3040be-7f67-4434-83b2-4b69aa6ad2d9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798316864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1798316864
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2656242114
Short name	T106
Test name
Test status
Simulation time	52098088316 ps
CPU time	383.07 seconds
Started	Mar 19 01:21:06 PM PDT 24
Finished	Mar 19 01:27:30 PM PDT 24
Peak memory	203356 kb
Host	smart-84f5fd18-837d-4645-bef8-307d8868babe
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656242114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.2656242114
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.1143343456
Short name	T434
Test name
Test status
Simulation time	122278621 ps
CPU time	0.75 seconds
Started	Mar 19 01:21:15 PM PDT 24
Finished	Mar 19 01:21:16 PM PDT 24
Peak memory	203216 kb
Host	smart-dbc45621-8c03-41f5-bde8-6427a4dab4e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143343456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1143343456
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.3704278668
Short name	T412
Test name
Test status
Simulation time	27199735824 ps
CPU time	1022.08 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:38:15 PM PDT 24
Peak memory	374380 kb
Host	smart-c889e145-b3d0-4387-a18c-ef51e8906ee3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704278668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3704278668
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_sec_cm.2366628289
Short name	T33
Test name
Test status
Simulation time	344595259 ps
CPU time	1.76 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:24 PM PDT 24
Peak memory	224936 kb
Host	smart-37b2fc30-59de-4432-958b-df585803946b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366628289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2366628289
Directory	/workspace/1.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.78057753
Short name	T828
Test name
Test status
Simulation time	207765289 ps
CPU time	12.14 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:21:19 PM PDT 24
Peak memory	203172 kb
Host	smart-4ec7323b-b410-4f0e-8cc0-2379f1cae220
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78057753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.78057753
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all.1532512751
Short name	T502
Test name
Test status
Simulation time	14203095553 ps
CPU time	1594.82 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:47:48 PM PDT 24
Peak memory	376080 kb
Host	smart-8e5cb3fd-822e-4b81-820d-f5d6e9d73fec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532512751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1532512751
Directory	/workspace/1.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3715794100
Short name	T366
Test name
Test status
Simulation time	2485976563 ps
CPU time	103.22 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	313240 kb
Host	smart-1420a1f4-e954-452c-afe9-79cc90315996
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3715794100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3715794100
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2277895812
Short name	T241
Test name
Test status
Simulation time	5335771031 ps
CPU time	266.78 seconds
Started	Mar 19 01:21:07 PM PDT 24
Finished	Mar 19 01:25:34 PM PDT 24
Peak memory	203272 kb
Host	smart-4f9c69f8-d547-4dc3-bc15-687add85821f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277895812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.2277895812
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3317795512
Short name	T629
Test name
Test status
Simulation time	266767091 ps
CPU time	93.48 seconds
Started	Mar 19 01:21:08 PM PDT 24
Finished	Mar 19 01:22:41 PM PDT 24
Peak memory	348568 kb
Host	smart-2b86b48a-ea9c-4ed0-9a51-779dd2abaf29
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317795512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3317795512
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.571671529
Short name	T4
Test name
Test status
Simulation time	21879716012 ps
CPU time	1138.99 seconds
Started	Mar 19 01:21:51 PM PDT 24
Finished	Mar 19 01:40:51 PM PDT 24
Peak memory	373052 kb
Host	smart-abad0497-6f5a-462a-af63-ccf59299fb76
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571671529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_access_during_key_req.571671529
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.1611731008
Short name	T379
Test name
Test status
Simulation time	21034385 ps
CPU time	0.7 seconds
Started	Mar 19 01:21:55 PM PDT 24
Finished	Mar 19 01:21:56 PM PDT 24
Peak memory	203020 kb
Host	smart-ea372763-efa1-4860-a41d-c06b752c0bab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611731008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1611731008
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.249850687
Short name	T350
Test name
Test status
Simulation time	6950272535 ps
CPU time	33.14 seconds
Started	Mar 19 01:21:53 PM PDT 24
Finished	Mar 19 01:22:27 PM PDT 24
Peak memory	203076 kb
Host	smart-5fc75e3d-b0f9-46f0-bd0c-018a5cf08d2f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249850687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 249850687
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.1791504066
Short name	T587
Test name
Test status
Simulation time	40753374445 ps
CPU time	1360.14 seconds
Started	Mar 19 01:21:56 PM PDT 24
Finished	Mar 19 01:44:36 PM PDT 24
Peak memory	375040 kb
Host	smart-8aad8ba7-0efd-4b25-9e02-fef77002a596
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791504066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1791504066
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.2018005016
Short name	T387
Test name
Test status
Simulation time	1138079807 ps
CPU time	3.81 seconds
Started	Mar 19 01:21:48 PM PDT 24
Finished	Mar 19 01:21:53 PM PDT 24
Peak memory	203224 kb
Host	smart-98164d12-8fb9-4bea-8fc1-66e3dbde32c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018005016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2018005016
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.4222878823
Short name	T440
Test name
Test status
Simulation time	80513439 ps
CPU time	2.05 seconds
Started	Mar 19 01:21:48 PM PDT 24
Finished	Mar 19 01:21:52 PM PDT 24
Peak memory	211392 kb
Host	smart-fbac5fd4-d58f-407b-98cf-780a6379b715
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222878823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.4222878823
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.713178325
Short name	T73
Test name
Test status
Simulation time	120852843 ps
CPU time	4.12 seconds
Started	Mar 19 01:21:54 PM PDT 24
Finished	Mar 19 01:21:58 PM PDT 24
Peak memory	211448 kb
Host	smart-bb8d13a4-0002-4f1e-acb6-eddca32a4eec
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713178325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.713178325
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.2432444863
Short name	T183
Test name
Test status
Simulation time	2627991602 ps
CPU time	10.5 seconds
Started	Mar 19 01:21:53 PM PDT 24
Finished	Mar 19 01:22:04 PM PDT 24
Peak memory	203168 kb
Host	smart-b5c1b355-57c4-44df-b51d-8c6894f5b126
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432444863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2432444863
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.2322209359
Short name	T882
Test name
Test status
Simulation time	9357819931 ps
CPU time	1067.01 seconds
Started	Mar 19 01:21:50 PM PDT 24
Finished	Mar 19 01:39:37 PM PDT 24
Peak memory	376172 kb
Host	smart-bb0d3ce7-9aa9-4733-8810-f37a5b77a4fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322209359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2322209359
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.2543948052
Short name	T820
Test name
Test status
Simulation time	965568251 ps
CPU time	20.75 seconds
Started	Mar 19 01:21:48 PM PDT 24
Finished	Mar 19 01:22:09 PM PDT 24
Peak memory	257664 kb
Host	smart-6fc990cd-1367-4ec7-87a8-d578411123dd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543948052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.2543948052
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2165768363
Short name	T372
Test name
Test status
Simulation time	38582270414 ps
CPU time	245.99 seconds
Started	Mar 19 01:21:51 PM PDT 24
Finished	Mar 19 01:25:58 PM PDT 24
Peak memory	203296 kb
Host	smart-ce9483d1-351f-42e3-a4b8-2fb58f34240b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165768363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.2165768363
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.440996288
Short name	T710
Test name
Test status
Simulation time	28158024 ps
CPU time	0.78 seconds
Started	Mar 19 01:21:55 PM PDT 24
Finished	Mar 19 01:21:56 PM PDT 24
Peak memory	203260 kb
Host	smart-6db1131f-2476-4f2d-8e6a-6f5afea6c5b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440996288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.440996288
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.3161937252
Short name	T860
Test name
Test status
Simulation time	12948606451 ps
CPU time	1640.16 seconds
Started	Mar 19 01:21:56 PM PDT 24
Finished	Mar 19 01:49:16 PM PDT 24
Peak memory	375504 kb
Host	smart-30e0abf9-7ad5-4a1f-b20a-502a28fc62f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161937252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3161937252
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.2187583652
Short name	T269
Test name
Test status
Simulation time	3094402956 ps
CPU time	16.57 seconds
Started	Mar 19 01:21:54 PM PDT 24
Finished	Mar 19 01:22:11 PM PDT 24
Peak memory	203272 kb
Host	smart-c2082a6d-3867-415c-a277-0f9e1bc0a524
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187583652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2187583652
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.2743790959
Short name	T590
Test name
Test status
Simulation time	78896773298 ps
CPU time	1355.88 seconds
Started	Mar 19 01:21:55 PM PDT 24
Finished	Mar 19 01:44:31 PM PDT 24
Peak memory	375144 kb
Host	smart-e03ebfee-8389-4837-aaba-2f81f039e0c5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743790959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.2743790959
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.139079288
Short name	T735
Test name
Test status
Simulation time	20680288675 ps
CPU time	315.74 seconds
Started	Mar 19 01:21:55 PM PDT 24
Finished	Mar 19 01:27:11 PM PDT 24
Peak memory	347632 kb
Host	smart-e6139e01-9b3c-466f-9f01-1232e301f903
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=139079288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.139079288
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2519313060
Short name	T280
Test name
Test status
Simulation time	1292783577 ps
CPU time	123.27 seconds
Started	Mar 19 01:21:49 PM PDT 24
Finished	Mar 19 01:23:53 PM PDT 24
Peak memory	203284 kb
Host	smart-e4340941-69c0-4517-b09e-b6c678608823
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519313060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2519313060
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.217657075
Short name	T188
Test name
Test status
Simulation time	367692421 ps
CPU time	31.49 seconds
Started	Mar 19 01:21:48 PM PDT 24
Finished	Mar 19 01:22:21 PM PDT 24
Peak memory	277760 kb
Host	smart-dd2f50e7-5a9c-4007-97ce-0f4a947ded44
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217657075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.217657075
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.770139446
Short name	T562
Test name
Test status
Simulation time	3433466713 ps
CPU time	748.21 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:34:32 PM PDT 24
Peak memory	367304 kb
Host	smart-709c2c49-c728-4100-ab84-d9f56f190b6e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770139446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_access_during_key_req.770139446
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.1422835173
Short name	T23
Test name
Test status
Simulation time	118706365 ps
CPU time	0.66 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:22:03 PM PDT 24
Peak memory	202976 kb
Host	smart-b7b341c7-0b37-498f-a105-87f48eb4acbf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422835173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1422835173
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.3732077853
Short name	T533
Test name
Test status
Simulation time	3582987806 ps
CPU time	39.92 seconds
Started	Mar 19 01:21:55 PM PDT 24
Finished	Mar 19 01:22:35 PM PDT 24
Peak memory	203216 kb
Host	smart-4298f6f5-927c-4573-9fee-9c075a5c35f9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732077853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3732077853
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.4097079698
Short name	T677
Test name
Test status
Simulation time	10044067490 ps
CPU time	1531.93 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:47:34 PM PDT 24
Peak memory	367820 kb
Host	smart-06e568a9-63ae-4291-97cf-0b562fec1fd1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097079698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.4097079698
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.2791824159
Short name	T582
Test name
Test status
Simulation time	410788623 ps
CPU time	4.33 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:22:06 PM PDT 24
Peak memory	203248 kb
Host	smart-ea87c886-f630-46ae-8d46-3034c9c625e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791824159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.2791824159
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.468893982
Short name	T933
Test name
Test status
Simulation time	565841423 ps
CPU time	163.74 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:24:47 PM PDT 24
Peak memory	368212 kb
Host	smart-fc995fe9-9aaf-4c89-82bb-c53bed1d0ce6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468893982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.468893982
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3188707460
Short name	T689
Test name
Test status
Simulation time	86633229 ps
CPU time	2.54 seconds
Started	Mar 19 01:22:01 PM PDT 24
Finished	Mar 19 01:22:04 PM PDT 24
Peak memory	211408 kb
Host	smart-c26aa4c5-4670-41c1-a257-0025da59cab5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188707460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3188707460
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.4043870746
Short name	T627
Test name
Test status
Simulation time	281156200 ps
CPU time	4.4 seconds
Started	Mar 19 01:22:06 PM PDT 24
Finished	Mar 19 01:22:11 PM PDT 24
Peak memory	203252 kb
Host	smart-6a202aab-2a6b-4b13-bb9b-17df7a21b929
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043870746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.4043870746
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.1870070377
Short name	T876
Test name
Test status
Simulation time	16463328289 ps
CPU time	1227.66 seconds
Started	Mar 19 01:21:54 PM PDT 24
Finished	Mar 19 01:42:22 PM PDT 24
Peak memory	370916 kb
Host	smart-e6cf96cf-6622-4aca-afa8-01b6b552af2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870070377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.1870070377
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.181297947
Short name	T448
Test name
Test status
Simulation time	250376280 ps
CPU time	12.66 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:22:16 PM PDT 24
Peak memory	203260 kb
Host	smart-7def4953-7139-4088-8658-1a4e9ad5b5a6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181297947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s ram_ctrl_partial_access.181297947
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.482305279
Short name	T284
Test name
Test status
Simulation time	4424439105 ps
CPU time	303.23 seconds
Started	Mar 19 01:22:01 PM PDT 24
Finished	Mar 19 01:27:05 PM PDT 24
Peak memory	203340 kb
Host	smart-dbac9f8f-272b-4690-b2b8-f87b1ba5dd21
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482305279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.sram_ctrl_partial_access_b2b.482305279
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.1409465714
Short name	T420
Test name
Test status
Simulation time	35295922 ps
CPU time	0.76 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:22:04 PM PDT 24
Peak memory	203256 kb
Host	smart-7de60fd0-083f-457c-8ebc-18ae15b8c8e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409465714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1409465714
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.3779694275
Short name	T699
Test name
Test status
Simulation time	25387801426 ps
CPU time	953.42 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:37:55 PM PDT 24
Peak memory	374024 kb
Host	smart-af20c6cd-d4bc-4e3a-9a71-fe6b20227e89
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779694275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3779694275
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.3166495595
Short name	T226
Test name
Test status
Simulation time	83608750 ps
CPU time	4.62 seconds
Started	Mar 19 01:21:54 PM PDT 24
Finished	Mar 19 01:21:59 PM PDT 24
Peak memory	203240 kb
Host	smart-ed3e2438-ba0d-4f5d-9639-4a8fe24a3d09
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166495595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3166495595
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all.64973734
Short name	T784
Test name
Test status
Simulation time	57421308028 ps
CPU time	3236.35 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 02:15:59 PM PDT 24
Peak memory	373624 kb
Host	smart-3f9c1a58-828a-498d-ac02-15012e866066
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64973734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.sram_ctrl_stress_all.64973734
Directory	/workspace/11.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2465513175
Short name	T519
Test name
Test status
Simulation time	2562182818 ps
CPU time	232.63 seconds
Started	Mar 19 01:21:54 PM PDT 24
Finished	Mar 19 01:25:47 PM PDT 24
Peak memory	203292 kb
Host	smart-3eaa257d-2d84-4c3e-8ab6-b3b450ea8785
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465513175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2465513175
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1580502797
Short name	T630
Test name
Test status
Simulation time	1300362486 ps
CPU time	151.5 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:24:34 PM PDT 24
Peak memory	367656 kb
Host	smart-4352ee6d-ee6c-4461-be78-25c67e831b74
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580502797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1580502797
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1904744892
Short name	T873
Test name
Test status
Simulation time	9177693707 ps
CPU time	533.06 seconds
Started	Mar 19 01:22:08 PM PDT 24
Finished	Mar 19 01:31:01 PM PDT 24
Peak memory	339964 kb
Host	smart-ea0db918-13e4-48b1-88fb-fabdb160aff3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904744892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1904744892
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.2008802301
Short name	T331
Test name
Test status
Simulation time	14996098 ps
CPU time	0.67 seconds
Started	Mar 19 01:22:09 PM PDT 24
Finished	Mar 19 01:22:10 PM PDT 24
Peak memory	202352 kb
Host	smart-1118e8f0-6e0a-486b-a798-08ee85d3f6ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008802301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2008802301
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.1468785835
Short name	T349
Test name
Test status
Simulation time	4342177383 ps
CPU time	23.76 seconds
Started	Mar 19 01:22:00 PM PDT 24
Finished	Mar 19 01:22:24 PM PDT 24
Peak memory	203308 kb
Host	smart-02fadd0a-b5c4-4b61-97bc-62ecf454336e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468785835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1468785835
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.4099277207
Short name	T154
Test name
Test status
Simulation time	8658750720 ps
CPU time	217.25 seconds
Started	Mar 19 01:22:07 PM PDT 24
Finished	Mar 19 01:25:45 PM PDT 24
Peak memory	350836 kb
Host	smart-911c0327-58bb-4d02-b5d7-f4a8b3a3a075
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099277207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.4099277207
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.951721525
Short name	T857
Test name
Test status
Simulation time	379212339 ps
CPU time	5.25 seconds
Started	Mar 19 01:22:11 PM PDT 24
Finished	Mar 19 01:22:17 PM PDT 24
Peak memory	203188 kb
Host	smart-bcb6de68-46e3-4741-a039-3116255fd53a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951721525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc alation.951721525
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.1390279590
Short name	T479
Test name
Test status
Simulation time	174221765 ps
CPU time	1.26 seconds
Started	Mar 19 01:22:11 PM PDT 24
Finished	Mar 19 01:22:13 PM PDT 24
Peak memory	211216 kb
Host	smart-55f84721-e2c1-4993-8471-02717159d4a9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390279590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.1390279590
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.505881373
Short name	T83
Test name
Test status
Simulation time	70135018 ps
CPU time	4.79 seconds
Started	Mar 19 01:22:07 PM PDT 24
Finished	Mar 19 01:22:12 PM PDT 24
Peak memory	211528 kb
Host	smart-235b4044-5886-4ef5-b818-26e7c1810a37
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505881373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.505881373
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.1934007745
Short name	T561
Test name
Test status
Simulation time	132921475 ps
CPU time	8.06 seconds
Started	Mar 19 01:22:09 PM PDT 24
Finished	Mar 19 01:22:17 PM PDT 24
Peak memory	203256 kb
Host	smart-e5e1906b-5b11-4fca-9497-f323af9856d1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934007745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1934007745
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3904646227
Short name	T581
Test name
Test status
Simulation time	9742079856 ps
CPU time	1151.77 seconds
Started	Mar 19 01:22:01 PM PDT 24
Finished	Mar 19 01:41:13 PM PDT 24
Peak memory	374076 kb
Host	smart-33bed173-c3c2-45ea-adc0-034f098bd5a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904646227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3904646227
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.784713013
Short name	T767
Test name
Test status
Simulation time	894143309 ps
CPU time	15.81 seconds
Started	Mar 19 01:22:02 PM PDT 24
Finished	Mar 19 01:22:17 PM PDT 24
Peak memory	203284 kb
Host	smart-0ae9b2ad-d7ba-4e44-9424-73255f733000
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784713013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.s ram_ctrl_partial_access.784713013
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3847627838
Short name	T666
Test name
Test status
Simulation time	24286655935 ps
CPU time	288.66 seconds
Started	Mar 19 01:22:04 PM PDT 24
Finished	Mar 19 01:26:53 PM PDT 24
Peak memory	203252 kb
Host	smart-960f6df8-b758-46cf-8492-a54a22a98514
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847627838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3847627838
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.1847349577
Short name	T812
Test name
Test status
Simulation time	32336169 ps
CPU time	0.76 seconds
Started	Mar 19 01:22:09 PM PDT 24
Finished	Mar 19 01:22:10 PM PDT 24
Peak memory	203260 kb
Host	smart-639623c6-8ab2-459d-a566-19c8271e7a70
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847349577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1847349577
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.439606264
Short name	T422
Test name
Test status
Simulation time	1444061810 ps
CPU time	358.7 seconds
Started	Mar 19 01:22:08 PM PDT 24
Finished	Mar 19 01:28:07 PM PDT 24
Peak memory	360140 kb
Host	smart-8b51f1d7-397b-48d4-82d7-58b7f530ce5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439606264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.439606264
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.1651338864
Short name	T311
Test name
Test status
Simulation time	817110004 ps
CPU time	12.76 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:22:16 PM PDT 24
Peak memory	203196 kb
Host	smart-bc132b0a-8243-4901-ab9c-37704dae9baf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651338864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1651338864
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2335616065
Short name	T783
Test name
Test status
Simulation time	17340918552 ps
CPU time	45.62 seconds
Started	Mar 19 01:22:06 PM PDT 24
Finished	Mar 19 01:22:51 PM PDT 24
Peak memory	279244 kb
Host	smart-ae8c2a19-c6ec-422a-beae-850a95d33989
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2335616065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2335616065
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.519769299
Short name	T936
Test name
Test status
Simulation time	4168432521 ps
CPU time	189.32 seconds
Started	Mar 19 01:22:03 PM PDT 24
Finished	Mar 19 01:25:12 PM PDT 24
Peak memory	203368 kb
Host	smart-95ef1ea3-f7a4-4bc5-84b0-72f88ed2f902
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519769299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_stress_pipeline.519769299
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3744371475
Short name	T94
Test name
Test status
Simulation time	575399213 ps
CPU time	90.43 seconds
Started	Mar 19 01:22:08 PM PDT 24
Finished	Mar 19 01:23:38 PM PDT 24
Peak memory	357684 kb
Host	smart-42ec557f-58bf-4a5b-ae8f-c2e83ece989f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744371475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.3744371475
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1253314135
Short name	T297
Test name
Test status
Simulation time	2214794608 ps
CPU time	431.04 seconds
Started	Mar 19 01:22:14 PM PDT 24
Finished	Mar 19 01:29:25 PM PDT 24
Peak memory	361152 kb
Host	smart-2caae559-66c1-4d7b-add6-4f2e0f05ffdd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253314135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1253314135
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.1512296190
Short name	T333
Test name
Test status
Simulation time	27072306 ps
CPU time	0.65 seconds
Started	Mar 19 01:22:13 PM PDT 24
Finished	Mar 19 01:22:14 PM PDT 24
Peak memory	202188 kb
Host	smart-e52ae153-bfa3-4cc6-93b4-0dd24c21b3a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512296190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1512296190
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.373563771
Short name	T586
Test name
Test status
Simulation time	2815326742 ps
CPU time	45.59 seconds
Started	Mar 19 01:22:10 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	203280 kb
Host	smart-d1f8bba3-7441-43b8-97e5-73a101e8340a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373563771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection. 373563771
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.3270486008
Short name	T505
Test name
Test status
Simulation time	3774525698 ps
CPU time	757 seconds
Started	Mar 19 01:22:14 PM PDT 24
Finished	Mar 19 01:34:52 PM PDT 24
Peak memory	374660 kb
Host	smart-ffe79005-db94-4679-8d05-304d30253625
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270486008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3270486008
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.618077320
Short name	T682
Test name
Test status
Simulation time	223060307 ps
CPU time	2.6 seconds
Started	Mar 19 01:22:12 PM PDT 24
Finished	Mar 19 01:22:15 PM PDT 24
Peak memory	211460 kb
Host	smart-e01ccf20-2d77-4026-b1b2-0e4ddcdf633e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618077320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc alation.618077320
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.1193545505
Short name	T175
Test name
Test status
Simulation time	199473610 ps
CPU time	45.38 seconds
Started	Mar 19 01:22:11 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	312944 kb
Host	smart-ede2d891-8d3a-4efb-bec6-d34182ce8ad1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193545505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1193545505
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3733845998
Short name	T739
Test name
Test status
Simulation time	619040892 ps
CPU time	5.43 seconds
Started	Mar 19 01:22:12 PM PDT 24
Finished	Mar 19 01:22:18 PM PDT 24
Peak memory	211420 kb
Host	smart-944195ec-e2b2-4601-a631-2a9bee7361db
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733845998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3733845998
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.1175304203
Short name	T847
Test name
Test status
Simulation time	144315706 ps
CPU time	4.41 seconds
Started	Mar 19 01:22:15 PM PDT 24
Finished	Mar 19 01:22:20 PM PDT 24
Peak memory	203256 kb
Host	smart-28823d7f-efcf-47b1-9613-8a75c1195196
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175304203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.1175304203
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.2874403497
Short name	T554
Test name
Test status
Simulation time	31188364729 ps
CPU time	1459.25 seconds
Started	Mar 19 01:22:07 PM PDT 24
Finished	Mar 19 01:46:27 PM PDT 24
Peak memory	375088 kb
Host	smart-d68e8ff2-3f84-463c-8f25-b1afc097b078
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874403497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.2874403497
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.3991907119
Short name	T300
Test name
Test status
Simulation time	727161156 ps
CPU time	125.2 seconds
Started	Mar 19 01:22:11 PM PDT 24
Finished	Mar 19 01:24:17 PM PDT 24
Peak memory	356788 kb
Host	smart-ed91702f-90d9-4203-ad59-fe665804bdcd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991907119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3991907119
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2923340817
Short name	T534
Test name
Test status
Simulation time	15632595306 ps
CPU time	314.06 seconds
Started	Mar 19 01:22:06 PM PDT 24
Finished	Mar 19 01:27:20 PM PDT 24
Peak memory	203392 kb
Host	smart-70e3d8eb-0c58-4b22-90d1-69f84888c088
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923340817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.2923340817
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.2466091982
Short name	T800
Test name
Test status
Simulation time	28756202 ps
CPU time	0.75 seconds
Started	Mar 19 01:22:11 PM PDT 24
Finished	Mar 19 01:22:13 PM PDT 24
Peak memory	203312 kb
Host	smart-4b9a2707-c89e-41b9-acd0-e40eba51511c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466091982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2466091982
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_regwen.1118278193
Short name	T261
Test name
Test status
Simulation time	2535863474 ps
CPU time	150.37 seconds
Started	Mar 19 01:22:15 PM PDT 24
Finished	Mar 19 01:24:46 PM PDT 24
Peak memory	349436 kb
Host	smart-9f09218b-5f0f-4332-beb0-c4011a412ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118278193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1118278193
Directory	/workspace/13.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.2008366834
Short name	T158
Test name
Test status
Simulation time	379897166 ps
CPU time	11.69 seconds
Started	Mar 19 01:22:09 PM PDT 24
Finished	Mar 19 01:22:20 PM PDT 24
Peak memory	203148 kb
Host	smart-3772aca6-dc2e-4c07-80c7-109d3301baf8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008366834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2008366834
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1257655112
Short name	T894
Test name
Test status
Simulation time	2252026471 ps
CPU time	271.77 seconds
Started	Mar 19 01:22:14 PM PDT 24
Finished	Mar 19 01:26:45 PM PDT 24
Peak memory	366552 kb
Host	smart-6073aea0-b391-4324-9bb5-17ded28c03c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1257655112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1257655112
Directory	/workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1756207887
Short name	T645
Test name
Test status
Simulation time	17700587448 ps
CPU time	247.68 seconds
Started	Mar 19 01:22:08 PM PDT 24
Finished	Mar 19 01:26:16 PM PDT 24
Peak memory	203252 kb
Host	smart-17781e5c-f8f8-4dd2-a53a-04671e36acd7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756207887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1756207887
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2310645220
Short name	T678
Test name
Test status
Simulation time	572162328 ps
CPU time	103.63 seconds
Started	Mar 19 01:22:09 PM PDT 24
Finished	Mar 19 01:23:52 PM PDT 24
Peak memory	354012 kb
Host	smart-dd0e8b98-ab4d-46dd-9caf-8d7ac8611d60
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310645220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2310645220
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2090064726
Short name	T713
Test name
Test status
Simulation time	3733042740 ps
CPU time	1275.04 seconds
Started	Mar 19 01:22:26 PM PDT 24
Finished	Mar 19 01:43:42 PM PDT 24
Peak memory	373100 kb
Host	smart-0533b229-74e3-4a89-8b6b-37a95d3b029a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090064726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.2090064726
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.441535256
Short name	T192
Test name
Test status
Simulation time	10333032 ps
CPU time	0.63 seconds
Started	Mar 19 01:22:26 PM PDT 24
Finished	Mar 19 01:22:27 PM PDT 24
Peak memory	202388 kb
Host	smart-3220e3fd-4fbb-4108-b4cf-db1facdb195d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441535256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.441535256
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.531805195
Short name	T496
Test name
Test status
Simulation time	6710610784 ps
CPU time	81.73 seconds
Started	Mar 19 01:22:17 PM PDT 24
Finished	Mar 19 01:23:38 PM PDT 24
Peak memory	203236 kb
Host	smart-9c5e573f-0aa1-44fc-a961-263879cdd14e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531805195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 531805195
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.4175840218
Short name	T676
Test name
Test status
Simulation time	5920999046 ps
CPU time	7.36 seconds
Started	Mar 19 01:22:25 PM PDT 24
Finished	Mar 19 01:22:34 PM PDT 24
Peak memory	214520 kb
Host	smart-cd4db777-b5ed-4691-a361-2684b3642531
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175840218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.4175840218
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.3567355437
Short name	T386
Test name
Test status
Simulation time	56345628 ps
CPU time	5.23 seconds
Started	Mar 19 01:22:19 PM PDT 24
Finished	Mar 19 01:22:24 PM PDT 24
Peak memory	234884 kb
Host	smart-89747df3-ece6-4648-bee1-c4d02dff6821
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567355437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.3567355437
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1756426611
Short name	T564
Test name
Test status
Simulation time	48987517 ps
CPU time	2.64 seconds
Started	Mar 19 01:22:26 PM PDT 24
Finished	Mar 19 01:22:29 PM PDT 24
Peak memory	211468 kb
Host	smart-b6f134a3-d079-4d25-9e74-7370e1aa5003
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756426611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.1756426611
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.2944501839
Short name	T636
Test name
Test status
Simulation time	272452069 ps
CPU time	4.36 seconds
Started	Mar 19 01:22:23 PM PDT 24
Finished	Mar 19 01:22:28 PM PDT 24
Peak memory	203312 kb
Host	smart-c8c60528-50f3-47c4-8ea5-412c15d077d7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944501839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.2944501839
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.3388983379
Short name	T843
Test name
Test status
Simulation time	4293395749 ps
CPU time	677.46 seconds
Started	Mar 19 01:22:13 PM PDT 24
Finished	Mar 19 01:33:31 PM PDT 24
Peak memory	371248 kb
Host	smart-767b822e-0ceb-4723-91db-757cb80dd252
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388983379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3388983379
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.2939730934
Short name	T419
Test name
Test status
Simulation time	167827315 ps
CPU time	3.23 seconds
Started	Mar 19 01:22:18 PM PDT 24
Finished	Mar 19 01:22:21 PM PDT 24
Peak memory	203240 kb
Host	smart-3e5a46d8-6d6b-4dcd-8836-af20f01846f2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939730934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2939730934
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4057493724
Short name	T103
Test name
Test status
Simulation time	14949747458 ps
CPU time	399.86 seconds
Started	Mar 19 01:22:18 PM PDT 24
Finished	Mar 19 01:28:58 PM PDT 24
Peak memory	203296 kb
Host	smart-4fa637cd-e886-42c7-89a0-4d98b51e8b2f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057493724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.4057493724
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.1879134675
Short name	T652
Test name
Test status
Simulation time	28311738991 ps
CPU time	460.55 seconds
Started	Mar 19 01:22:26 PM PDT 24
Finished	Mar 19 01:30:07 PM PDT 24
Peak memory	352564 kb
Host	smart-8d8b6fe3-4ac9-4877-98a2-3d47171764ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879134675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1879134675
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.2302146754
Short name	T859
Test name
Test status
Simulation time	266741267 ps
CPU time	5.94 seconds
Started	Mar 19 01:22:15 PM PDT 24
Finished	Mar 19 01:22:21 PM PDT 24
Peak memory	203240 kb
Host	smart-617bf61f-2737-4654-a847-2949e18cc063
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302146754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2302146754
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.2170667447
Short name	T730
Test name
Test status
Simulation time	283019323752 ps
CPU time	5802.89 seconds
Started	Mar 19 01:22:25 PM PDT 24
Finished	Mar 19 02:59:10 PM PDT 24
Peak memory	377252 kb
Host	smart-6e4dc5d4-0110-4f96-83dd-89332ffce95e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170667447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.2170667447
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1155138068
Short name	T441
Test name
Test status
Simulation time	2790785210 ps
CPU time	303.85 seconds
Started	Mar 19 01:22:25 PM PDT 24
Finished	Mar 19 01:27:30 PM PDT 24
Peak memory	356168 kb
Host	smart-f336394f-74ac-46b1-8dc4-3619b1063045
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1155138068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1155138068
Directory	/workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1002185189
Short name	T426
Test name
Test status
Simulation time	3050835834 ps
CPU time	147.13 seconds
Started	Mar 19 01:22:17 PM PDT 24
Finished	Mar 19 01:24:44 PM PDT 24
Peak memory	203328 kb
Host	smart-291c9a55-285e-48e6-92bf-f3f6d3eb7c96
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002185189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1002185189
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.485947741
Short name	T316
Test name
Test status
Simulation time	924380857 ps
CPU time	7.18 seconds
Started	Mar 19 01:22:24 PM PDT 24
Finished	Mar 19 01:22:33 PM PDT 24
Peak memory	235960 kb
Host	smart-f91264eb-80e7-4a82-9c82-262b68fadb10
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485947741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_throughput_w_partial_write.485947741
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2440866661
Short name	T722
Test name
Test status
Simulation time	6245149079 ps
CPU time	947.23 seconds
Started	Mar 19 01:22:29 PM PDT 24
Finished	Mar 19 01:38:18 PM PDT 24
Peak memory	370960 kb
Host	smart-2effe118-0648-43ae-96b6-a12ffc373b7c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440866661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2440866661
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.3553860778
Short name	T322
Test name
Test status
Simulation time	19689040 ps
CPU time	0.63 seconds
Started	Mar 19 01:22:37 PM PDT 24
Finished	Mar 19 01:22:40 PM PDT 24
Peak memory	202996 kb
Host	smart-46168a3d-3129-4f4a-9346-c303f394e38f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553860778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3553860778
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_bijection.1561300563
Short name	T481
Test name
Test status
Simulation time	981348137 ps
CPU time	29.32 seconds
Started	Mar 19 01:22:30 PM PDT 24
Finished	Mar 19 01:23:00 PM PDT 24
Peak memory	203172 kb
Host	smart-53ad0889-8a44-4155-98de-69ec7ea4b38a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561300563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .1561300563
Directory	/workspace/15.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.3356499416
Short name	T142
Test name
Test status
Simulation time	1956438415 ps
CPU time	321.94 seconds
Started	Mar 19 01:22:35 PM PDT 24
Finished	Mar 19 01:27:57 PM PDT 24
Peak memory	368240 kb
Host	smart-19bc1e1e-0990-41ac-98c8-25cd974191a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356499416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3356499416
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.2494105919
Short name	T766
Test name
Test status
Simulation time	217110483 ps
CPU time	1.68 seconds
Started	Mar 19 01:22:30 PM PDT 24
Finished	Mar 19 01:22:33 PM PDT 24
Peak memory	203036 kb
Host	smart-ffa26631-aa30-4340-b6fc-565706c5b5b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494105919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2494105919
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.164096167
Short name	T724
Test name
Test status
Simulation time	234449562 ps
CPU time	10.03 seconds
Started	Mar 19 01:22:30 PM PDT 24
Finished	Mar 19 01:22:41 PM PDT 24
Peak memory	241336 kb
Host	smart-24fea685-7efd-4164-9ba0-0af5b99efa76
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164096167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.164096167
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1509464224
Short name	T732
Test name
Test status
Simulation time	496403114 ps
CPU time	4.99 seconds
Started	Mar 19 01:22:35 PM PDT 24
Finished	Mar 19 01:22:40 PM PDT 24
Peak memory	211460 kb
Host	smart-c8194415-8415-4dc3-a81c-7450d3e2e4a3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509464224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.1509464224
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.3982236974
Short name	T914
Test name
Test status
Simulation time	893770900 ps
CPU time	5.49 seconds
Started	Mar 19 01:22:37 PM PDT 24
Finished	Mar 19 01:22:42 PM PDT 24
Peak memory	203236 kb
Host	smart-7e5cbe9e-9a7b-4d07-b1bb-293a8b4220af
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982236974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3982236974
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.2348963560
Short name	T256
Test name
Test status
Simulation time	10884534120 ps
CPU time	1064.08 seconds
Started	Mar 19 01:22:23 PM PDT 24
Finished	Mar 19 01:40:08 PM PDT 24
Peak memory	373020 kb
Host	smart-00e6f4a6-4b55-4ea4-b3a2-504d99852149
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348963560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2348963560
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.2055625390
Short name	T667
Test name
Test status
Simulation time	1190129799 ps
CPU time	18.07 seconds
Started	Mar 19 01:22:28 PM PDT 24
Finished	Mar 19 01:22:49 PM PDT 24
Peak memory	203188 kb
Host	smart-52e9f3d7-bc48-4c13-a8c4-c412f2b1d392
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055625390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.2055625390
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.940128546
Short name	T609
Test name
Test status
Simulation time	5792717973 ps
CPU time	127.21 seconds
Started	Mar 19 01:22:30 PM PDT 24
Finished	Mar 19 01:24:38 PM PDT 24
Peak memory	203316 kb
Host	smart-96bde06c-df4f-4811-8a84-8fadea09a8f6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940128546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.940128546
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.4010126954
Short name	T871
Test name
Test status
Simulation time	146254696 ps
CPU time	0.77 seconds
Started	Mar 19 01:22:28 PM PDT 24
Finished	Mar 19 01:22:32 PM PDT 24
Peak memory	203272 kb
Host	smart-07b75284-f35a-4b23-a360-549929520f7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010126954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4010126954
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.2461243511
Short name	T477
Test name
Test status
Simulation time	5537649860 ps
CPU time	946.6 seconds
Started	Mar 19 01:22:29 PM PDT 24
Finished	Mar 19 01:38:18 PM PDT 24
Peak memory	375100 kb
Host	smart-1fedd367-18c6-4568-87bf-899ce9451133
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461243511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2461243511
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.12297047
Short name	T484
Test name
Test status
Simulation time	99119848 ps
CPU time	0.91 seconds
Started	Mar 19 01:22:24 PM PDT 24
Finished	Mar 19 01:22:25 PM PDT 24
Peak memory	202968 kb
Host	smart-a677f5d4-f0b6-4fce-8df2-8821d65ac397
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.12297047
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.1423388657
Short name	T9
Test name
Test status
Simulation time	192467314957 ps
CPU time	4525.43 seconds
Started	Mar 19 01:22:34 PM PDT 24
Finished	Mar 19 02:38:01 PM PDT 24
Peak memory	377112 kb
Host	smart-ef3c1d7c-0437-4ea5-87b1-49728417b6c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423388657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1423388657
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.934153331
Short name	T476
Test name
Test status
Simulation time	14900523042 ps
CPU time	370.54 seconds
Started	Mar 19 01:22:29 PM PDT 24
Finished	Mar 19 01:28:42 PM PDT 24
Peak memory	203400 kb
Host	smart-98fdac4b-d72a-4c13-8619-ee78d85b4614
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934153331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_stress_pipeline.934153331
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2934271182
Short name	T749
Test name
Test status
Simulation time	271029876 ps
CPU time	154.32 seconds
Started	Mar 19 01:22:29 PM PDT 24
Finished	Mar 19 01:25:05 PM PDT 24
Peak memory	370864 kb
Host	smart-b2b610ab-113c-4cd8-86bd-290e357121e2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934271182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2934271182
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.757030716
Short name	T899
Test name
Test status
Simulation time	1352164005 ps
CPU time	168.98 seconds
Started	Mar 19 01:22:41 PM PDT 24
Finished	Mar 19 01:25:32 PM PDT 24
Peak memory	330348 kb
Host	smart-45630d37-061b-4280-ae0f-39cc7879380c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757030716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.757030716
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.3734313656
Short name	T922
Test name
Test status
Simulation time	46703956 ps
CPU time	0.59 seconds
Started	Mar 19 01:22:49 PM PDT 24
Finished	Mar 19 01:22:50 PM PDT 24
Peak memory	202112 kb
Host	smart-d5dec446-2915-4ea1-8b50-45d82bce6fa6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734313656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3734313656
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.996596627
Short name	T762
Test name
Test status
Simulation time	57699054949 ps
CPU time	85.06 seconds
Started	Mar 19 01:22:43 PM PDT 24
Finished	Mar 19 01:24:09 PM PDT 24
Peak memory	203272 kb
Host	smart-927a201f-ed68-42fd-afcf-ee42ca56f77b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996596627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 996596627
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.4202243908
Short name	T320
Test name
Test status
Simulation time	1354655008 ps
CPU time	668.35 seconds
Started	Mar 19 01:22:42 PM PDT 24
Finished	Mar 19 01:33:52 PM PDT 24
Peak memory	373988 kb
Host	smart-cceb24fb-0aeb-4132-9bbc-04d56b361f9e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202243908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.4202243908
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.1291416952
Short name	T802
Test name
Test status
Simulation time	1116286697 ps
CPU time	3.64 seconds
Started	Mar 19 01:22:45 PM PDT 24
Finished	Mar 19 01:22:51 PM PDT 24
Peak memory	203144 kb
Host	smart-baf698ca-ec8b-4912-907b-065e99eab3ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291416952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.1291416952
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.1816579790
Short name	T789
Test name
Test status
Simulation time	436187846 ps
CPU time	78.34 seconds
Started	Mar 19 01:22:42 PM PDT 24
Finished	Mar 19 01:24:02 PM PDT 24
Peak memory	328764 kb
Host	smart-40716e5d-a4df-4f42-bded-56ed15240b60
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816579790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1816579790
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1770599002
Short name	T344
Test name
Test status
Simulation time	43583829 ps
CPU time	2.6 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:22:52 PM PDT 24
Peak memory	211380 kb
Host	smart-f67b7be9-3320-49a3-a727-4b5ea7cfa5da
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770599002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1770599002
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.2287098728
Short name	T13
Test name
Test status
Simulation time	2735052107 ps
CPU time	10.06 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:22:58 PM PDT 24
Peak memory	203340 kb
Host	smart-ce251c0b-6c66-41fa-ab3f-ea952641162e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287098728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2287098728
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.2336290361
Short name	T275
Test name
Test status
Simulation time	3421836782 ps
CPU time	729.92 seconds
Started	Mar 19 01:22:43 PM PDT 24
Finished	Mar 19 01:34:53 PM PDT 24
Peak memory	358752 kb
Host	smart-e820ca1b-2018-4b13-bcfc-7f4ed063e7ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336290361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.2336290361
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.1024311750
Short name	T874
Test name
Test status
Simulation time	527001172 ps
CPU time	10.26 seconds
Started	Mar 19 01:22:42 PM PDT 24
Finished	Mar 19 01:22:54 PM PDT 24
Peak memory	203272 kb
Host	smart-7d945c12-7aad-46b1-a7f9-b706a4b4dce2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024311750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.1024311750
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2495633406
Short name	T208
Test name
Test status
Simulation time	4451456768 ps
CPU time	298.08 seconds
Started	Mar 19 01:22:42 PM PDT 24
Finished	Mar 19 01:27:42 PM PDT 24
Peak memory	203316 kb
Host	smart-fb25f03d-601c-46eb-a5ff-c0f7372ac895
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495633406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2495633406
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.3300818284
Short name	T213
Test name
Test status
Simulation time	26373233 ps
CPU time	0.77 seconds
Started	Mar 19 01:22:42 PM PDT 24
Finished	Mar 19 01:22:44 PM PDT 24
Peak memory	203316 kb
Host	smart-bc44c75c-524e-45a2-9448-1fb91b1b1407
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300818284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3300818284
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.2247208819
Short name	T235
Test name
Test status
Simulation time	45634417229 ps
CPU time	918.88 seconds
Started	Mar 19 01:22:43 PM PDT 24
Finished	Mar 19 01:38:02 PM PDT 24
Peak memory	371908 kb
Host	smart-e01be1fb-446d-42b2-ba5e-0d2ceb205307
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247208819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2247208819
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.2630374402
Short name	T375
Test name
Test status
Simulation time	104123210 ps
CPU time	1.35 seconds
Started	Mar 19 01:22:35 PM PDT 24
Finished	Mar 19 01:22:37 PM PDT 24
Peak memory	203180 kb
Host	smart-73fa1b33-9619-42d6-b86c-da3d86565405
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630374402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2630374402
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1434391228
Short name	T371
Test name
Test status
Simulation time	16811311482 ps
CPU time	716.49 seconds
Started	Mar 19 01:22:46 PM PDT 24
Finished	Mar 19 01:34:44 PM PDT 24
Peak memory	373260 kb
Host	smart-50594330-bdcd-4e20-99c9-1fb2ffec37b3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1434391228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1434391228
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3190452640
Short name	T925
Test name
Test status
Simulation time	2822703447 ps
CPU time	254.33 seconds
Started	Mar 19 01:22:45 PM PDT 24
Finished	Mar 19 01:27:01 PM PDT 24
Peak memory	203284 kb
Host	smart-411a30a6-4d05-4ad4-8fed-a911c084906c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190452640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3190452640
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2569837038
Short name	T414
Test name
Test status
Simulation time	151371471 ps
CPU time	1.34 seconds
Started	Mar 19 01:22:41 PM PDT 24
Finished	Mar 19 01:22:45 PM PDT 24
Peak memory	211484 kb
Host	smart-9db161a6-64e4-447e-a07f-8ddb36a44b91
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569837038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2569837038
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2606009520
Short name	T761
Test name
Test status
Simulation time	3074201064 ps
CPU time	1081.73 seconds
Started	Mar 19 01:22:47 PM PDT 24
Finished	Mar 19 01:40:50 PM PDT 24
Peak memory	373868 kb
Host	smart-ab4678d8-6cc4-4a32-a5a7-e745dfe380cf
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606009520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2606009520
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.4187556124
Short name	T683
Test name
Test status
Simulation time	15476097 ps
CPU time	0.65 seconds
Started	Mar 19 01:22:56 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	202132 kb
Host	smart-2a8c819a-e42a-4808-8ab6-7f6a9f20e87d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187556124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.4187556124
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.3754274117
Short name	T517
Test name
Test status
Simulation time	2722299188 ps
CPU time	16.6 seconds
Started	Mar 19 01:22:51 PM PDT 24
Finished	Mar 19 01:23:07 PM PDT 24
Peak memory	203104 kb
Host	smart-47f66e5f-36ee-4b83-8114-080e92bbd7f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754274117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3754274117
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.1960056475
Short name	T173
Test name
Test status
Simulation time	3618915117 ps
CPU time	696.62 seconds
Started	Mar 19 01:22:54 PM PDT 24
Finished	Mar 19 01:34:31 PM PDT 24
Peak memory	375096 kb
Host	smart-8511cfa4-f54d-4fe9-9a33-f15460d5f559
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960056475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.1960056475
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.1385771976
Short name	T315
Test name
Test status
Simulation time	2595214667 ps
CPU time	7.44 seconds
Started	Mar 19 01:22:49 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	203312 kb
Host	smart-4a13f741-c44f-45df-ba8d-186c91b14543
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385771976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1385771976
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.3810911324
Short name	T538
Test name
Test status
Simulation time	155816541 ps
CPU time	16.79 seconds
Started	Mar 19 01:22:51 PM PDT 24
Finished	Mar 19 01:23:07 PM PDT 24
Peak memory	263436 kb
Host	smart-fdf50abc-0e2d-4c93-aa04-889565e6703e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810911324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.3810911324
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2267410880
Short name	T898
Test name
Test status
Simulation time	123521216 ps
CPU time	4.52 seconds
Started	Mar 19 01:22:52 PM PDT 24
Finished	Mar 19 01:22:57 PM PDT 24
Peak memory	211448 kb
Host	smart-bdc4eec7-71e6-4355-8a3a-4da60dbea859
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267410880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.2267410880
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.587118357
Short name	T270
Test name
Test status
Simulation time	6216928111 ps
CPU time	10.06 seconds
Started	Mar 19 01:22:56 PM PDT 24
Finished	Mar 19 01:23:06 PM PDT 24
Peak memory	203320 kb
Host	smart-e16e83d5-8f79-4ec7-aca9-9f2abbda9aad
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587118357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.587118357
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.19216483
Short name	T599
Test name
Test status
Simulation time	9608532975 ps
CPU time	736.53 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:35:06 PM PDT 24
Peak memory	374928 kb
Host	smart-230c7eee-2976-4308-8d57-d0b845f69257
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multipl e_keys.19216483
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.1353945529
Short name	T355
Test name
Test status
Simulation time	2150068585 ps
CPU time	19.98 seconds
Started	Mar 19 01:22:49 PM PDT 24
Finished	Mar 19 01:23:10 PM PDT 24
Peak memory	203324 kb
Host	smart-256699e4-5717-493b-b014-1799a3da2e56
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353945529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.1353945529
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.616986007
Short name	T206
Test name
Test status
Simulation time	31637314437 ps
CPU time	374.54 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:29:04 PM PDT 24
Peak memory	203324 kb
Host	smart-c21c7800-9039-4d94-972e-7511352b12ea
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616986007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.sram_ctrl_partial_access_b2b.616986007
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.1368787731
Short name	T400
Test name
Test status
Simulation time	29749185 ps
CPU time	0.77 seconds
Started	Mar 19 01:22:54 PM PDT 24
Finished	Mar 19 01:22:55 PM PDT 24
Peak memory	203320 kb
Host	smart-0bdd9553-2e20-417c-b8b1-8533a95b25a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368787731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1368787731
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.631252634
Short name	T589
Test name
Test status
Simulation time	5905646374 ps
CPU time	450.58 seconds
Started	Mar 19 01:22:53 PM PDT 24
Finished	Mar 19 01:30:24 PM PDT 24
Peak memory	371964 kb
Host	smart-7e253027-95eb-486f-ba2b-19b19d9b73a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631252634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.631252634
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.3053414690
Short name	T814
Test name
Test status
Simulation time	200266115 ps
CPU time	12.05 seconds
Started	Mar 19 01:22:47 PM PDT 24
Finished	Mar 19 01:23:00 PM PDT 24
Peak memory	203172 kb
Host	smart-654cf776-56de-483d-a6f7-64f66e439f3e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053414690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3053414690
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3422257105
Short name	T559
Test name
Test status
Simulation time	5047998964 ps
CPU time	199.06 seconds
Started	Mar 19 01:22:54 PM PDT 24
Finished	Mar 19 01:26:13 PM PDT 24
Peak memory	378212 kb
Host	smart-c46e5fbb-5623-4062-89ee-d9a0cc9fcbac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3422257105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3422257105
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3246112044
Short name	T61
Test name
Test status
Simulation time	7860351856 ps
CPU time	172.37 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:25:42 PM PDT 24
Peak memory	203224 kb
Host	smart-27cb2eac-73de-405c-a9c8-4fc834ba7473
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246112044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3246112044
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3220143895
Short name	T634
Test name
Test status
Simulation time	111349676 ps
CPU time	32.54 seconds
Started	Mar 19 01:22:48 PM PDT 24
Finished	Mar 19 01:23:22 PM PDT 24
Peak memory	301156 kb
Host	smart-fb444e3e-bac7-40da-8921-966bf6c9096d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220143895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3220143895
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.176189540
Short name	T510
Test name
Test status
Simulation time	1340874529 ps
CPU time	362.01 seconds
Started	Mar 19 01:23:07 PM PDT 24
Finished	Mar 19 01:29:09 PM PDT 24
Peak memory	371416 kb
Host	smart-a4fef387-f183-49ef-b16a-f9dae4c5448b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176189540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_access_during_key_req.176189540
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.2262757798
Short name	T384
Test name
Test status
Simulation time	41511054 ps
CPU time	0.66 seconds
Started	Mar 19 01:23:04 PM PDT 24
Finished	Mar 19 01:23:04 PM PDT 24
Peak memory	203056 kb
Host	smart-c796edef-695f-482f-be5a-638d204c06f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262757798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2262757798
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.886899984
Short name	T579
Test name
Test status
Simulation time	1983596451 ps
CPU time	39.2 seconds
Started	Mar 19 01:22:53 PM PDT 24
Finished	Mar 19 01:23:33 PM PDT 24
Peak memory	203148 kb
Host	smart-5db91fdc-1381-4fe3-bfed-b1953dfafbac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886899984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection. 886899984
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.3572241199
Short name	T370
Test name
Test status
Simulation time	41642655950 ps
CPU time	636.32 seconds
Started	Mar 19 01:23:01 PM PDT 24
Finished	Mar 19 01:33:37 PM PDT 24
Peak memory	374800 kb
Host	smart-cf37c79d-1543-4cb2-88ad-9fcb5df66655
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572241199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3572241199
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.3523420909
Short name	T341
Test name
Test status
Simulation time	1370210547 ps
CPU time	7.12 seconds
Started	Mar 19 01:23:02 PM PDT 24
Finished	Mar 19 01:23:10 PM PDT 24
Peak memory	203248 kb
Host	smart-afe139cf-64d9-4d27-b783-106997fc7ecb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523420909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3523420909
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.3128242113
Short name	T233
Test name
Test status
Simulation time	429780973 ps
CPU time	113.55 seconds
Started	Mar 19 01:22:58 PM PDT 24
Finished	Mar 19 01:24:51 PM PDT 24
Peak memory	369816 kb
Host	smart-1f99421a-923e-4947-870d-ca121b5548f8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128242113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3128242113
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.68106452
Short name	T723
Test name
Test status
Simulation time	288805659 ps
CPU time	2.65 seconds
Started	Mar 19 01:23:01 PM PDT 24
Finished	Mar 19 01:23:04 PM PDT 24
Peak memory	211396 kb
Host	smart-833336ff-0ab2-442d-abdf-34169dd65757
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68106452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_mem_partial_access.68106452
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.2985333211
Short name	T43
Test name
Test status
Simulation time	499385456 ps
CPU time	7.99 seconds
Started	Mar 19 01:23:01 PM PDT 24
Finished	Mar 19 01:23:10 PM PDT 24
Peak memory	203220 kb
Host	smart-233fe932-4e8a-44ee-aaaa-d5db1f2bf4c1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985333211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.2985333211
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.3432868838
Short name	T202
Test name
Test status
Simulation time	52948866775 ps
CPU time	1245.88 seconds
Started	Mar 19 01:22:55 PM PDT 24
Finished	Mar 19 01:43:41 PM PDT 24
Peak memory	372568 kb
Host	smart-fe0e55e5-6322-44ea-a4d1-1b27a7bfff8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432868838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.3432868838
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.2380359255
Short name	T230
Test name
Test status
Simulation time	143329111 ps
CPU time	11.4 seconds
Started	Mar 19 01:22:53 PM PDT 24
Finished	Mar 19 01:23:05 PM PDT 24
Peak memory	241168 kb
Host	smart-94c305b2-4056-435c-ba69-60c8ea131998
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380359255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.2380359255
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.297257329
Short name	T305
Test name
Test status
Simulation time	6062889362 ps
CPU time	419.13 seconds
Started	Mar 19 01:23:07 PM PDT 24
Finished	Mar 19 01:30:06 PM PDT 24
Peak memory	203372 kb
Host	smart-de6b2e3b-eef2-47aa-a6e6-32f95d79f0ab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297257329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.sram_ctrl_partial_access_b2b.297257329
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.2831424557
Short name	T40
Test name
Test status
Simulation time	36225050 ps
CPU time	0.83 seconds
Started	Mar 19 01:23:03 PM PDT 24
Finished	Mar 19 01:23:04 PM PDT 24
Peak memory	203284 kb
Host	smart-a65e8502-3852-4969-b7d3-89d210db1be5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831424557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2831424557
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.2506484062
Short name	T665
Test name
Test status
Simulation time	14544515377 ps
CPU time	204.3 seconds
Started	Mar 19 01:23:01 PM PDT 24
Finished	Mar 19 01:26:25 PM PDT 24
Peak memory	352144 kb
Host	smart-a9ad2070-2bab-4d55-9292-68e65926e66f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506484062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2506484062
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.3573996354
Short name	T304
Test name
Test status
Simulation time	863432596 ps
CPU time	91.79 seconds
Started	Mar 19 01:22:54 PM PDT 24
Finished	Mar 19 01:24:26 PM PDT 24
Peak memory	344488 kb
Host	smart-1d3a0181-d122-4c16-b927-7d29b0bca80a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573996354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3573996354
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.1006527049
Short name	T291
Test name
Test status
Simulation time	39985106428 ps
CPU time	87.4 seconds
Started	Mar 19 01:23:01 PM PDT 24
Finished	Mar 19 01:24:28 PM PDT 24
Peak memory	211468 kb
Host	smart-7dcf4927-3682-4be6-a716-4562451c316d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006527049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1006527049
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2621843029
Short name	T929
Test name
Test status
Simulation time	19365255798 ps
CPU time	100.19 seconds
Started	Mar 19 01:23:00 PM PDT 24
Finished	Mar 19 01:24:41 PM PDT 24
Peak memory	274788 kb
Host	smart-a510b318-390c-4d3a-828a-fd1bb5214374
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2621843029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2621843029
Directory	/workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.433227556
Short name	T107
Test name
Test status
Simulation time	3174828610 ps
CPU time	290.2 seconds
Started	Mar 19 01:22:56 PM PDT 24
Finished	Mar 19 01:27:46 PM PDT 24
Peak memory	203344 kb
Host	smart-ace8489f-e224-4d3b-9a92-2c693e369752
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433227556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_stress_pipeline.433227556
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3157270856
Short name	T150
Test name
Test status
Simulation time	86242160 ps
CPU time	2.53 seconds
Started	Mar 19 01:23:00 PM PDT 24
Finished	Mar 19 01:23:03 PM PDT 24
Peak memory	217804 kb
Host	smart-188aae14-1413-4c64-b0ed-1116847c79b7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157270856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3157270856
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.329698921
Short name	T81
Test name
Test status
Simulation time	1739064750 ps
CPU time	781.18 seconds
Started	Mar 19 01:23:08 PM PDT 24
Finished	Mar 19 01:36:09 PM PDT 24
Peak memory	376088 kb
Host	smart-a1c603a5-063c-4d8d-a9bc-b367c9ea6443
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329698921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.329698921
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.1700500004
Short name	T182
Test name
Test status
Simulation time	28147108 ps
CPU time	0.64 seconds
Started	Mar 19 01:23:12 PM PDT 24
Finished	Mar 19 01:23:13 PM PDT 24
Peak memory	203012 kb
Host	smart-cb3bc29e-ce73-4fb8-b106-f5413f80f956
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700500004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1700500004
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.2074601370
Short name	T454
Test name
Test status
Simulation time	4364803353 ps
CPU time	50.94 seconds
Started	Mar 19 01:23:00 PM PDT 24
Finished	Mar 19 01:23:51 PM PDT 24
Peak memory	203252 kb
Host	smart-36e588cd-e73d-415f-93ee-ade597a11a87
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074601370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .2074601370
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_executable.255748198
Short name	T670
Test name
Test status
Simulation time	88602884104 ps
CPU time	1156.25 seconds
Started	Mar 19 01:23:05 PM PDT 24
Finished	Mar 19 01:42:21 PM PDT 24
Peak memory	366204 kb
Host	smart-41c32c34-d141-427b-8f73-8cc43ed383d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255748198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.255748198
Directory	/workspace/19.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.40084543
Short name	T908
Test name
Test status
Simulation time	444872652 ps
CPU time	1.89 seconds
Started	Mar 19 01:23:07 PM PDT 24
Finished	Mar 19 01:23:09 PM PDT 24
Peak memory	203112 kb
Host	smart-bfce59c4-6ab4-4f1e-9735-e6f295a9d502
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40084543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esca lation.40084543
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.815649784
Short name	T522
Test name
Test status
Simulation time	72639305 ps
CPU time	18.34 seconds
Started	Mar 19 01:23:06 PM PDT 24
Finished	Mar 19 01:23:24 PM PDT 24
Peak memory	255732 kb
Host	smart-2b8b80b6-2567-4d68-99ed-da95bfb6ec46
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815649784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_max_throughput.815649784
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3855281167
Short name	T78
Test name
Test status
Simulation time	766998516 ps
CPU time	5.11 seconds
Started	Mar 19 01:23:11 PM PDT 24
Finished	Mar 19 01:23:16 PM PDT 24
Peak memory	211372 kb
Host	smart-fe0acb78-8d66-4ca2-9f09-00a68eb830df
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855281167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.3855281167
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.3032884611
Short name	T180
Test name
Test status
Simulation time	76162824 ps
CPU time	4.41 seconds
Started	Mar 19 01:23:12 PM PDT 24
Finished	Mar 19 01:23:17 PM PDT 24
Peak memory	203276 kb
Host	smart-0c8ddc6f-48b8-44a3-b47f-b64d58f0624f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032884611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3032884611
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.3126344482
Short name	T698
Test name
Test status
Simulation time	15652677833 ps
CPU time	1627.85 seconds
Started	Mar 19 01:23:03 PM PDT 24
Finished	Mar 19 01:50:11 PM PDT 24
Peak memory	375052 kb
Host	smart-1c403b0b-fa75-4442-9e60-55929e34adef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126344482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3126344482
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.1923042270
Short name	T155
Test name
Test status
Simulation time	212893272 ps
CPU time	149.23 seconds
Started	Mar 19 01:23:05 PM PDT 24
Finished	Mar 19 01:25:34 PM PDT 24
Peak memory	367740 kb
Host	smart-06cf18ff-df15-4e2b-ab3e-2d765c437a3c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923042270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1923042270
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.560796490
Short name	T791
Test name
Test status
Simulation time	38971866732 ps
CPU time	222.9 seconds
Started	Mar 19 01:23:04 PM PDT 24
Finished	Mar 19 01:26:47 PM PDT 24
Peak memory	203312 kb
Host	smart-61829548-b50b-4756-afda-35ad7b254edd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560796490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.sram_ctrl_partial_access_b2b.560796490
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.875766663
Short name	T462
Test name
Test status
Simulation time	27071671 ps
CPU time	0.77 seconds
Started	Mar 19 01:23:05 PM PDT 24
Finished	Mar 19 01:23:06 PM PDT 24
Peak memory	203308 kb
Host	smart-bbf4a31f-ad01-449e-b41a-26547f4c2815
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875766663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.875766663
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.4004455792
Short name	T835
Test name
Test status
Simulation time	6894536194 ps
CPU time	1270.91 seconds
Started	Mar 19 01:23:07 PM PDT 24
Finished	Mar 19 01:44:19 PM PDT 24
Peak memory	375028 kb
Host	smart-8f4c6cbe-785f-477b-848c-f545f71ba938
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004455792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4004455792
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.828074045
Short name	T184
Test name
Test status
Simulation time	437929013 ps
CPU time	40.66 seconds
Started	Mar 19 01:23:05 PM PDT 24
Finished	Mar 19 01:23:46 PM PDT 24
Peak memory	301140 kb
Host	smart-4b22e9aa-ed9f-4b73-8fdd-eac7bcd847cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828074045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.828074045
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.2753362474
Short name	T195
Test name
Test status
Simulation time	6734844139 ps
CPU time	134.87 seconds
Started	Mar 19 01:23:12 PM PDT 24
Finished	Mar 19 01:25:27 PM PDT 24
Peak memory	213856 kb
Host	smart-b68e7e36-ca15-4399-b47d-c12bd5665476
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753362474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.2753362474
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2388988116
Short name	T119
Test name
Test status
Simulation time	6332219772 ps
CPU time	89.41 seconds
Started	Mar 19 01:23:12 PM PDT 24
Finished	Mar 19 01:24:42 PM PDT 24
Peak memory	320944 kb
Host	smart-dfd5769c-f288-44f8-b9d7-915b6552a0b6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2388988116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2388988116
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.704716054
Short name	T691
Test name
Test status
Simulation time	22620219220 ps
CPU time	298.94 seconds
Started	Mar 19 01:23:00 PM PDT 24
Finished	Mar 19 01:27:59 PM PDT 24
Peak memory	203332 kb
Host	smart-9d530b2b-695b-4f8b-bff1-6dbc7113b509
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704716054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_stress_pipeline.704716054
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2670819870
Short name	T198
Test name
Test status
Simulation time	475226987 ps
CPU time	76.47 seconds
Started	Mar 19 01:23:06 PM PDT 24
Finished	Mar 19 01:24:23 PM PDT 24
Peak memory	326888 kb
Host	smart-09fa58d3-2069-483c-969d-8cefc44252b9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670819870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2670819870
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2885767452
Short name	T781
Test name
Test status
Simulation time	2683629065 ps
CPU time	694.36 seconds
Started	Mar 19 01:21:17 PM PDT 24
Finished	Mar 19 01:32:51 PM PDT 24
Peak memory	374056 kb
Host	smart-f1ae6c72-ab77-4628-9fe3-580fbfdb1145
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885767452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2885767452
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.1179443999
Short name	T651
Test name
Test status
Simulation time	12221470 ps
CPU time	0.63 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:21:15 PM PDT 24
Peak memory	202144 kb
Host	smart-5b9a19a3-a2cb-4b4d-98d3-f001ac752fee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179443999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1179443999
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.2839582532
Short name	T310
Test name
Test status
Simulation time	666934664 ps
CPU time	41.82 seconds
Started	Mar 19 01:21:15 PM PDT 24
Finished	Mar 19 01:21:57 PM PDT 24
Peak memory	203196 kb
Host	smart-bbe7e673-9432-4126-95af-0df1310bbe44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839582532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2839582532
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.3149322984
Short name	T459
Test name
Test status
Simulation time	6373208284 ps
CPU time	419.23 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:28:22 PM PDT 24
Peak memory	374716 kb
Host	smart-7c0a27d8-ee05-4ebd-89c4-7d5461addfa5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149322984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.3149322984
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.1074708124
Short name	T28
Test name
Test status
Simulation time	427439612 ps
CPU time	5.68 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:21:18 PM PDT 24
Peak memory	203168 kb
Host	smart-81ebd84e-3bd7-49e6-967b-95561f6b8cbe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074708124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.1074708124
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.923000880
Short name	T863
Test name
Test status
Simulation time	97558667 ps
CPU time	34.45 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:21:47 PM PDT 24
Peak memory	295232 kb
Host	smart-f3d092b7-7987-41db-b926-c4999a2c99d1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923000880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.sram_ctrl_max_throughput.923000880
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.4268117656
Short name	T669
Test name
Test status
Simulation time	170227511 ps
CPU time	5.28 seconds
Started	Mar 19 01:21:15 PM PDT 24
Finished	Mar 19 01:21:20 PM PDT 24
Peak memory	211436 kb
Host	smart-937283b2-346a-4d81-a524-0e6f680a7ae2
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268117656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.4268117656
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.3079092375
Short name	T915
Test name
Test status
Simulation time	1757260935 ps
CPU time	8.76 seconds
Started	Mar 19 01:21:17 PM PDT 24
Finished	Mar 19 01:21:26 PM PDT 24
Peak memory	203276 kb
Host	smart-ccfbf2e0-640b-481e-8554-afb2086b5fd9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079092375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3079092375
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.4293570625
Short name	T307
Test name
Test status
Simulation time	4747458643 ps
CPU time	1350.62 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:43:45 PM PDT 24
Peak memory	374080 kb
Host	smart-0d83f003-0b48-4251-8a7e-14bbdefa5a1b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293570625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.4293570625
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.1702459573
Short name	T428
Test name
Test status
Simulation time	1677718172 ps
CPU time	119.22 seconds
Started	Mar 19 01:21:17 PM PDT 24
Finished	Mar 19 01:23:16 PM PDT 24
Peak memory	366516 kb
Host	smart-612e6dc3-a8c1-4e35-b366-2cb9c0eafcaa
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702459573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.1702459573
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3395266267
Short name	T660
Test name
Test status
Simulation time	25786009214 ps
CPU time	166.6 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:24:01 PM PDT 24
Peak memory	203276 kb
Host	smart-d485f6a4-0f64-4752-b156-984e182fd522
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395266267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3395266267
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.2997927406
Short name	T570
Test name
Test status
Simulation time	45827717 ps
CPU time	0.75 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:21:13 PM PDT 24
Peak memory	203212 kb
Host	smart-d129d2e2-4e17-41fb-a26e-70189a8d593a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997927406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2997927406
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.2131315677
Short name	T852
Test name
Test status
Simulation time	5324471891 ps
CPU time	967.34 seconds
Started	Mar 19 01:21:17 PM PDT 24
Finished	Mar 19 01:37:24 PM PDT 24
Peak memory	373980 kb
Host	smart-9a35180d-b5d5-4ae5-88a0-cbc97f8f2417
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131315677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2131315677
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_sec_cm.2980638532
Short name	T34
Test name
Test status
Simulation time	110032119 ps
CPU time	1.77 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:21:16 PM PDT 24
Peak memory	225144 kb
Host	smart-8e4a663d-f2b4-464c-a572-2947964ad357
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980638532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2980638532
Directory	/workspace/2.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.3920967101
Short name	T603
Test name
Test status
Simulation time	92977578 ps
CPU time	15.9 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:39 PM PDT 24
Peak memory	258376 kb
Host	smart-2b853f85-b11d-4d2b-b1fd-e82a3d68c4ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920967101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3920967101
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.2556994763
Short name	T909
Test name
Test status
Simulation time	47789480062 ps
CPU time	3895.21 seconds
Started	Mar 19 01:21:16 PM PDT 24
Finished	Mar 19 02:26:12 PM PDT 24
Peak memory	383756 kb
Host	smart-b8f697a4-ce82-4ebd-849f-4a20908666fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556994763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2556994763
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4056816877
Short name	T681
Test name
Test status
Simulation time	1620526562 ps
CPU time	15.54 seconds
Started	Mar 19 01:21:16 PM PDT 24
Finished	Mar 19 01:21:32 PM PDT 24
Peak memory	211484 kb
Host	smart-14af5cb4-e178-40af-a4ab-fa1f35905a10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4056816877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.4056816877
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.591592883
Short name	T923
Test name
Test status
Simulation time	4460230045 ps
CPU time	214.38 seconds
Started	Mar 19 01:21:16 PM PDT 24
Finished	Mar 19 01:24:50 PM PDT 24
Peak memory	203412 kb
Host	smart-c3b6d626-f625-4dd0-95de-7297ff7c8855
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591592883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_stress_pipeline.591592883
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3958583715
Short name	T703
Test name
Test status
Simulation time	548865020 ps
CPU time	127.41 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:23:21 PM PDT 24
Peak memory	357584 kb
Host	smart-6d4f2944-bae0-4d1b-af9a-0ba2ada185c2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958583715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3958583715
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2799796429
Short name	T323
Test name
Test status
Simulation time	6430299129 ps
CPU time	756.74 seconds
Started	Mar 19 01:23:21 PM PDT 24
Finished	Mar 19 01:35:58 PM PDT 24
Peak memory	367960 kb
Host	smart-fe7939fd-9a6e-4ce9-96da-d54e060950d3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799796429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.2799796429
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.676645287
Short name	T608
Test name
Test status
Simulation time	42126190 ps
CPU time	0.65 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:23:27 PM PDT 24
Peak memory	202176 kb
Host	smart-c58edd0f-4a3c-47dc-b4a1-75ffa743ec80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676645287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.676645287
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.198254444
Short name	T237
Test name
Test status
Simulation time	1969040527 ps
CPU time	41.12 seconds
Started	Mar 19 01:23:11 PM PDT 24
Finished	Mar 19 01:23:52 PM PDT 24
Peak memory	203192 kb
Host	smart-2c6b660f-817e-4a54-ace7-17c7e390ea41
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198254444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 198254444
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_executable.4122805466
Short name	T143
Test name
Test status
Simulation time	8818913871 ps
CPU time	474.55 seconds
Started	Mar 19 01:23:19 PM PDT 24
Finished	Mar 19 01:31:14 PM PDT 24
Peak memory	336768 kb
Host	smart-5555f26a-5490-4e9a-b990-1fa2fb1aa38a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122805466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.4122805466
Directory	/workspace/20.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.1652722113
Short name	T8
Test name
Test status
Simulation time	189019540 ps
CPU time	2.84 seconds
Started	Mar 19 01:23:19 PM PDT 24
Finished	Mar 19 01:23:22 PM PDT 24
Peak memory	203156 kb
Host	smart-adedc3e3-d026-4f5c-8330-e5289558c9cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652722113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.1652722113
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.494400374
Short name	T655
Test name
Test status
Simulation time	71070253 ps
CPU time	12.22 seconds
Started	Mar 19 01:23:19 PM PDT 24
Finished	Mar 19 01:23:31 PM PDT 24
Peak memory	258040 kb
Host	smart-19219fc1-e058-41eb-a862-9d7fab6bfd8b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494400374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.494400374
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1406001188
Short name	T394
Test name
Test status
Simulation time	209578305 ps
CPU time	4.6 seconds
Started	Mar 19 01:23:25 PM PDT 24
Finished	Mar 19 01:23:30 PM PDT 24
Peak memory	211496 kb
Host	smart-0a3f473e-34cc-40f0-97d8-e1c15d8b2445
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406001188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.1406001188
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.2499291926
Short name	T486
Test name
Test status
Simulation time	2994496205 ps
CPU time	5.16 seconds
Started	Mar 19 01:23:21 PM PDT 24
Finished	Mar 19 01:23:26 PM PDT 24
Peak memory	203196 kb
Host	smart-8e890f4f-50a5-4dce-b3a3-d676da378ac6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499291926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2499291926
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.691592811
Short name	T507
Test name
Test status
Simulation time	12108260263 ps
CPU time	896.87 seconds
Started	Mar 19 01:23:13 PM PDT 24
Finished	Mar 19 01:38:11 PM PDT 24
Peak memory	367620 kb
Host	smart-f1c3687b-48aa-4517-ba72-1dbaa064e778
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691592811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.691592811
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.3852237686
Short name	T58
Test name
Test status
Simulation time	875893617 ps
CPU time	124.44 seconds
Started	Mar 19 01:23:22 PM PDT 24
Finished	Mar 19 01:25:26 PM PDT 24
Peak memory	368524 kb
Host	smart-cfca5479-1a67-4155-b1c1-c0b3a808cc28
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852237686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3852237686
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2826233154
Short name	T555
Test name
Test status
Simulation time	14678921418 ps
CPU time	335.27 seconds
Started	Mar 19 01:23:19 PM PDT 24
Finished	Mar 19 01:28:55 PM PDT 24
Peak memory	203304 kb
Host	smart-586ff83c-536b-436d-b830-d475d8bca8b6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826233154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2826233154
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.520397084
Short name	T215
Test name
Test status
Simulation time	96826930 ps
CPU time	0.75 seconds
Started	Mar 19 01:23:21 PM PDT 24
Finished	Mar 19 01:23:22 PM PDT 24
Peak memory	203220 kb
Host	smart-69625e7a-f705-4462-9108-6651808b9a62
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520397084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.520397084
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.3263078338
Short name	T17
Test name
Test status
Simulation time	34466557073 ps
CPU time	601.39 seconds
Started	Mar 19 01:23:21 PM PDT 24
Finished	Mar 19 01:33:22 PM PDT 24
Peak memory	364596 kb
Host	smart-3530660f-71e2-4b91-9a3b-eb751bc6f8b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263078338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3263078338
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.1830141863
Short name	T756
Test name
Test status
Simulation time	65684914 ps
CPU time	11.34 seconds
Started	Mar 19 01:23:10 PM PDT 24
Finished	Mar 19 01:23:22 PM PDT 24
Peak memory	246092 kb
Host	smart-8cb7582b-df16-43f3-b031-089b5475adab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830141863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1830141863
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.3707825995
Short name	T868
Test name
Test status
Simulation time	45437743548 ps
CPU time	4166.75 seconds
Started	Mar 19 01:23:27 PM PDT 24
Finished	Mar 19 02:32:54 PM PDT 24
Peak memory	376996 kb
Host	smart-fe53ab6b-501c-417f-8520-ef92a747df37
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707825995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3707825995
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2314410472
Short name	T532
Test name
Test status
Simulation time	3808760175 ps
CPU time	190.04 seconds
Started	Mar 19 01:23:27 PM PDT 24
Finished	Mar 19 01:26:37 PM PDT 24
Peak memory	349604 kb
Host	smart-e1ea21f7-6d6e-47cc-a454-925d83d21180
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2314410472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2314410472
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2912628593
Short name	T338
Test name
Test status
Simulation time	1698014145 ps
CPU time	151.38 seconds
Started	Mar 19 01:23:12 PM PDT 24
Finished	Mar 19 01:25:44 PM PDT 24
Peak memory	203232 kb
Host	smart-9b3c023e-9b55-480c-a292-fd50dfd24a57
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912628593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2912628593
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4099469054
Short name	T531
Test name
Test status
Simulation time	1133447508 ps
CPU time	47.54 seconds
Started	Mar 19 01:23:20 PM PDT 24
Finished	Mar 19 01:24:07 PM PDT 24
Peak memory	316352 kb
Host	smart-dede9031-cbbd-4e77-9be1-d8f8cc8ddec8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099469054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.4099469054
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1533829059
Short name	T242
Test name
Test status
Simulation time	16310020585 ps
CPU time	787.8 seconds
Started	Mar 19 01:23:32 PM PDT 24
Finished	Mar 19 01:36:40 PM PDT 24
Peak memory	373992 kb
Host	smart-9724a8b8-46f6-4d09-9926-355703c278f5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533829059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.1533829059
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.2307108877
Short name	T853
Test name
Test status
Simulation time	19049067 ps
CPU time	0.68 seconds
Started	Mar 19 01:23:34 PM PDT 24
Finished	Mar 19 01:23:35 PM PDT 24
Peak memory	202948 kb
Host	smart-1821df11-dfeb-4f5f-bc2a-9e3089b8c5d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307108877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2307108877
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.3551676656
Short name	T53
Test name
Test status
Simulation time	34097390614 ps
CPU time	40.56 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:24:07 PM PDT 24
Peak memory	203280 kb
Host	smart-afd20444-71e3-4bc6-bcaf-1682538b6d34
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551676656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3551676656
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.1746377620
Short name	T219
Test name
Test status
Simulation time	8441564331 ps
CPU time	260.97 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:27:54 PM PDT 24
Peak memory	310640 kb
Host	smart-b71bc8dd-a524-48dd-816e-b12382ade2c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746377620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1746377620
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.4133639712
Short name	T228
Test name
Test status
Simulation time	1083638258 ps
CPU time	7.16 seconds
Started	Mar 19 01:23:32 PM PDT 24
Finished	Mar 19 01:23:39 PM PDT 24
Peak memory	203208 kb
Host	smart-0b34282b-eb48-4cb9-b94b-b9857093665f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133639712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.4133639712
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.2134568281
Short name	T149
Test name
Test status
Simulation time	57131757 ps
CPU time	6.65 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:23:33 PM PDT 24
Peak memory	235896 kb
Host	smart-aa032be0-fbf4-4a2b-9c6a-5508a3297a5d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134568281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.2134568281
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2737741355
Short name	T353
Test name
Test status
Simulation time	118406806 ps
CPU time	4.33 seconds
Started	Mar 19 01:23:31 PM PDT 24
Finished	Mar 19 01:23:35 PM PDT 24
Peak memory	211520 kb
Host	smart-6ac0114d-871d-4a72-849e-154d4bff3881
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737741355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.2737741355
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.236746113
Short name	T224
Test name
Test status
Simulation time	2595011064 ps
CPU time	10.21 seconds
Started	Mar 19 01:23:34 PM PDT 24
Finished	Mar 19 01:23:44 PM PDT 24
Peak memory	203292 kb
Host	smart-5748ee38-866c-4dca-93a3-c31484270269
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236746113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.236746113
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.2001734576
Short name	T530
Test name
Test status
Simulation time	7087216161 ps
CPU time	903 seconds
Started	Mar 19 01:23:27 PM PDT 24
Finished	Mar 19 01:38:30 PM PDT 24
Peak memory	369560 kb
Host	smart-05448566-ddca-4675-a7c5-278b8a4e2b85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001734576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2001734576
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.1315292945
Short name	T96
Test name
Test status
Simulation time	176483202 ps
CPU time	8.92 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:23:35 PM PDT 24
Peak memory	203264 kb
Host	smart-d86634e5-376d-49e6-b882-9e7de83a5549
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315292945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1315292945
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2275549207
Short name	T870
Test name
Test status
Simulation time	32547069549 ps
CPU time	378.44 seconds
Started	Mar 19 01:23:27 PM PDT 24
Finished	Mar 19 01:29:45 PM PDT 24
Peak memory	203240 kb
Host	smart-c8dcedd0-f37f-49bd-962e-a9caac8888e8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275549207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2275549207
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3420688906
Short name	T153
Test name
Test status
Simulation time	47820705 ps
CPU time	0.74 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:23:34 PM PDT 24
Peak memory	203220 kb
Host	smart-c99df26e-8d23-4e7c-9ada-b73295de8ac1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420688906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3420688906
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.1028509733
Short name	T335
Test name
Test status
Simulation time	14398282421 ps
CPU time	1022.05 seconds
Started	Mar 19 01:23:31 PM PDT 24
Finished	Mar 19 01:40:34 PM PDT 24
Peak memory	366184 kb
Host	smart-bad34cad-102d-4924-bd37-fcac94cbfebf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028509733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1028509733
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.3316955531
Short name	T145
Test name
Test status
Simulation time	840675940 ps
CPU time	5.1 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:23:31 PM PDT 24
Peak memory	219604 kb
Host	smart-587ff001-997a-4520-88fd-b4247808eb90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316955531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3316955531
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2581024951
Short name	T50
Test name
Test status
Simulation time	6468346583 ps
CPU time	35.11 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:24:08 PM PDT 24
Peak memory	212660 kb
Host	smart-a6cb4c77-2222-4b2e-a88b-52a778b5ec81
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2581024951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2581024951
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.757491653
Short name	T662
Test name
Test status
Simulation time	9090835398 ps
CPU time	216.51 seconds
Started	Mar 19 01:23:26 PM PDT 24
Finished	Mar 19 01:27:03 PM PDT 24
Peak memory	203268 kb
Host	smart-ce360cd0-4ca2-49fc-8df6-30d345405af8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757491653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.757491653
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2457648730
Short name	T178
Test name
Test status
Simulation time	150891249 ps
CPU time	109.78 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:25:22 PM PDT 24
Peak memory	359620 kb
Host	smart-ca840865-86f9-4808-a18f-fdf97f50c4c4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457648730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2457648730
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.675762795
Short name	T688
Test name
Test status
Simulation time	22644710106 ps
CPU time	649.39 seconds
Started	Mar 19 01:23:40 PM PDT 24
Finished	Mar 19 01:34:30 PM PDT 24
Peak memory	363860 kb
Host	smart-f43fa057-1fdb-4fbc-9ac2-9a6110abdc42
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675762795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sram_ctrl_access_during_key_req.675762795
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.3027819709
Short name	T752
Test name
Test status
Simulation time	65871308 ps
CPU time	0.67 seconds
Started	Mar 19 01:23:47 PM PDT 24
Finished	Mar 19 01:23:47 PM PDT 24
Peak memory	202104 kb
Host	smart-db225ae2-832e-4472-a7e8-d9654d639170
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027819709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3027819709
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.3913593849
Short name	T834
Test name
Test status
Simulation time	409735872 ps
CPU time	24.11 seconds
Started	Mar 19 01:23:34 PM PDT 24
Finished	Mar 19 01:23:58 PM PDT 24
Peak memory	203212 kb
Host	smart-4e8205dc-3c22-46d6-b770-2d02e49e595d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913593849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .3913593849
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.815984667
Short name	T272
Test name
Test status
Simulation time	13559053855 ps
CPU time	1356.16 seconds
Started	Mar 19 01:23:38 PM PDT 24
Finished	Mar 19 01:46:15 PM PDT 24
Peak memory	370264 kb
Host	smart-acec687c-e132-4366-9c21-5e73e93f4a5b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815984667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl e.815984667
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.1638342439
Short name	T130
Test name
Test status
Simulation time	783062556 ps
CPU time	8.24 seconds
Started	Mar 19 01:23:39 PM PDT 24
Finished	Mar 19 01:23:48 PM PDT 24
Peak memory	203292 kb
Host	smart-85d82cc1-f15d-4ec7-92bd-849bb8e9ea0f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638342439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1638342439
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.2095948812
Short name	T189
Test name
Test status
Simulation time	97835589 ps
CPU time	26.8 seconds
Started	Mar 19 01:23:39 PM PDT 24
Finished	Mar 19 01:24:06 PM PDT 24
Peak memory	281580 kb
Host	smart-af15e411-c48d-4512-b433-2dafafae8f4d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095948812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2095948812
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3325104412
Short name	T672
Test name
Test status
Simulation time	334870822 ps
CPU time	3.02 seconds
Started	Mar 19 01:23:45 PM PDT 24
Finished	Mar 19 01:23:48 PM PDT 24
Peak memory	211412 kb
Host	smart-8f8911de-3c50-437c-854e-12c286e8dfa9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325104412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3325104412
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.723787235
Short name	T302
Test name
Test status
Simulation time	1356305925 ps
CPU time	10.67 seconds
Started	Mar 19 01:23:44 PM PDT 24
Finished	Mar 19 01:23:55 PM PDT 24
Peak memory	203264 kb
Host	smart-99547727-daac-4950-88f3-9ca11b9fa118
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723787235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _mem_walk.723787235
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.2411716797
Short name	T303
Test name
Test status
Simulation time	62863530933 ps
CPU time	882.53 seconds
Started	Mar 19 01:23:33 PM PDT 24
Finished	Mar 19 01:38:16 PM PDT 24
Peak memory	375080 kb
Host	smart-c1643230-0c2b-404c-bc2f-7e1dc739d38f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411716797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.2411716797
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.1367831688
Short name	T680
Test name
Test status
Simulation time	533587890 ps
CPU time	85.3 seconds
Started	Mar 19 01:23:38 PM PDT 24
Finished	Mar 19 01:25:03 PM PDT 24
Peak memory	338784 kb
Host	smart-325ed5b3-5617-40f3-92d4-b13a51de8141
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367831688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1367831688
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1574088052
Short name	T616
Test name
Test status
Simulation time	6168851719 ps
CPU time	462.07 seconds
Started	Mar 19 01:23:36 PM PDT 24
Finished	Mar 19 01:31:19 PM PDT 24
Peak memory	203324 kb
Host	smart-38ca56b0-56d4-42b4-8b9f-50aacd4cbfcd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574088052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1574088052
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.1533051280
Short name	T393
Test name
Test status
Simulation time	30910109 ps
CPU time	0.76 seconds
Started	Mar 19 01:23:37 PM PDT 24
Finished	Mar 19 01:23:38 PM PDT 24
Peak memory	203268 kb
Host	smart-3b48d280-bfe5-4387-84b9-da3fd8ba5eac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533051280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1533051280
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.3875896263
Short name	T644
Test name
Test status
Simulation time	1240669943 ps
CPU time	593.8 seconds
Started	Mar 19 01:23:36 PM PDT 24
Finished	Mar 19 01:33:30 PM PDT 24
Peak memory	366804 kb
Host	smart-b5659157-9e86-47d1-8814-8c465b7dcffa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875896263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3875896263
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.566916269
Short name	T212
Test name
Test status
Simulation time	79428321 ps
CPU time	4.16 seconds
Started	Mar 19 01:23:32 PM PDT 24
Finished	Mar 19 01:23:36 PM PDT 24
Peak memory	203120 kb
Host	smart-498f2224-f67d-4fb4-a3c5-65cfe2e2c3bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566916269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.566916269
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all.138747770
Short name	T10
Test name
Test status
Simulation time	30221578415 ps
CPU time	2292.32 seconds
Started	Mar 19 01:23:47 PM PDT 24
Finished	Mar 19 02:01:59 PM PDT 24
Peak memory	375692 kb
Host	smart-16222cd3-8f75-4421-8244-88327bedf721
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138747770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.138747770
Directory	/workspace/22.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2325135356
Short name	T41
Test name
Test status
Simulation time	544554946 ps
CPU time	11.67 seconds
Started	Mar 19 01:23:44 PM PDT 24
Finished	Mar 19 01:23:55 PM PDT 24
Peak memory	211544 kb
Host	smart-e1bf3b4c-2bac-4ae2-a60b-522d3196321e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2325135356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2325135356
Directory	/workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.424181838
Short name	T218
Test name
Test status
Simulation time	4708751951 ps
CPU time	161.15 seconds
Started	Mar 19 01:23:38 PM PDT 24
Finished	Mar 19 01:26:19 PM PDT 24
Peak memory	203340 kb
Host	smart-77f0d94b-879c-4cc6-a09b-db8776684de6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424181838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.424181838
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3571827856
Short name	T498
Test name
Test status
Simulation time	793139704 ps
CPU time	38.38 seconds
Started	Mar 19 01:23:38 PM PDT 24
Finished	Mar 19 01:24:16 PM PDT 24
Peak memory	300648 kb
Host	smart-5f73145c-b54b-4126-a21c-2855096947a6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571827856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3571827856
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.4124666733
Short name	T641
Test name
Test status
Simulation time	5393799351 ps
CPU time	1810.82 seconds
Started	Mar 19 01:23:53 PM PDT 24
Finished	Mar 19 01:54:04 PM PDT 24
Peak memory	374128 kb
Host	smart-f0ce246c-afd0-4dd2-acf6-7fcbf3ef350c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124666733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.4124666733
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.1709903667
Short name	T36
Test name
Test status
Simulation time	128899268 ps
CPU time	0.68 seconds
Started	Mar 19 01:23:59 PM PDT 24
Finished	Mar 19 01:24:01 PM PDT 24
Peak memory	202028 kb
Host	smart-11c92483-82cc-40a8-b4e4-a81bef280ad2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709903667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1709903667
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.1618463191
Short name	T157
Test name
Test status
Simulation time	1710489159 ps
CPU time	29.29 seconds
Started	Mar 19 01:23:44 PM PDT 24
Finished	Mar 19 01:24:14 PM PDT 24
Peak memory	203256 kb
Host	smart-521d6448-583a-494c-b4bf-4abf840ee778
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618463191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .1618463191
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.4294392951
Short name	T467
Test name
Test status
Simulation time	4917083345 ps
CPU time	749.26 seconds
Started	Mar 19 01:23:52 PM PDT 24
Finished	Mar 19 01:36:23 PM PDT 24
Peak memory	375100 kb
Host	smart-140b58eb-7ed0-4fdb-99a4-753627339c12
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294392951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.4294392951
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.2734906329
Short name	T274
Test name
Test status
Simulation time	691737364 ps
CPU time	7.23 seconds
Started	Mar 19 01:23:49 PM PDT 24
Finished	Mar 19 01:23:56 PM PDT 24
Peak memory	203276 kb
Host	smart-c7d67e79-8b5a-4dbe-b18c-fa8579f8f21b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734906329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2734906329
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.2128507184
Short name	T685
Test name
Test status
Simulation time	72878687 ps
CPU time	16.23 seconds
Started	Mar 19 01:23:52 PM PDT 24
Finished	Mar 19 01:24:09 PM PDT 24
Peak memory	258824 kb
Host	smart-9f21fe8e-c1c0-41fe-a2ef-44dfee443492
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128507184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2128507184
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2915537959
Short name	T912
Test name
Test status
Simulation time	50255662 ps
CPU time	2.59 seconds
Started	Mar 19 01:23:58 PM PDT 24
Finished	Mar 19 01:24:03 PM PDT 24
Peak memory	211448 kb
Host	smart-d50c955d-100a-45bc-b2d8-4113f774b7f1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915537959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2915537959
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.1933611170
Short name	T383
Test name
Test status
Simulation time	908881511 ps
CPU time	9.85 seconds
Started	Mar 19 01:23:57 PM PDT 24
Finished	Mar 19 01:24:07 PM PDT 24
Peak memory	203220 kb
Host	smart-be4da88e-cc9a-4c06-b9fe-4327956d1f2d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933611170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.1933611170
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.3873967380
Short name	T42
Test name
Test status
Simulation time	2921329637 ps
CPU time	930.47 seconds
Started	Mar 19 01:23:43 PM PDT 24
Finished	Mar 19 01:39:14 PM PDT 24
Peak memory	371712 kb
Host	smart-a74394ba-39f2-4163-a3da-ae1187d1472a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873967380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3873967380
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.2941726018
Short name	T18
Test name
Test status
Simulation time	678341805 ps
CPU time	31.96 seconds
Started	Mar 19 01:23:42 PM PDT 24
Finished	Mar 19 01:24:14 PM PDT 24
Peak memory	280480 kb
Host	smart-23649979-1f4f-401d-8818-dddfd6b416f9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941726018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2941726018
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3301422562
Short name	T247
Test name
Test status
Simulation time	10726679369 ps
CPU time	220.28 seconds
Started	Mar 19 01:23:51 PM PDT 24
Finished	Mar 19 01:27:32 PM PDT 24
Peak memory	203332 kb
Host	smart-cb96b054-0ca4-4b4b-8502-59f7f2922262
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301422562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3301422562
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.1953675581
Short name	T367
Test name
Test status
Simulation time	44489735 ps
CPU time	0.71 seconds
Started	Mar 19 01:23:50 PM PDT 24
Finished	Mar 19 01:23:52 PM PDT 24
Peak memory	203272 kb
Host	smart-3971d3b4-b803-4302-b159-29cad6e104f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953675581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1953675581
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.1367103463
Short name	T701
Test name
Test status
Simulation time	20621235574 ps
CPU time	1630.74 seconds
Started	Mar 19 01:23:51 PM PDT 24
Finished	Mar 19 01:51:02 PM PDT 24
Peak memory	370796 kb
Host	smart-becb44a9-7b42-4cc3-8bbd-442925362150
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367103463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1367103463
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.3445051228
Short name	T753
Test name
Test status
Simulation time	1651016994 ps
CPU time	6.92 seconds
Started	Mar 19 01:23:43 PM PDT 24
Finished	Mar 19 01:23:50 PM PDT 24
Peak memory	228032 kb
Host	smart-94afe509-df04-4b3f-bc20-cff2574cf6be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445051228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3445051228
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.2841797148
Short name	T902
Test name
Test status
Simulation time	17675913526 ps
CPU time	2843.87 seconds
Started	Mar 19 01:23:57 PM PDT 24
Finished	Mar 19 02:11:22 PM PDT 24
Peak memory	382332 kb
Host	smart-e2af66cf-2353-4f42-abc1-1d0708bf05dd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841797148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2841797148
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1263719838
Short name	T163
Test name
Test status
Simulation time	11812488510 ps
CPU time	263.36 seconds
Started	Mar 19 01:23:42 PM PDT 24
Finished	Mar 19 01:28:06 PM PDT 24
Peak memory	203244 kb
Host	smart-30a486f7-682c-4a94-b16c-703c6bfc37a1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263719838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.1263719838
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3394936595
Short name	T324
Test name
Test status
Simulation time	182846738 ps
CPU time	120.11 seconds
Started	Mar 19 01:23:50 PM PDT 24
Finished	Mar 19 01:25:52 PM PDT 24
Peak memory	370880 kb
Host	smart-831dc404-acde-418a-8d60-f4bcbe6f5b49
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394936595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3394936595
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1284952158
Short name	T529
Test name
Test status
Simulation time	4412946072 ps
CPU time	1315.74 seconds
Started	Mar 19 01:23:57 PM PDT 24
Finished	Mar 19 01:45:53 PM PDT 24
Peak memory	375152 kb
Host	smart-cf340fcc-91c5-432b-8b79-d96f07f7e7c8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284952158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.1284952158
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.988892364
Short name	T932
Test name
Test status
Simulation time	14468314 ps
CPU time	0.66 seconds
Started	Mar 19 01:24:10 PM PDT 24
Finished	Mar 19 01:24:10 PM PDT 24
Peak memory	202344 kb
Host	smart-1f475823-5a63-49ae-9aaa-6d68ae09e206
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988892364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.988892364
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.2678162070
Short name	T497
Test name
Test status
Simulation time	3161616232 ps
CPU time	49.24 seconds
Started	Mar 19 01:23:59 PM PDT 24
Finished	Mar 19 01:24:51 PM PDT 24
Peak memory	203272 kb
Host	smart-e6c115cf-7094-4135-b2ba-3ecd5847396e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678162070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .2678162070
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_executable.270999327
Short name	T508
Test name
Test status
Simulation time	4442027335 ps
CPU time	687.2 seconds
Started	Mar 19 01:24:02 PM PDT 24
Finished	Mar 19 01:35:29 PM PDT 24
Peak memory	370468 kb
Host	smart-22ab68f3-3e54-4862-92a2-6df2b2829ad5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270999327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl e.270999327
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.660353436
Short name	T385
Test name
Test status
Simulation time	621576766 ps
CPU time	6.92 seconds
Started	Mar 19 01:23:57 PM PDT 24
Finished	Mar 19 01:24:04 PM PDT 24
Peak memory	203216 kb
Host	smart-e12bb62c-f2e7-41d7-bec6-936e8a3a3ab0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660353436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.660353436
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.3377755469
Short name	T731
Test name
Test status
Simulation time	505980057 ps
CPU time	139.16 seconds
Started	Mar 19 01:23:57 PM PDT 24
Finished	Mar 19 01:26:17 PM PDT 24
Peak memory	363864 kb
Host	smart-af0d27aa-2fdb-4a31-906c-2b6418bc4d3e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377755469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3377755469
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.648905687
Short name	T79
Test name
Test status
Simulation time	42820304 ps
CPU time	2.71 seconds
Started	Mar 19 01:24:03 PM PDT 24
Finished	Mar 19 01:24:06 PM PDT 24
Peak memory	211428 kb
Host	smart-5b95efa5-841f-48c8-abd3-d97f91960580
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648905687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_mem_partial_access.648905687
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.188027427
Short name	T823
Test name
Test status
Simulation time	922775484 ps
CPU time	9.24 seconds
Started	Mar 19 01:24:04 PM PDT 24
Finished	Mar 19 01:24:15 PM PDT 24
Peak memory	203248 kb
Host	smart-a747c4d1-a37e-433f-9cd7-d6ddbba670a3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188027427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _mem_walk.188027427
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.1534777836
Short name	T196
Test name
Test status
Simulation time	5161345136 ps
CPU time	558.64 seconds
Started	Mar 19 01:23:58 PM PDT 24
Finished	Mar 19 01:33:19 PM PDT 24
Peak memory	351780 kb
Host	smart-bb5ad1ae-a6e1-4a61-b714-5c5b09a13434
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534777836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1534777836
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.3334187869
Short name	T851
Test name
Test status
Simulation time	215310111 ps
CPU time	11.52 seconds
Started	Mar 19 01:24:01 PM PDT 24
Finished	Mar 19 01:24:13 PM PDT 24
Peak memory	203276 kb
Host	smart-5ee7f0a2-faed-4bc6-a50d-bf45eb0a69e7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334187869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.3334187869
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.1376710940
Short name	T32
Test name
Test status
Simulation time	30139862 ps
CPU time	0.78 seconds
Started	Mar 19 01:24:06 PM PDT 24
Finished	Mar 19 01:24:07 PM PDT 24
Peak memory	203260 kb
Host	smart-b39c17f6-36b0-43e8-aa79-eba39f42e299
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376710940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1376710940
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.1284969612
Short name	T649
Test name
Test status
Simulation time	10087940044 ps
CPU time	407.93 seconds
Started	Mar 19 01:23:59 PM PDT 24
Finished	Mar 19 01:30:50 PM PDT 24
Peak memory	362244 kb
Host	smart-b5fa5f31-a34f-4f6d-b55b-14f53a2f8e44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284969612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1284969612
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.2620362476
Short name	T337
Test name
Test status
Simulation time	837824681 ps
CPU time	61.32 seconds
Started	Mar 19 01:23:59 PM PDT 24
Finished	Mar 19 01:25:02 PM PDT 24
Peak memory	314912 kb
Host	smart-40ae2e42-2e5f-45a6-95f0-fe3a5ee1b211
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620362476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2620362476
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.490131708
Short name	T129
Test name
Test status
Simulation time	521692521454 ps
CPU time	3899.86 seconds
Started	Mar 19 01:24:05 PM PDT 24
Finished	Mar 19 02:29:06 PM PDT 24
Peak memory	383308 kb
Host	smart-547570cb-fbb6-4b5b-9313-5c3cfba8b96c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490131708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.490131708
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3496253029
Short name	T293
Test name
Test status
Simulation time	1803390798 ps
CPU time	57.9 seconds
Started	Mar 19 01:24:04 PM PDT 24
Finished	Mar 19 01:25:03 PM PDT 24
Peak memory	303932 kb
Host	smart-6d988f15-9ad8-4d27-957d-9f6f18ee8341
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3496253029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3496253029
Directory	/workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1483424825
Short name	T792
Test name
Test status
Simulation time	1685717058 ps
CPU time	149.97 seconds
Started	Mar 19 01:23:58 PM PDT 24
Finished	Mar 19 01:26:30 PM PDT 24
Peak memory	203212 kb
Host	smart-b6a433e1-6787-48eb-b65e-a58effceaa59
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483424825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1483424825
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1941428789
Short name	T838
Test name
Test status
Simulation time	131118516 ps
CPU time	48.2 seconds
Started	Mar 19 01:23:58 PM PDT 24
Finished	Mar 19 01:24:46 PM PDT 24
Peak memory	296264 kb
Host	smart-492cb606-97ff-4b54-9604-159a9fcff6fb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941428789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1941428789
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4284065605
Short name	T181
Test name
Test status
Simulation time	7108825633 ps
CPU time	867.23 seconds
Started	Mar 19 01:24:12 PM PDT 24
Finished	Mar 19 01:38:39 PM PDT 24
Peak memory	352544 kb
Host	smart-ca8b5e11-4612-420a-b616-ba2917d810c8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284065605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.4284065605
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.710055453
Short name	T236
Test name
Test status
Simulation time	26228801 ps
CPU time	0.63 seconds
Started	Mar 19 01:24:16 PM PDT 24
Finished	Mar 19 01:24:17 PM PDT 24
Peak memory	202168 kb
Host	smart-b80a696d-9b30-4064-b186-f4a53041b6c4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710055453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.710055453
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.2561095456
Short name	T6
Test name
Test status
Simulation time	5690035645 ps
CPU time	40.73 seconds
Started	Mar 19 01:24:12 PM PDT 24
Finished	Mar 19 01:24:53 PM PDT 24
Peak memory	203248 kb
Host	smart-1a3ac11f-3961-43fd-9e24-c4c0728d40c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561095456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2561095456
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.1409757803
Short name	T719
Test name
Test status
Simulation time	56526231886 ps
CPU time	729.23 seconds
Started	Mar 19 01:24:11 PM PDT 24
Finished	Mar 19 01:36:21 PM PDT 24
Peak memory	376272 kb
Host	smart-522e9afa-6579-4e26-a31f-eac219faed4d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409757803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1409757803
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.632554374
Short name	T574
Test name
Test status
Simulation time	184014338 ps
CPU time	2.58 seconds
Started	Mar 19 01:24:10 PM PDT 24
Finished	Mar 19 01:24:13 PM PDT 24
Peak memory	203172 kb
Host	smart-4f07d443-04c7-4923-94b2-c51013f45d93
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632554374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc alation.632554374
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.4247735957
Short name	T190
Test name
Test status
Simulation time	214778552 ps
CPU time	73.9 seconds
Started	Mar 19 01:24:11 PM PDT 24
Finished	Mar 19 01:25:25 PM PDT 24
Peak memory	322876 kb
Host	smart-d270bfc9-ee56-468d-aef3-7c3b9e4fba0c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247735957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.4247735957
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1253666817
Short name	T255
Test name
Test status
Simulation time	122609895 ps
CPU time	4.29 seconds
Started	Mar 19 01:24:17 PM PDT 24
Finished	Mar 19 01:24:22 PM PDT 24
Peak memory	211472 kb
Host	smart-95f12964-0415-455e-b37f-c0fcb632d7bc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253666817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.1253666817
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.4038183006
Short name	T209
Test name
Test status
Simulation time	630788456 ps
CPU time	8.19 seconds
Started	Mar 19 01:24:16 PM PDT 24
Finished	Mar 19 01:24:24 PM PDT 24
Peak memory	203172 kb
Host	smart-12f709ed-935f-4282-bc23-044c9082afe3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038183006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.4038183006
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.1206709806
Short name	T707
Test name
Test status
Simulation time	31319776269 ps
CPU time	864.24 seconds
Started	Mar 19 01:24:11 PM PDT 24
Finished	Mar 19 01:38:35 PM PDT 24
Peak memory	371084 kb
Host	smart-e09a6fc1-ae53-4c34-ba7e-7d08875dc156
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206709806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1206709806
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.1983898164
Short name	T709
Test name
Test status
Simulation time	1373615501 ps
CPU time	54.82 seconds
Started	Mar 19 01:24:13 PM PDT 24
Finished	Mar 19 01:25:08 PM PDT 24
Peak memory	309256 kb
Host	smart-c86a4925-45d2-4811-8f1b-150c7bf57c54
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983898164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.1983898164
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2803172769
Short name	T848
Test name
Test status
Simulation time	26153215843 ps
CPU time	302.34 seconds
Started	Mar 19 01:24:12 PM PDT 24
Finished	Mar 19 01:29:15 PM PDT 24
Peak memory	203236 kb
Host	smart-91d7c250-528e-480f-ad8e-24b6ac353940
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803172769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.2803172769
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.815115443
Short name	T415
Test name
Test status
Simulation time	471913237 ps
CPU time	0.8 seconds
Started	Mar 19 01:24:13 PM PDT 24
Finished	Mar 19 01:24:14 PM PDT 24
Peak memory	203148 kb
Host	smart-8854e5c2-a30e-4fc4-971e-4b851954bf93
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815115443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.815115443
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.3163774514
Short name	T773
Test name
Test status
Simulation time	3840104081 ps
CPU time	635 seconds
Started	Mar 19 01:24:09 PM PDT 24
Finished	Mar 19 01:34:45 PM PDT 24
Peak memory	358504 kb
Host	smart-25ac2c54-3ade-4487-9c46-6789cf0ba333
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163774514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3163774514
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.1703037253
Short name	T176
Test name
Test status
Simulation time	1426055133 ps
CPU time	40.65 seconds
Started	Mar 19 01:24:12 PM PDT 24
Finished	Mar 19 01:24:53 PM PDT 24
Peak memory	286420 kb
Host	smart-1f4fe704-b875-4d03-9b05-be4701170b68
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703037253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1703037253
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.794331974
Short name	T889
Test name
Test status
Simulation time	69038788340 ps
CPU time	3338.2 seconds
Started	Mar 19 01:24:16 PM PDT 24
Finished	Mar 19 02:19:55 PM PDT 24
Peak memory	383204 kb
Host	smart-b83f5a68-f9f0-4eef-9c2b-82fc9a274e64
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794331974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_stress_all.794331974
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2179886388
Short name	T804
Test name
Test status
Simulation time	406541629 ps
CPU time	41.66 seconds
Started	Mar 19 01:24:16 PM PDT 24
Finished	Mar 19 01:24:58 PM PDT 24
Peak memory	302292 kb
Host	smart-e164e054-3591-4703-a394-9374cc9f9d08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2179886388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2179886388
Directory	/workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1538288783
Short name	T295
Test name
Test status
Simulation time	1767863771 ps
CPU time	163.66 seconds
Started	Mar 19 01:24:10 PM PDT 24
Finished	Mar 19 01:26:54 PM PDT 24
Peak memory	203316 kb
Host	smart-448bc463-fa8d-4ba7-8b29-5f3ebc46f530
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538288783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.1538288783
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3125489958
Short name	T396
Test name
Test status
Simulation time	861529897 ps
CPU time	161.12 seconds
Started	Mar 19 01:24:12 PM PDT 24
Finished	Mar 19 01:26:53 PM PDT 24
Peak memory	370728 kb
Host	smart-da70587e-e828-4c0d-a883-ceaf882a5b12
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125489958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3125489958
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1011844055
Short name	T357
Test name
Test status
Simulation time	1893160756 ps
CPU time	543.94 seconds
Started	Mar 19 01:24:21 PM PDT 24
Finished	Mar 19 01:33:27 PM PDT 24
Peak memory	354964 kb
Host	smart-b7adbb69-ea48-4a56-82e3-322c30bc96a9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011844055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.1011844055
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.711908311
Short name	T576
Test name
Test status
Simulation time	33549327 ps
CPU time	0.65 seconds
Started	Mar 19 01:24:28 PM PDT 24
Finished	Mar 19 01:24:29 PM PDT 24
Peak memory	202112 kb
Host	smart-da8e2839-3e6d-4e94-8237-1492dd9617df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711908311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.711908311
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.736858227
Short name	T126
Test name
Test status
Simulation time	3541169681 ps
CPU time	63.26 seconds
Started	Mar 19 01:24:17 PM PDT 24
Finished	Mar 19 01:25:20 PM PDT 24
Peak memory	203168 kb
Host	smart-adf6bd8a-4da8-4b28-a2e6-1ba0593c936e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736858227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 736858227
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.3743085251
Short name	T217
Test name
Test status
Simulation time	8577279889 ps
CPU time	821.64 seconds
Started	Mar 19 01:24:20 PM PDT 24
Finished	Mar 19 01:38:05 PM PDT 24
Peak memory	371028 kb
Host	smart-fd4d33cf-e57f-434e-8bd8-8b3de41bb5f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743085251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.3743085251
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1648845769
Short name	T818
Test name
Test status
Simulation time	2058943280 ps
CPU time	5.3 seconds
Started	Mar 19 01:24:20 PM PDT 24
Finished	Mar 19 01:24:29 PM PDT 24
Peak memory	203144 kb
Host	smart-5104dbec-bfa9-4f12-aae0-e09693299dd5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648845769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1648845769
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.2672750963
Short name	T646
Test name
Test status
Simulation time	1214190387 ps
CPU time	97.44 seconds
Started	Mar 19 01:24:21 PM PDT 24
Finished	Mar 19 01:26:01 PM PDT 24
Peak memory	360340 kb
Host	smart-364f5d96-d6f9-4dcb-a329-7552c30a01b8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672750963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2672750963
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1458290030
Short name	T606
Test name
Test status
Simulation time	67330981 ps
CPU time	4.46 seconds
Started	Mar 19 01:24:29 PM PDT 24
Finished	Mar 19 01:24:33 PM PDT 24
Peak memory	211388 kb
Host	smart-9aee08a3-7571-40ae-905e-c7ec0287a19a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458290030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1458290030
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.4052432704
Short name	T571
Test name
Test status
Simulation time	472242033 ps
CPU time	9.44 seconds
Started	Mar 19 01:24:29 PM PDT 24
Finished	Mar 19 01:24:38 PM PDT 24
Peak memory	203268 kb
Host	smart-b0092a99-485b-46a8-87bb-1066f8d1a632
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052432704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.4052432704
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.2360043021
Short name	T148
Test name
Test status
Simulation time	9963360113 ps
CPU time	1237.38 seconds
Started	Mar 19 01:24:17 PM PDT 24
Finished	Mar 19 01:44:54 PM PDT 24
Peak memory	376092 kb
Host	smart-fa97f8d2-7c6c-4ae9-963d-4839cca51b52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360043021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.2360043021
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.2902113873
Short name	T447
Test name
Test status
Simulation time	88805289 ps
CPU time	0.85 seconds
Started	Mar 19 01:24:20 PM PDT 24
Finished	Mar 19 01:24:24 PM PDT 24
Peak memory	203020 kb
Host	smart-9c7b7d91-213c-4127-876e-ee035b7d7822
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902113873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2902113873
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3139682440
Short name	T363
Test name
Test status
Simulation time	38632299503 ps
CPU time	422.62 seconds
Started	Mar 19 01:24:21 PM PDT 24
Finished	Mar 19 01:31:26 PM PDT 24
Peak memory	203316 kb
Host	smart-e9ca571a-185e-462f-a564-e5516f828a24
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139682440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3139682440
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.3315868915
Short name	T431
Test name
Test status
Simulation time	28799413 ps
CPU time	0.76 seconds
Started	Mar 19 01:24:30 PM PDT 24
Finished	Mar 19 01:24:31 PM PDT 24
Peak memory	203296 kb
Host	smart-0da3f015-7730-4568-848c-ac645cd7a231
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315868915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3315868915
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.3198129796
Short name	T381
Test name
Test status
Simulation time	18532553235 ps
CPU time	1358.92 seconds
Started	Mar 19 01:24:29 PM PDT 24
Finished	Mar 19 01:47:08 PM PDT 24
Peak memory	371964 kb
Host	smart-de9b8aa5-2f7c-4354-8d0d-1911f14a3cf1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198129796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3198129796
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.4006342059
Short name	T861
Test name
Test status
Simulation time	254518751 ps
CPU time	14.2 seconds
Started	Mar 19 01:24:19 PM PDT 24
Finished	Mar 19 01:24:38 PM PDT 24
Peak memory	203200 kb
Host	smart-d332bc24-7b56-44e8-ae8d-a1eaf742b318
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006342059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4006342059
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.1302646155
Short name	T569
Test name
Test status
Simulation time	75629590632 ps
CPU time	821.97 seconds
Started	Mar 19 01:24:28 PM PDT 24
Finished	Mar 19 01:38:10 PM PDT 24
Peak memory	367620 kb
Host	smart-eca43371-1df6-4ff8-af14-c6c566662a12
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302646155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1302646155
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.994628876
Short name	T553
Test name
Test status
Simulation time	2011010246 ps
CPU time	44.11 seconds
Started	Mar 19 01:24:28 PM PDT 24
Finished	Mar 19 01:25:12 PM PDT 24
Peak memory	291200 kb
Host	smart-bb15cb32-2843-4e05-9f4c-6d12ab73ac73
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=994628876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.994628876
Directory	/workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.490119626
Short name	T342
Test name
Test status
Simulation time	9190720906 ps
CPU time	310.33 seconds
Started	Mar 19 01:24:21 PM PDT 24
Finished	Mar 19 01:29:34 PM PDT 24
Peak memory	203332 kb
Host	smart-1771db14-957b-421d-89cb-92564fbb90fe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490119626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.490119626
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3498152644
Short name	T544
Test name
Test status
Simulation time	426356178 ps
CPU time	48.55 seconds
Started	Mar 19 01:24:21 PM PDT 24
Finished	Mar 19 01:25:12 PM PDT 24
Peak memory	310596 kb
Host	smart-7d7c102b-e1c3-402b-bef4-6862d49a3dc4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498152644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3498152644
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.465033624
Short name	T540
Test name
Test status
Simulation time	2314470272 ps
CPU time	901.49 seconds
Started	Mar 19 01:24:37 PM PDT 24
Finished	Mar 19 01:39:39 PM PDT 24
Peak memory	374092 kb
Host	smart-4760573a-1410-4f90-8a77-e342e407b486
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465033624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 27.sram_ctrl_access_during_key_req.465033624
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.4098884656
Short name	T251
Test name
Test status
Simulation time	12035910 ps
CPU time	0.63 seconds
Started	Mar 19 01:24:44 PM PDT 24
Finished	Mar 19 01:24:45 PM PDT 24
Peak memory	202356 kb
Host	smart-eb0039c1-b7dc-44d2-8130-7fc0924a0523
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098884656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.4098884656
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.303773138
Short name	T321
Test name
Test status
Simulation time	1471536388 ps
CPU time	31.73 seconds
Started	Mar 19 01:24:37 PM PDT 24
Finished	Mar 19 01:25:09 PM PDT 24
Peak memory	203140 kb
Host	smart-a9868e6c-3dfd-4503-8b43-170bc5f0e477
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303773138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 303773138
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.3999201895
Short name	T826
Test name
Test status
Simulation time	3010800341 ps
CPU time	887.62 seconds
Started	Mar 19 01:24:38 PM PDT 24
Finished	Mar 19 01:39:26 PM PDT 24
Peak memory	374068 kb
Host	smart-f383182f-0015-44c8-872a-ebf52de3ba14
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999201895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.3999201895
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.2431281240
Short name	T648
Test name
Test status
Simulation time	1188727075 ps
CPU time	4.89 seconds
Started	Mar 19 01:24:38 PM PDT 24
Finished	Mar 19 01:24:43 PM PDT 24
Peak memory	203208 kb
Host	smart-99a9e5ac-56c2-40f3-ab37-3244c15ec630
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431281240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.2431281240
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.889703342
Short name	T928
Test name
Test status
Simulation time	227617915 ps
CPU time	100.16 seconds
Started	Mar 19 01:24:35 PM PDT 24
Finished	Mar 19 01:26:15 PM PDT 24
Peak memory	341096 kb
Host	smart-01aa6a66-cd36-44e5-87af-8665c01ad953
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889703342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.889703342
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1902596152
Short name	T840
Test name
Test status
Simulation time	67180764 ps
CPU time	4.24 seconds
Started	Mar 19 01:24:38 PM PDT 24
Finished	Mar 19 01:24:43 PM PDT 24
Peak memory	211456 kb
Host	smart-1376ccf3-e912-4d85-957b-c705254b94da
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902596152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.1902596152
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.1268867863
Short name	T787
Test name
Test status
Simulation time	146305092 ps
CPU time	8.06 seconds
Started	Mar 19 01:24:40 PM PDT 24
Finished	Mar 19 01:24:49 PM PDT 24
Peak memory	203244 kb
Host	smart-48308b29-3a77-434e-a29b-d5ee4e7f0ea7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268867863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.1268867863
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.4014395495
Short name	T231
Test name
Test status
Simulation time	14176055014 ps
CPU time	2234.94 seconds
Started	Mar 19 01:24:37 PM PDT 24
Finished	Mar 19 02:01:52 PM PDT 24
Peak memory	376108 kb
Host	smart-034a013c-389f-4e06-a8ab-80023534b6ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014395495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.4014395495
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.2636408444
Short name	T794
Test name
Test status
Simulation time	223597673 ps
CPU time	16.44 seconds
Started	Mar 19 01:24:34 PM PDT 24
Finished	Mar 19 01:24:51 PM PDT 24
Peak memory	250424 kb
Host	smart-a0df5e89-eddf-4110-972c-fc6001ffef64
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636408444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.2636408444
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2684540759
Short name	T805
Test name
Test status
Simulation time	18275131257 ps
CPU time	459.21 seconds
Started	Mar 19 01:24:37 PM PDT 24
Finished	Mar 19 01:32:16 PM PDT 24
Peak memory	203304 kb
Host	smart-9c1c2497-308e-4195-8431-0b6aeef471ef
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684540759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2684540759
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.164637956
Short name	T520
Test name
Test status
Simulation time	78234353 ps
CPU time	0.73 seconds
Started	Mar 19 01:24:40 PM PDT 24
Finished	Mar 19 01:24:40 PM PDT 24
Peak memory	203252 kb
Host	smart-9c1cec3d-3e77-4de4-9394-2deacf53291a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164637956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.164637956
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.1847518011
Short name	T747
Test name
Test status
Simulation time	5623031163 ps
CPU time	356.3 seconds
Started	Mar 19 01:24:38 PM PDT 24
Finished	Mar 19 01:30:34 PM PDT 24
Peak memory	352784 kb
Host	smart-fd4dba31-88e7-4425-808a-fc9c5c79001d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847518011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1847518011
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.897880587
Short name	T351
Test name
Test status
Simulation time	2417594544 ps
CPU time	98.33 seconds
Started	Mar 19 01:24:27 PM PDT 24
Finished	Mar 19 01:26:06 PM PDT 24
Peak memory	343292 kb
Host	smart-739734d5-d065-4c52-831a-7e3cee763dd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897880587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.897880587
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all.1827132378
Short name	T472
Test name
Test status
Simulation time	12296094120 ps
CPU time	2395.99 seconds
Started	Mar 19 01:24:45 PM PDT 24
Finished	Mar 19 02:04:41 PM PDT 24
Peak memory	383044 kb
Host	smart-eb3c70a5-7cef-487f-9edf-7ffc23cc3be3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827132378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.1827132378
Directory	/workspace/27.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1252541731
Short name	T390
Test name
Test status
Simulation time	11827700333 ps
CPU time	198.98 seconds
Started	Mar 19 01:24:33 PM PDT 24
Finished	Mar 19 01:27:54 PM PDT 24
Peak memory	203340 kb
Host	smart-3e93509b-ae4b-4ef9-aac9-f475e1611dbd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252541731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1252541731
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1079161092
Short name	T306
Test name
Test status
Simulation time	547499101 ps
CPU time	112.23 seconds
Started	Mar 19 01:24:33 PM PDT 24
Finished	Mar 19 01:26:27 PM PDT 24
Peak memory	349576 kb
Host	smart-4346176b-66e8-46f6-8132-197e452c09e0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079161092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1079161092
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3514564480
Short name	T631
Test name
Test status
Simulation time	4721476471 ps
CPU time	1073.86 seconds
Started	Mar 19 01:24:50 PM PDT 24
Finished	Mar 19 01:42:47 PM PDT 24
Peak memory	350660 kb
Host	smart-48a34d40-bc87-44fe-8851-4b9d1ac36331
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514564480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.3514564480
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.3531221167
Short name	T714
Test name
Test status
Simulation time	19715172 ps
CPU time	0.66 seconds
Started	Mar 19 01:24:55 PM PDT 24
Finished	Mar 19 01:24:56 PM PDT 24
Peak memory	202336 kb
Host	smart-f9aa9574-0ff5-4f9c-b8a6-5e21df739a02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531221167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3531221167
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_bijection.2892287056
Short name	T527
Test name
Test status
Simulation time	576756538 ps
CPU time	35.55 seconds
Started	Mar 19 01:24:47 PM PDT 24
Finished	Mar 19 01:25:22 PM PDT 24
Peak memory	203172 kb
Host	smart-b31ddda1-b8a4-4f47-ab31-a2559b76c37f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892287056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2892287056
Directory	/workspace/28.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.1458780574
Short name	T782
Test name
Test status
Simulation time	41594211145 ps
CPU time	1509.32 seconds
Started	Mar 19 01:24:50 PM PDT 24
Finished	Mar 19 01:50:03 PM PDT 24
Peak memory	374128 kb
Host	smart-c6e13a89-7a52-4bbd-8e01-aa5b79e50dcb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458780574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1458780574
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.905810328
Short name	T622
Test name
Test status
Simulation time	91277693 ps
CPU time	2.27 seconds
Started	Mar 19 01:24:51 PM PDT 24
Finished	Mar 19 01:24:55 PM PDT 24
Peak memory	203200 kb
Host	smart-b5bd3c6f-3861-499b-adea-9fcd7579f36c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905810328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.905810328
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.3732434654
Short name	T597
Test name
Test status
Simulation time	2623784223 ps
CPU time	120.39 seconds
Started	Mar 19 01:24:46 PM PDT 24
Finished	Mar 19 01:26:46 PM PDT 24
Peak memory	364640 kb
Host	smart-d8eccb38-736a-4e57-a35c-424048888456
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732434654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3732434654
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3139383965
Short name	T177
Test name
Test status
Simulation time	126176116 ps
CPU time	4.38 seconds
Started	Mar 19 01:24:51 PM PDT 24
Finished	Mar 19 01:24:58 PM PDT 24
Peak memory	211560 kb
Host	smart-b7cb35ab-6b3e-41f3-98f5-31ffc67fdc06
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139383965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3139383965
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.1679018708
Short name	T187
Test name
Test status
Simulation time	2565238594 ps
CPU time	10.27 seconds
Started	Mar 19 01:24:51 PM PDT 24
Finished	Mar 19 01:25:04 PM PDT 24
Peak memory	202912 kb
Host	smart-fa7908ba-e008-4d00-bb6e-d749a7b6c106
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679018708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.1679018708
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.1404465460
Short name	T285
Test name
Test status
Simulation time	7056629628 ps
CPU time	1023.04 seconds
Started	Mar 19 01:24:44 PM PDT 24
Finished	Mar 19 01:41:48 PM PDT 24
Peak memory	373900 kb
Host	smart-2ed18eff-08a6-45d9-980d-a42ad260ca9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404465460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1404465460
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.2276943680
Short name	T259
Test name
Test status
Simulation time	3416648930 ps
CPU time	14.76 seconds
Started	Mar 19 01:24:45 PM PDT 24
Finished	Mar 19 01:25:00 PM PDT 24
Peak memory	203332 kb
Host	smart-37c33764-d6ed-4387-b839-1f2174f6ab64
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276943680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.2276943680
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2275742039
Short name	T638
Test name
Test status
Simulation time	12765685313 ps
CPU time	219.72 seconds
Started	Mar 19 01:24:44 PM PDT 24
Finished	Mar 19 01:28:23 PM PDT 24
Peak memory	203408 kb
Host	smart-114c3fdd-1ccf-487f-9ad6-da1d0fdc7d16
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275742039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.2275742039
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.3586407014
Short name	T663
Test name
Test status
Simulation time	103641965 ps
CPU time	0.74 seconds
Started	Mar 19 01:24:50 PM PDT 24
Finished	Mar 19 01:24:54 PM PDT 24
Peak memory	203336 kb
Host	smart-0cedbb22-f2a2-430f-a624-f87a3c5baf2e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586407014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3586407014
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.2993658577
Short name	T733
Test name
Test status
Simulation time	9048599186 ps
CPU time	1562.19 seconds
Started	Mar 19 01:24:52 PM PDT 24
Finished	Mar 19 01:50:56 PM PDT 24
Peak memory	373632 kb
Host	smart-d9667eff-0a11-4b9e-bf7b-8fb81a3b539b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993658577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2993658577
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.3547039767
Short name	T151
Test name
Test status
Simulation time	1804114736 ps
CPU time	14.37 seconds
Started	Mar 19 01:24:45 PM PDT 24
Finished	Mar 19 01:25:00 PM PDT 24
Peak memory	203180 kb
Host	smart-18ab3d5f-2050-4b7d-aeb2-b136728b0359
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547039767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3547039767
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.3383535864
Short name	T919
Test name
Test status
Simulation time	59466292836 ps
CPU time	5504.69 seconds
Started	Mar 19 01:24:51 PM PDT 24
Finished	Mar 19 02:56:38 PM PDT 24
Peak memory	383276 kb
Host	smart-029bdf36-70ed-44cf-9ffa-e92a30397f92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383535864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.3383535864
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4125876716
Short name	T514
Test name
Test status
Simulation time	299790977 ps
CPU time	77.81 seconds
Started	Mar 19 01:24:51 PM PDT 24
Finished	Mar 19 01:26:11 PM PDT 24
Peak memory	312872 kb
Host	smart-86d702f8-0f16-450a-8072-8fb024a7ec33
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4125876716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.4125876716
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3718669219
Short name	T535
Test name
Test status
Simulation time	15362986537 ps
CPU time	341.05 seconds
Started	Mar 19 01:24:44 PM PDT 24
Finished	Mar 19 01:30:25 PM PDT 24
Peak memory	203312 kb
Host	smart-b03f4173-b51d-4793-9983-0f17603bb1c4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718669219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3718669219
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2902969875
Short name	T365
Test name
Test status
Simulation time	146468524 ps
CPU time	1.37 seconds
Started	Mar 19 01:24:44 PM PDT 24
Finished	Mar 19 01:24:45 PM PDT 24
Peak memory	211412 kb
Host	smart-a4e25888-aa57-455b-a757-b74491034612
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902969875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2902969875
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3246716804
Short name	T705
Test name
Test status
Simulation time	5592421013 ps
CPU time	812.32 seconds
Started	Mar 19 01:25:08 PM PDT 24
Finished	Mar 19 01:38:40 PM PDT 24
Peak memory	368960 kb
Host	smart-5fe57b70-b935-42c3-a864-4550bfea21c8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246716804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.3246716804
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.16831305
Short name	T427
Test name
Test status
Simulation time	30036537 ps
CPU time	0.6 seconds
Started	Mar 19 01:25:11 PM PDT 24
Finished	Mar 19 01:25:12 PM PDT 24
Peak memory	202996 kb
Host	smart-bf6df078-cb63-433a-a475-27c2e444ce48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_alert_test.16831305
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.881643493
Short name	T453
Test name
Test status
Simulation time	537364607 ps
CPU time	33.56 seconds
Started	Mar 19 01:24:55 PM PDT 24
Finished	Mar 19 01:25:28 PM PDT 24
Peak memory	203240 kb
Host	smart-3b62cced-d031-4ac0-97b9-9577e8cb4760
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881643493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 881643493
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_executable.1056932607
Short name	T865
Test name
Test status
Simulation time	13701749932 ps
CPU time	1617.01 seconds
Started	Mar 19 01:25:05 PM PDT 24
Finished	Mar 19 01:52:02 PM PDT 24
Peak memory	374968 kb
Host	smart-d8cbeed1-dbf2-47eb-a1c6-9a8b0ac36475
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056932607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1056932607
Directory	/workspace/29.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.1740085240
Short name	T389
Test name
Test status
Simulation time	762612129 ps
CPU time	7.01 seconds
Started	Mar 19 01:25:08 PM PDT 24
Finished	Mar 19 01:25:15 PM PDT 24
Peak memory	203184 kb
Host	smart-e880273d-f305-4399-a118-70e57ead4441
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740085240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.1740085240
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.1663758252
Short name	T409
Test name
Test status
Simulation time	139585406 ps
CPU time	13.18 seconds
Started	Mar 19 01:25:07 PM PDT 24
Finished	Mar 19 01:25:21 PM PDT 24
Peak memory	256780 kb
Host	smart-95f2d524-9303-4ae2-802a-267e29fe66de
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663758252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1663758252
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2714065468
Short name	T572
Test name
Test status
Simulation time	52415187 ps
CPU time	2.54 seconds
Started	Mar 19 01:25:11 PM PDT 24
Finished	Mar 19 01:25:14 PM PDT 24
Peak memory	211484 kb
Host	smart-3468266c-c6de-4706-aa64-a25a4675ac4e
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714065468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2714065468
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.4291746678
Short name	T764
Test name
Test status
Simulation time	581433929 ps
CPU time	9.53 seconds
Started	Mar 19 01:25:07 PM PDT 24
Finished	Mar 19 01:25:17 PM PDT 24
Peak memory	203308 kb
Host	smart-9c9debaf-786e-4252-9c74-a2a68388c640
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291746678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.4291746678
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.1228427084
Short name	T833
Test name
Test status
Simulation time	17147227365 ps
CPU time	559.68 seconds
Started	Mar 19 01:24:56 PM PDT 24
Finished	Mar 19 01:34:16 PM PDT 24
Peak memory	369900 kb
Host	smart-8bc3b7bb-8423-4ba8-9e98-a9acba6ecf72
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228427084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.1228427084
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.763310415
Short name	T179
Test name
Test status
Simulation time	509287803 ps
CPU time	28.9 seconds
Started	Mar 19 01:25:02 PM PDT 24
Finished	Mar 19 01:25:31 PM PDT 24
Peak memory	278620 kb
Host	smart-2847b8ac-e8f5-4b85-8563-6ac56fdda82b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763310415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.763310415
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1456261478
Short name	T799
Test name
Test status
Simulation time	54463853123 ps
CPU time	313.86 seconds
Started	Mar 19 01:25:06 PM PDT 24
Finished	Mar 19 01:30:20 PM PDT 24
Peak memory	203272 kb
Host	smart-7f0a9b93-62a4-4833-bc26-dff46c6c6ea1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456261478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1456261478
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.501109708
Short name	T22
Test name
Test status
Simulation time	29723439 ps
CPU time	0.76 seconds
Started	Mar 19 01:25:06 PM PDT 24
Finished	Mar 19 01:25:07 PM PDT 24
Peak memory	203224 kb
Host	smart-032d0f67-de2b-4bb8-845b-34023ffeb8ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501109708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.501109708
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.3072017385
Short name	T460
Test name
Test status
Simulation time	23400909295 ps
CPU time	377.26 seconds
Started	Mar 19 01:25:07 PM PDT 24
Finished	Mar 19 01:31:24 PM PDT 24
Peak memory	338024 kb
Host	smart-f63cb2a4-da41-4b15-836b-f56a84e7df01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072017385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3072017385
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.1815071330
Short name	T35
Test name
Test status
Simulation time	1430148865 ps
CPU time	134.38 seconds
Started	Mar 19 01:24:55 PM PDT 24
Finished	Mar 19 01:27:10 PM PDT 24
Peak memory	367792 kb
Host	smart-9ec2233e-c200-45b2-84da-f28560696331
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815071330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1815071330
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.3789526935
Short name	T901
Test name
Test status
Simulation time	37793561906 ps
CPU time	3260.83 seconds
Started	Mar 19 01:25:14 PM PDT 24
Finished	Mar 19 02:19:36 PM PDT 24
Peak memory	375156 kb
Host	smart-797b35c4-18a5-424c-a237-a6ca60ed65dc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789526935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.3789526935
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1992839911
Short name	T46
Test name
Test status
Simulation time	822238703 ps
CPU time	93.71 seconds
Started	Mar 19 01:25:14 PM PDT 24
Finished	Mar 19 01:26:48 PM PDT 24
Peak memory	339228 kb
Host	smart-2cfbeb59-f714-4c1a-85c4-0d553c2453ec
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1992839911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1992839911
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3035328516
Short name	T640
Test name
Test status
Simulation time	7028694946 ps
CPU time	207.3 seconds
Started	Mar 19 01:25:01 PM PDT 24
Finished	Mar 19 01:28:28 PM PDT 24
Peak memory	203324 kb
Host	smart-128c2c5f-824e-45df-8daf-dc1a29e51ea8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035328516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3035328516
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.685747903
Short name	T765
Test name
Test status
Simulation time	105617827 ps
CPU time	4.52 seconds
Started	Mar 19 01:25:06 PM PDT 24
Finished	Mar 19 01:25:11 PM PDT 24
Peak memory	225936 kb
Host	smart-d3325792-1bcb-4091-b273-ea9fe4c056c5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685747903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.685747903
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3479208706
Short name	T299
Test name
Test status
Simulation time	3903832356 ps
CPU time	1381.42 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:44:21 PM PDT 24
Peak memory	375024 kb
Host	smart-c89f0164-e435-4a70-a611-a208b4bb44d7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479208706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3479208706
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.3729838897
Short name	T3
Test name
Test status
Simulation time	14186528 ps
CPU time	0.64 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:21:20 PM PDT 24
Peak memory	203032 kb
Host	smart-09382381-e158-41ca-9ea7-63399e93d973
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729838897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3729838897
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.4246482320
Short name	T59
Test name
Test status
Simulation time	13480207989 ps
CPU time	45.54 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:22:06 PM PDT 24
Peak memory	203300 kb
Host	smart-0d5d1948-73b0-424e-bba1-8a1736661dfb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246482320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 4246482320
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.2234133427
Short name	T282
Test name
Test status
Simulation time	6628771471 ps
CPU time	318.46 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:26:40 PM PDT 24
Peak memory	364028 kb
Host	smart-14beb3c8-2e7a-4ea8-aa4e-ab73bffff602
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234133427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.2234133427
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.3387914543
Short name	T509
Test name
Test status
Simulation time	993066130 ps
CPU time	6.98 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	203212 kb
Host	smart-b1784c31-cc47-4774-ab2f-caaf3f4550e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387914543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3387914543
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.3165582716
Short name	T704
Test name
Test status
Simulation time	134395499 ps
CPU time	138.04 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:23:39 PM PDT 24
Peak memory	369504 kb
Host	smart-061117c6-7096-48b0-936a-228f726dfd4a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165582716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3165582716
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.486823893
Short name	T592
Test name
Test status
Simulation time	600871060 ps
CPU time	5.65 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:21:30 PM PDT 24
Peak memory	211424 kb
Host	smart-5c2de65d-1694-40f4-a51d-e177a28d556d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486823893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.486823893
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.2837325796
Short name	T56
Test name
Test status
Simulation time	78656950 ps
CPU time	4.77 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	203292 kb
Host	smart-acffbd3d-4ea6-4635-b156-9b667659bf3f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837325796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2837325796
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.558631850
Short name	T536
Test name
Test status
Simulation time	4336872995 ps
CPU time	543.61 seconds
Started	Mar 19 01:21:13 PM PDT 24
Finished	Mar 19 01:30:16 PM PDT 24
Peak memory	363784 kb
Host	smart-6ef2d45a-a6fc-4c75-bbc9-ddb94b0ba15f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558631850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.558631850
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.599345301
Short name	T210
Test name
Test status
Simulation time	93187770 ps
CPU time	2 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:25 PM PDT 24
Peak memory	203392 kb
Host	smart-809453d5-81f2-43ee-8701-999faf7b0e37
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599345301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.599345301
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.50493497
Short name	T346
Test name
Test status
Simulation time	37021585753 ps
CPU time	424.14 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:28:28 PM PDT 24
Peak memory	203364 kb
Host	smart-f4c988cc-4c8b-436b-9c85-8ea0435b47aa
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50493497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_partial_access_b2b.50493497
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.76377506
Short name	T866
Test name
Test status
Simulation time	45766004 ps
CPU time	0.72 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:21:25 PM PDT 24
Peak memory	203300 kb
Host	smart-78253581-4c97-4e9f-ab6a-afe5e9fd96e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76377506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.76377506
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.2844702271
Short name	T475
Test name
Test status
Simulation time	19349818091 ps
CPU time	1101.24 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:39:41 PM PDT 24
Peak memory	371968 kb
Host	smart-dd63eb9b-52ee-4cf2-ba8b-b27303ba94b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844702271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2844702271
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_sec_cm.865582053
Short name	T25
Test name
Test status
Simulation time	1783994651 ps
CPU time	4.01 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:21:26 PM PDT 24
Peak memory	222196 kb
Host	smart-106d017b-fd6d-4c54-9245-bf0e2f42d3d3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865582053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.865582053
Directory	/workspace/3.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.2486759041
Short name	T526
Test name
Test status
Simulation time	702490414 ps
CPU time	3.13 seconds
Started	Mar 19 01:21:14 PM PDT 24
Finished	Mar 19 01:21:17 PM PDT 24
Peak memory	211228 kb
Host	smart-3ed4341c-f08b-40e8-95c9-552ca5894db9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486759041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2486759041
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3021591549
Short name	T116
Test name
Test status
Simulation time	8015948197 ps
CPU time	141.12 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:23:45 PM PDT 24
Peak memory	311684 kb
Host	smart-b3e0bc06-da6f-4bdc-bb9c-0e2c7db1424c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3021591549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3021591549
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.4116480637
Short name	T877
Test name
Test status
Simulation time	2786206136 ps
CPU time	242.13 seconds
Started	Mar 19 01:21:18 PM PDT 24
Finished	Mar 19 01:25:21 PM PDT 24
Peak memory	203360 kb
Host	smart-343e7b53-5217-45f4-90e6-3e7752f72024
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116480637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.4116480637
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1936000526
Short name	T890
Test name
Test status
Simulation time	495926662 ps
CPU time	105.53 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:23:06 PM PDT 24
Peak memory	354412 kb
Host	smart-c5d410f1-eb42-410f-b39b-1785f45e3de9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936000526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1936000526
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2062475292
Short name	T80
Test name
Test status
Simulation time	18070545993 ps
CPU time	1347.72 seconds
Started	Mar 19 01:25:19 PM PDT 24
Finished	Mar 19 01:47:48 PM PDT 24
Peak memory	374016 kb
Host	smart-23cd11bf-95ee-4abd-85bb-7af3fc1578c5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062475292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2062475292
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.1766368514
Short name	T194
Test name
Test status
Simulation time	13180446 ps
CPU time	0.63 seconds
Started	Mar 19 01:25:22 PM PDT 24
Finished	Mar 19 01:25:25 PM PDT 24
Peak memory	202128 kb
Host	smart-65d25e16-8a3d-412d-bc53-ec5d4b7d9dc8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766368514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1766368514
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.207532372
Short name	T227
Test name
Test status
Simulation time	439941546 ps
CPU time	26.24 seconds
Started	Mar 19 01:25:15 PM PDT 24
Finished	Mar 19 01:25:43 PM PDT 24
Peak memory	203152 kb
Host	smart-5a0baa96-bd2a-44ac-ad7c-9636688ba673
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207532372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection. 207532372
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.511831051
Short name	T169
Test name
Test status
Simulation time	3053380424 ps
CPU time	470.22 seconds
Started	Mar 19 01:25:22 PM PDT 24
Finished	Mar 19 01:33:12 PM PDT 24
Peak memory	362340 kb
Host	smart-fee10afc-458d-4020-83ab-b58e351e8534
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511831051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl e.511831051
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.2903470584
Short name	T604
Test name
Test status
Simulation time	195172012 ps
CPU time	3.22 seconds
Started	Mar 19 01:25:21 PM PDT 24
Finished	Mar 19 01:25:24 PM PDT 24
Peak memory	203216 kb
Host	smart-dc846fe6-14eb-49ea-8574-1caf795fd9fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903470584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2903470584
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.234675301
Short name	T900
Test name
Test status
Simulation time	448767455 ps
CPU time	83.3 seconds
Started	Mar 19 01:25:20 PM PDT 24
Finished	Mar 19 01:26:44 PM PDT 24
Peak memory	345232 kb
Host	smart-6a3b02da-ad27-47d7-98ae-d517b87fb41a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234675301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.sram_ctrl_max_throughput.234675301
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1997993052
Short name	T84
Test name
Test status
Simulation time	158079116 ps
CPU time	4.46 seconds
Started	Mar 19 01:25:21 PM PDT 24
Finished	Mar 19 01:25:25 PM PDT 24
Peak memory	211412 kb
Host	smart-076c4834-5074-4885-9711-0fa418a6cbf9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997993052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1997993052
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.3642148662
Short name	T542
Test name
Test status
Simulation time	271994828 ps
CPU time	8.4 seconds
Started	Mar 19 01:25:22 PM PDT 24
Finished	Mar 19 01:25:33 PM PDT 24
Peak memory	203220 kb
Host	smart-3cbfb8ce-854c-456b-a373-137ffdc0b37f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642148662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3642148662
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.3209766046
Short name	T813
Test name
Test status
Simulation time	12566986259 ps
CPU time	1401.12 seconds
Started	Mar 19 01:25:16 PM PDT 24
Finished	Mar 19 01:48:38 PM PDT 24
Peak memory	376088 kb
Host	smart-0b0fa12d-4f2e-486d-9f10-a0c7ea584d5e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209766046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.3209766046
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.351604603
Short name	T165
Test name
Test status
Simulation time	1958372482 ps
CPU time	9.97 seconds
Started	Mar 19 01:25:25 PM PDT 24
Finished	Mar 19 01:25:35 PM PDT 24
Peak memory	203264 kb
Host	smart-2d071686-09e5-48be-a648-72e0cb1a97ab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351604603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s ram_ctrl_partial_access.351604603
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2050596005
Short name	T827
Test name
Test status
Simulation time	20155609559 ps
CPU time	501.96 seconds
Started	Mar 19 01:25:15 PM PDT 24
Finished	Mar 19 01:33:37 PM PDT 24
Peak memory	203316 kb
Host	smart-1b8620e8-53ee-487d-a251-39b3ef4342e3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050596005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.2050596005
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.2275281186
Short name	T1
Test name
Test status
Simulation time	90712147 ps
CPU time	0.76 seconds
Started	Mar 19 01:25:20 PM PDT 24
Finished	Mar 19 01:25:21 PM PDT 24
Peak memory	203336 kb
Host	smart-8bb02d91-0325-49d2-bef4-eb46ff235c44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275281186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2275281186
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.2554917877
Short name	T452
Test name
Test status
Simulation time	73372054945 ps
CPU time	608.51 seconds
Started	Mar 19 01:25:22 PM PDT 24
Finished	Mar 19 01:35:30 PM PDT 24
Peak memory	372376 kb
Host	smart-d0d72d07-b9bf-4411-8218-4c15b393f508
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554917877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2554917877
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.3181406667
Short name	T369
Test name
Test status
Simulation time	107450625 ps
CPU time	33.34 seconds
Started	Mar 19 01:25:11 PM PDT 24
Finished	Mar 19 01:25:44 PM PDT 24
Peak memory	291752 kb
Host	smart-9999c5c0-e747-4784-88a0-86dd75361454
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181406667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3181406667
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all.2018504813
Short name	T809
Test name
Test status
Simulation time	26133519884 ps
CPU time	3193.58 seconds
Started	Mar 19 01:25:21 PM PDT 24
Finished	Mar 19 02:18:35 PM PDT 24
Peak memory	375492 kb
Host	smart-d8788478-aab6-41d2-8f8f-41cd7907d988
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018504813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.2018504813
Directory	/workspace/30.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3034937484
Short name	T837
Test name
Test status
Simulation time	1870063117 ps
CPU time	60.44 seconds
Started	Mar 19 01:25:20 PM PDT 24
Finished	Mar 19 01:26:21 PM PDT 24
Peak memory	236872 kb
Host	smart-359ef3eb-15c3-4beb-83a6-00aeaca3a5be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3034937484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3034937484
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3047009992
Short name	T222
Test name
Test status
Simulation time	1519432473 ps
CPU time	140.66 seconds
Started	Mar 19 01:25:15 PM PDT 24
Finished	Mar 19 01:27:35 PM PDT 24
Peak memory	203268 kb
Host	smart-e56da736-2e1c-4837-9ea5-457e1e27c784
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047009992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.3047009992
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3895398788
Short name	T560
Test name
Test status
Simulation time	149473466 ps
CPU time	75.03 seconds
Started	Mar 19 01:25:25 PM PDT 24
Finished	Mar 19 01:26:40 PM PDT 24
Peak memory	327872 kb
Host	smart-b3033f22-8576-4fc3-b9b5-c931508758c8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895398788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3895398788
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2615002608
Short name	T408
Test name
Test status
Simulation time	4085061412 ps
CPU time	1018.9 seconds
Started	Mar 19 01:25:31 PM PDT 24
Finished	Mar 19 01:42:31 PM PDT 24
Peak memory	372084 kb
Host	smart-a5c6a836-07c3-4df2-8432-2acce1b771a8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615002608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2615002608
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.1724451935
Short name	T556
Test name
Test status
Simulation time	31173904 ps
CPU time	0.66 seconds
Started	Mar 19 01:25:33 PM PDT 24
Finished	Mar 19 01:25:34 PM PDT 24
Peak memory	202112 kb
Host	smart-49ba05d5-3fb6-4bfd-b415-f46d0162a060
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724451935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1724451935
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.546365255
Short name	T451
Test name
Test status
Simulation time	2756207078 ps
CPU time	40.99 seconds
Started	Mar 19 01:25:25 PM PDT 24
Finished	Mar 19 01:26:10 PM PDT 24
Peak memory	203336 kb
Host	smart-96db4dc6-e79f-479e-b92d-fe94addad8fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546365255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 546365255
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.3219126881
Short name	T854
Test name
Test status
Simulation time	2917610637 ps
CPU time	225.11 seconds
Started	Mar 19 01:25:33 PM PDT 24
Finished	Mar 19 01:29:18 PM PDT 24
Peak memory	358936 kb
Host	smart-59f383e1-299b-47ef-8423-d31216de56e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219126881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3219126881
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.630069128
Short name	T700
Test name
Test status
Simulation time	2993091957 ps
CPU time	6.38 seconds
Started	Mar 19 01:25:33 PM PDT 24
Finished	Mar 19 01:25:39 PM PDT 24
Peak memory	203284 kb
Host	smart-0fc4e57b-3cea-481c-b669-7830cf78be1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630069128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.630069128
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.1867746017
Short name	T267
Test name
Test status
Simulation time	120914130 ps
CPU time	51.19 seconds
Started	Mar 19 01:25:32 PM PDT 24
Finished	Mar 19 01:26:23 PM PDT 24
Peak memory	342092 kb
Host	smart-82eff2ac-1d0a-4003-9acd-e3781677ecbc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867746017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.1867746017
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3384886218
Short name	T621
Test name
Test status
Simulation time	162830552 ps
CPU time	5.25 seconds
Started	Mar 19 01:25:32 PM PDT 24
Finished	Mar 19 01:25:37 PM PDT 24
Peak memory	211324 kb
Host	smart-b78bad0d-7e9b-40a1-8fac-3740a845e090
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384886218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.3384886218
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.1640438384
Short name	T7
Test name
Test status
Simulation time	589769568 ps
CPU time	10.53 seconds
Started	Mar 19 01:25:33 PM PDT 24
Finished	Mar 19 01:25:44 PM PDT 24
Peak memory	203256 kb
Host	smart-ed1c8d68-e6f0-4ed5-b15b-af4517966800
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640438384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1640438384
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.1766556936
Short name	T156
Test name
Test status
Simulation time	2922385173 ps
CPU time	942.97 seconds
Started	Mar 19 01:25:33 PM PDT 24
Finished	Mar 19 01:41:16 PM PDT 24
Peak memory	374152 kb
Host	smart-863ba32a-bdef-4a28-b1a6-09cfb1b1ed61
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766556936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.1766556936
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.2340003293
Short name	T277
Test name
Test status
Simulation time	45602807 ps
CPU time	3.84 seconds
Started	Mar 19 01:25:30 PM PDT 24
Finished	Mar 19 01:25:36 PM PDT 24
Peak memory	216644 kb
Host	smart-b46b9a9e-3c1f-431f-8e0a-17e731d53743
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340003293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2340003293
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2762231368
Short name	T548
Test name
Test status
Simulation time	7975002446 ps
CPU time	541.95 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:34:38 PM PDT 24
Peak memory	203260 kb
Host	smart-1c049e73-2a67-405e-9846-d99298b20557
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762231368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2762231368
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.2230436976
Short name	T432
Test name
Test status
Simulation time	69821902 ps
CPU time	0.78 seconds
Started	Mar 19 01:25:35 PM PDT 24
Finished	Mar 19 01:25:37 PM PDT 24
Peak memory	203228 kb
Host	smart-65a0bf3b-5699-4f15-b8cd-79dc97edda54
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230436976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2230436976
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.916716564
Short name	T897
Test name
Test status
Simulation time	8874381483 ps
CPU time	1016.91 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:42:31 PM PDT 24
Peak memory	373040 kb
Host	smart-6653a347-b914-4934-b5a3-bd1b80693077
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916716564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.916716564
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.2567681950
Short name	T512
Test name
Test status
Simulation time	1847276213 ps
CPU time	45.58 seconds
Started	Mar 19 01:25:21 PM PDT 24
Finished	Mar 19 01:26:07 PM PDT 24
Peak memory	300212 kb
Host	smart-ac3ad617-53fa-4bbb-a145-c502115322b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567681950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2567681950
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.503116353
Short name	T918
Test name
Test status
Simulation time	53360069029 ps
CPU time	1763.82 seconds
Started	Mar 19 01:25:32 PM PDT 24
Finished	Mar 19 01:54:57 PM PDT 24
Peak memory	383272 kb
Host	smart-f2be912f-6d23-4b05-b7f0-5dbdaa7c641b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503116353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_stress_all.503116353
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.152666360
Short name	T347
Test name
Test status
Simulation time	7914630200 ps
CPU time	984.61 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:42:00 PM PDT 24
Peak memory	377232 kb
Host	smart-30710e24-76ae-4cbc-ab0d-240ea314ac4e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=152666360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.152666360
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3165888334
Short name	T239
Test name
Test status
Simulation time	2448178166 ps
CPU time	235.42 seconds
Started	Mar 19 01:25:25 PM PDT 24
Finished	Mar 19 01:29:21 PM PDT 24
Peak memory	203256 kb
Host	smart-7d29fd05-14e3-4107-a728-c89a517a6759
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165888334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3165888334
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.4241776357
Short name	T480
Test name
Test status
Simulation time	77988179 ps
CPU time	8.31 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:25:44 PM PDT 24
Peak memory	240872 kb
Host	smart-9ec265e6-2b80-4695-8156-728c2b958ac7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241776357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.4241776357
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2351159935
Short name	T57
Test name
Test status
Simulation time	18733117787 ps
CPU time	1007.53 seconds
Started	Mar 19 01:25:41 PM PDT 24
Finished	Mar 19 01:42:29 PM PDT 24
Peak memory	375144 kb
Host	smart-d88dcd3f-78ec-443d-803c-9cf8ccf94422
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351159935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2351159935
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.1066840628
Short name	T12
Test name
Test status
Simulation time	938715781 ps
CPU time	13.41 seconds
Started	Mar 19 01:25:35 PM PDT 24
Finished	Mar 19 01:25:49 PM PDT 24
Peak memory	203192 kb
Host	smart-02c479a1-4088-4469-9396-1c6a1342fbab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066840628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1066840628
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.3817692925
Short name	T810
Test name
Test status
Simulation time	2741617567 ps
CPU time	986.22 seconds
Started	Mar 19 01:25:41 PM PDT 24
Finished	Mar 19 01:42:07 PM PDT 24
Peak memory	373232 kb
Host	smart-27c5569a-194d-433c-bde9-ae2324521d44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817692925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3817692925
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.1214593874
Short name	T354
Test name
Test status
Simulation time	750908851 ps
CPU time	2.9 seconds
Started	Mar 19 01:25:41 PM PDT 24
Finished	Mar 19 01:25:44 PM PDT 24
Peak memory	203160 kb
Host	smart-590ff094-fb93-4f94-aa84-7ad73002250b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214593874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1214593874
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.3361168572
Short name	T243
Test name
Test status
Simulation time	212054437 ps
CPU time	53.25 seconds
Started	Mar 19 01:25:46 PM PDT 24
Finished	Mar 19 01:26:40 PM PDT 24
Peak memory	314600 kb
Host	smart-89021d94-87bd-45d1-9f7c-e0e78cb5bf8c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361168572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3361168572
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3361339384
Short name	T856
Test name
Test status
Simulation time	160442341 ps
CPU time	2.72 seconds
Started	Mar 19 01:25:46 PM PDT 24
Finished	Mar 19 01:25:49 PM PDT 24
Peak memory	211408 kb
Host	smart-5bd82614-9260-4813-88e8-15bcda8829a7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361339384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3361339384
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.1206460338
Short name	T95
Test name
Test status
Simulation time	716602226 ps
CPU time	8.24 seconds
Started	Mar 19 01:25:51 PM PDT 24
Finished	Mar 19 01:26:01 PM PDT 24
Peak memory	203284 kb
Host	smart-28ef95c4-d5dc-4187-a26c-ba1f2c8fe697
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206460338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1206460338
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.1116288454
Short name	T573
Test name
Test status
Simulation time	24860883836 ps
CPU time	889.44 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:40:25 PM PDT 24
Peak memory	358060 kb
Host	smart-d49ada5e-f32a-4365-8a66-c8da7922decc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116288454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.1116288454
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.4228994133
Short name	T591
Test name
Test status
Simulation time	716339145 ps
CPU time	158.65 seconds
Started	Mar 19 01:25:34 PM PDT 24
Finished	Mar 19 01:28:14 PM PDT 24
Peak memory	368788 kb
Host	smart-9277fe3f-59b1-47d7-96a3-f0c97f299ec8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228994133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.4228994133
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.734701372
Short name	T716
Test name
Test status
Simulation time	34387845977 ps
CPU time	410.9 seconds
Started	Mar 19 01:25:36 PM PDT 24
Finished	Mar 19 01:32:27 PM PDT 24
Peak memory	203308 kb
Host	smart-e6f8e204-29db-41a1-8ca7-cd3aed39d816
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734701372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.sram_ctrl_partial_access_b2b.734701372
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.3880856842
Short name	T596
Test name
Test status
Simulation time	26652972 ps
CPU time	0.76 seconds
Started	Mar 19 01:25:46 PM PDT 24
Finished	Mar 19 01:25:47 PM PDT 24
Peak memory	203308 kb
Host	smart-003901af-db99-42e6-a4c1-92a0050ec4a6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880856842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3880856842
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.2459447911
Short name	T288
Test name
Test status
Simulation time	19514127282 ps
CPU time	949.06 seconds
Started	Mar 19 01:25:46 PM PDT 24
Finished	Mar 19 01:41:36 PM PDT 24
Peak memory	376104 kb
Host	smart-91ab1460-fab9-4e82-9e43-f12c7887a519
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459447911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2459447911
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.944943857
Short name	T824
Test name
Test status
Simulation time	279741302 ps
CPU time	13.98 seconds
Started	Mar 19 01:25:37 PM PDT 24
Finished	Mar 19 01:25:51 PM PDT 24
Peak memory	252196 kb
Host	smart-32a98d2d-ccd2-467e-9f7a-944a775b8f50
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944943857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.944943857
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.687650992
Short name	T513
Test name
Test status
Simulation time	7167333431 ps
CPU time	1944.19 seconds
Started	Mar 19 01:25:45 PM PDT 24
Finished	Mar 19 01:58:11 PM PDT 24
Peak memory	376040 kb
Host	smart-e2df91d5-d338-4e66-a3b5-ce0b9d03b509
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687650992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.687650992
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.281878129
Short name	T48
Test name
Test status
Simulation time	4798394031 ps
CPU time	337.75 seconds
Started	Mar 19 01:25:47 PM PDT 24
Finished	Mar 19 01:31:25 PM PDT 24
Peak memory	371664 kb
Host	smart-d1e4c368-6c13-4d7d-91a8-37f683968f91
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=281878129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.281878129
Directory	/workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1081021566
Short name	T821
Test name
Test status
Simulation time	6449284380 ps
CPU time	151.44 seconds
Started	Mar 19 01:25:35 PM PDT 24
Finished	Mar 19 01:28:07 PM PDT 24
Peak memory	203320 kb
Host	smart-63e51c12-4b3e-42c0-acdc-fef18d86342c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081021566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1081021566
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3465226025
Short name	T550
Test name
Test status
Simulation time	85728851 ps
CPU time	20.78 seconds
Started	Mar 19 01:25:40 PM PDT 24
Finished	Mar 19 01:26:01 PM PDT 24
Peak memory	273800 kb
Host	smart-6f150a1f-bd51-4757-b0ff-b6b42c107377
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465226025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3465226025
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.67467664
Short name	T839
Test name
Test status
Simulation time	1361595215 ps
CPU time	268.89 seconds
Started	Mar 19 01:25:55 PM PDT 24
Finished	Mar 19 01:30:27 PM PDT 24
Peak memory	356160 kb
Host	smart-77cd88e2-202f-4d83-9ad2-f85efd7658a9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67467664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.sram_ctrl_access_during_key_req.67467664
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.2416536464
Short name	T758
Test name
Test status
Simulation time	20937378 ps
CPU time	0.67 seconds
Started	Mar 19 01:26:00 PM PDT 24
Finished	Mar 19 01:26:01 PM PDT 24
Peak memory	202188 kb
Host	smart-e17ccd13-44b6-4784-b53d-a382a202c93c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416536464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2416536464
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.1592363060
Short name	T650
Test name
Test status
Simulation time	3346979914 ps
CPU time	61.21 seconds
Started	Mar 19 01:25:50 PM PDT 24
Finished	Mar 19 01:26:51 PM PDT 24
Peak memory	203320 kb
Host	smart-024cab3c-8965-4bbc-a7db-b161e43bd76a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592363060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1592363060
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.2103655935
Short name	T121
Test name
Test status
Simulation time	27639429960 ps
CPU time	1580.48 seconds
Started	Mar 19 01:25:58 PM PDT 24
Finished	Mar 19 01:52:19 PM PDT 24
Peak memory	375044 kb
Host	smart-3103a605-b68a-4a34-8f4a-fab1b8728bdd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103655935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.2103655935
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.1036949233
Short name	T123
Test name
Test status
Simulation time	1960534805 ps
CPU time	5.82 seconds
Started	Mar 19 01:25:51 PM PDT 24
Finished	Mar 19 01:25:58 PM PDT 24
Peak memory	203196 kb
Host	smart-439e5168-ee08-4a0a-8a5a-a603825d2d5d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036949233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.1036949233
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.2644423690
Short name	T795
Test name
Test status
Simulation time	75667441 ps
CPU time	13.93 seconds
Started	Mar 19 01:25:51 PM PDT 24
Finished	Mar 19 01:26:06 PM PDT 24
Peak memory	258792 kb
Host	smart-c0d31035-37f1-4ab9-9ac6-a9ccab09e20e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644423690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2644423690
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3559088660
Short name	T312
Test name
Test status
Simulation time	103389176 ps
CPU time	3.1 seconds
Started	Mar 19 01:25:57 PM PDT 24
Finished	Mar 19 01:26:01 PM PDT 24
Peak memory	211472 kb
Host	smart-08c96d56-1f67-419f-94b7-f3da888c2a25
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559088660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3559088660
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.3403101223
Short name	T593
Test name
Test status
Simulation time	443181962 ps
CPU time	9.97 seconds
Started	Mar 19 01:25:58 PM PDT 24
Finished	Mar 19 01:26:08 PM PDT 24
Peak memory	203292 kb
Host	smart-2a1009c9-b5ff-46f6-830e-091b572bd153
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403101223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3403101223
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.2453940409
Short name	T405
Test name
Test status
Simulation time	111769448331 ps
CPU time	2018.31 seconds
Started	Mar 19 01:25:47 PM PDT 24
Finished	Mar 19 01:59:25 PM PDT 24
Peak memory	375664 kb
Host	smart-66bcb738-38f9-45dd-b5a8-76b3bcb6b471
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453940409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2453940409
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.213829024
Short name	T715
Test name
Test status
Simulation time	152982487 ps
CPU time	2.9 seconds
Started	Mar 19 01:25:50 PM PDT 24
Finished	Mar 19 01:25:53 PM PDT 24
Peak memory	203348 kb
Host	smart-fbee9dc6-90aa-448c-bd12-cf085741956f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213829024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.213829024
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2693193238
Short name	T846
Test name
Test status
Simulation time	2693929025 ps
CPU time	192.54 seconds
Started	Mar 19 01:25:53 PM PDT 24
Finished	Mar 19 01:29:10 PM PDT 24
Peak memory	203256 kb
Host	smart-d64e24be-e44f-45eb-bee0-dbe37cff29cc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693193238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2693193238
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.4046084283
Short name	T240
Test name
Test status
Simulation time	173824042 ps
CPU time	0.84 seconds
Started	Mar 19 01:25:57 PM PDT 24
Finished	Mar 19 01:25:59 PM PDT 24
Peak memory	203248 kb
Host	smart-d02a7dca-e945-4e50-bb2d-46b5ef2eceae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046084283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.4046084283
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_regwen.2061851382
Short name	T771
Test name
Test status
Simulation time	2321925463 ps
CPU time	853.73 seconds
Started	Mar 19 01:25:57 PM PDT 24
Finished	Mar 19 01:40:12 PM PDT 24
Peak memory	365808 kb
Host	smart-72a3c024-c5bf-4ad7-9a0c-5d19b8897666
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061851382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2061851382
Directory	/workspace/33.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.2563653125
Short name	T352
Test name
Test status
Simulation time	167655081 ps
CPU time	142.46 seconds
Started	Mar 19 01:25:45 PM PDT 24
Finished	Mar 19 01:28:09 PM PDT 24
Peak memory	357584 kb
Host	smart-8cf8ae99-b7a3-48f7-ae7c-cb55ebe12c54
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563653125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2563653125
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.1024732386
Short name	T728
Test name
Test status
Simulation time	20898328142 ps
CPU time	2128.43 seconds
Started	Mar 19 01:26:02 PM PDT 24
Finished	Mar 19 02:01:31 PM PDT 24
Peak memory	376116 kb
Host	smart-389d417f-3baf-4ecc-900a-6383198dee45
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024732386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.1024732386
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1369150169
Short name	T628
Test name
Test status
Simulation time	3158937495 ps
CPU time	302.53 seconds
Started	Mar 19 01:25:58 PM PDT 24
Finished	Mar 19 01:31:00 PM PDT 24
Peak memory	368364 kb
Host	smart-789db0e6-f2c9-4544-b057-8d0cd09281d3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1369150169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1369150169
Directory	/workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2507250816
Short name	T927
Test name
Test status
Simulation time	2337319944 ps
CPU time	125.36 seconds
Started	Mar 19 01:25:51 PM PDT 24
Finished	Mar 19 01:27:58 PM PDT 24
Peak memory	203296 kb
Host	smart-d80e8b38-68dd-4056-b72c-176b803e022d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507250816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2507250816
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3864678890
Short name	T528
Test name
Test status
Simulation time	119645315 ps
CPU time	42.81 seconds
Started	Mar 19 01:25:51 PM PDT 24
Finished	Mar 19 01:26:35 PM PDT 24
Peak memory	306528 kb
Host	smart-ad10b594-eb3f-469b-8033-08fc310bf4d4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864678890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3864678890
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3179918154
Short name	T246
Test name
Test status
Simulation time	21566469679 ps
CPU time	1022.2 seconds
Started	Mar 19 01:26:06 PM PDT 24
Finished	Mar 19 01:43:08 PM PDT 24
Peak memory	376168 kb
Host	smart-6f042845-c241-4c08-98a1-88e7e388a6f7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179918154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3179918154
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.2736855128
Short name	T499
Test name
Test status
Simulation time	11500816 ps
CPU time	0.65 seconds
Started	Mar 19 01:26:14 PM PDT 24
Finished	Mar 19 01:26:16 PM PDT 24
Peak memory	201968 kb
Host	smart-ba54e732-eb4e-4c3e-ad8d-63b7757fae07
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736855128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2736855128
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.2873743834
Short name	T444
Test name
Test status
Simulation time	760849890 ps
CPU time	48.23 seconds
Started	Mar 19 01:26:01 PM PDT 24
Finished	Mar 19 01:26:50 PM PDT 24
Peak memory	203220 kb
Host	smart-78a30610-54bb-497e-bab3-0cbfbbd80a48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873743834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2873743834
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.928246056
Short name	T801
Test name
Test status
Simulation time	16812268683 ps
CPU time	1166.55 seconds
Started	Mar 19 01:26:08 PM PDT 24
Finished	Mar 19 01:45:35 PM PDT 24
Peak memory	374440 kb
Host	smart-c26e0c2f-e11a-42c6-9b09-f80c4ede35af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928246056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.928246056
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.2931667844
Short name	T858
Test name
Test status
Simulation time	1032736139 ps
CPU time	9.93 seconds
Started	Mar 19 01:26:07 PM PDT 24
Finished	Mar 19 01:26:17 PM PDT 24
Peak memory	211404 kb
Host	smart-dbf249de-65ca-47f8-a55a-ef9f3dd4b61e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931667844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2931667844
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.453856811
Short name	T720
Test name
Test status
Simulation time	239033877 ps
CPU time	70.85 seconds
Started	Mar 19 01:26:06 PM PDT 24
Finished	Mar 19 01:27:17 PM PDT 24
Peak memory	312516 kb
Host	smart-0e48f03d-d851-4397-a987-2b64d890db7f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453856811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.453856811
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1073100633
Short name	T906
Test name
Test status
Simulation time	159314045 ps
CPU time	4.98 seconds
Started	Mar 19 01:26:10 PM PDT 24
Finished	Mar 19 01:26:15 PM PDT 24
Peak memory	211488 kb
Host	smart-208721cc-78ea-459f-a7c0-1e7bbce4b0db
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073100633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.1073100633
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.2531765401
Short name	T127
Test name
Test status
Simulation time	540477859 ps
CPU time	9.3 seconds
Started	Mar 19 01:26:05 PM PDT 24
Finished	Mar 19 01:26:15 PM PDT 24
Peak memory	203292 kb
Host	smart-35cf7aaa-cd8f-40d9-8c93-6ad47e3b6d27
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531765401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2531765401
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.3375539757
Short name	T872
Test name
Test status
Simulation time	78851646876 ps
CPU time	1782.96 seconds
Started	Mar 19 01:26:03 PM PDT 24
Finished	Mar 19 01:55:46 PM PDT 24
Peak memory	376012 kb
Host	smart-86d221d3-ad37-4c95-b48d-11a8243681c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375539757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.3375539757
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.31458904
Short name	T161
Test name
Test status
Simulation time	338445414 ps
CPU time	34.01 seconds
Started	Mar 19 01:26:02 PM PDT 24
Finished	Mar 19 01:26:36 PM PDT 24
Peak memory	279904 kb
Host	smart-d7505d2a-3055-4b9e-a5c6-226dc9254a7f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sr am_ctrl_partial_access.31458904
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1037074351
Short name	T738
Test name
Test status
Simulation time	6037169551 ps
CPU time	208.73 seconds
Started	Mar 19 01:26:05 PM PDT 24
Finished	Mar 19 01:29:34 PM PDT 24
Peak memory	203272 kb
Host	smart-725e4f24-78e8-4a16-9cde-4f8d149553fb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037074351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1037074351
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.458707833
Short name	T493
Test name
Test status
Simulation time	281322765 ps
CPU time	0.73 seconds
Started	Mar 19 01:26:07 PM PDT 24
Finished	Mar 19 01:26:08 PM PDT 24
Peak memory	203220 kb
Host	smart-46da8fc4-fd82-4943-850b-363ad8b78936
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458707833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.458707833
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.2347514063
Short name	T279
Test name
Test status
Simulation time	63555150842 ps
CPU time	776.48 seconds
Started	Mar 19 01:26:05 PM PDT 24
Finished	Mar 19 01:39:02 PM PDT 24
Peak memory	358252 kb
Host	smart-c270d4c5-1ab7-44de-9d23-3d9e905367b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347514063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2347514063
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.2061915377
Short name	T537
Test name
Test status
Simulation time	750893742 ps
CPU time	15.26 seconds
Started	Mar 19 01:26:01 PM PDT 24
Finished	Mar 19 01:26:17 PM PDT 24
Peak memory	203152 kb
Host	smart-fc635345-0bd6-445a-b49b-4eb317305494
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061915377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2061915377
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.32630459
Short name	T141
Test name
Test status
Simulation time	202452039699 ps
CPU time	3830.61 seconds
Started	Mar 19 01:26:10 PM PDT 24
Finished	Mar 19 02:30:01 PM PDT 24
Peak memory	376488 kb
Host	smart-8fb21b7a-88c5-46c5-9554-9329b0ede450
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32630459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_stress_all.32630459
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1328404278
Short name	T494
Test name
Test status
Simulation time	4619615234 ps
CPU time	418.72 seconds
Started	Mar 19 01:26:10 PM PDT 24
Finished	Mar 19 01:33:09 PM PDT 24
Peak memory	371008 kb
Host	smart-34a537cb-1d1f-4b27-b298-e6f34779db5d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1328404278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1328404278
Directory	/workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3132855712
Short name	T511
Test name
Test status
Simulation time	55784328220 ps
CPU time	323.78 seconds
Started	Mar 19 01:26:00 PM PDT 24
Finished	Mar 19 01:31:24 PM PDT 24
Peak memory	203356 kb
Host	smart-d99dc491-2c0a-42be-a044-72bbd5f1e4ba
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132855712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3132855712
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.4181144672
Short name	T336
Test name
Test status
Simulation time	220116888 ps
CPU time	149.01 seconds
Started	Mar 19 01:26:07 PM PDT 24
Finished	Mar 19 01:28:36 PM PDT 24
Peak memory	367720 kb
Host	smart-0cbae0dc-db65-4f7f-bbd1-500a74c02da2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181144672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.4181144672
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.4214947533
Short name	T368
Test name
Test status
Simulation time	16921519463 ps
CPU time	1009.85 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 01:43:06 PM PDT 24
Peak memory	375096 kb
Host	smart-36b629b2-273e-4ff4-915b-b5441d4534c0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214947533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.4214947533
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.2624909514
Short name	T565
Test name
Test status
Simulation time	15300759 ps
CPU time	0.65 seconds
Started	Mar 19 01:26:15 PM PDT 24
Finished	Mar 19 01:26:16 PM PDT 24
Peak memory	202332 kb
Host	smart-b75d5116-4fa8-4fe7-a4a4-cfa530715cc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624909514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2624909514
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.2741154016
Short name	T744
Test name
Test status
Simulation time	870852437 ps
CPU time	50.27 seconds
Started	Mar 19 01:26:15 PM PDT 24
Finished	Mar 19 01:27:05 PM PDT 24
Peak memory	203192 kb
Host	smart-cb01b531-3cf3-4f89-9c7b-67cc1b1974ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741154016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2741154016
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.2679148848
Short name	T410
Test name
Test status
Simulation time	25583369373 ps
CPU time	1081.85 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 01:44:18 PM PDT 24
Peak memory	373736 kb
Host	smart-b6ebff39-9958-45d6-9308-e28ce48afcff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679148848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2679148848
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.1972971364
Short name	T250
Test name
Test status
Simulation time	323524067 ps
CPU time	2.24 seconds
Started	Mar 19 01:26:17 PM PDT 24
Finished	Mar 19 01:26:19 PM PDT 24
Peak memory	203192 kb
Host	smart-1ba78ca0-ef1f-4aea-80c9-8eb6fe7e798d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972971364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.1972971364
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.1251066397
Short name	T276
Test name
Test status
Simulation time	35049264 ps
CPU time	0.87 seconds
Started	Mar 19 01:26:14 PM PDT 24
Finished	Mar 19 01:26:16 PM PDT 24
Peak memory	202844 kb
Host	smart-fece3473-8221-43cc-9d71-e14f4d096817
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251066397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1251066397
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.422548891
Short name	T435
Test name
Test status
Simulation time	176247415 ps
CPU time	5.08 seconds
Started	Mar 19 01:26:20 PM PDT 24
Finished	Mar 19 01:26:25 PM PDT 24
Peak memory	211440 kb
Host	smart-f6fe0252-91e8-488a-b17e-b5c785adc6d1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422548891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.422548891
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.48898214
Short name	T317
Test name
Test status
Simulation time	300689883 ps
CPU time	5.16 seconds
Started	Mar 19 01:26:20 PM PDT 24
Finished	Mar 19 01:26:25 PM PDT 24
Peak memory	203264 kb
Host	smart-56b94f06-ca0e-4a0e-9680-f0df772bfe91
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48898214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ mem_walk.48898214
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.3512089968
Short name	T717
Test name
Test status
Simulation time	13471452371 ps
CPU time	513.11 seconds
Started	Mar 19 01:26:11 PM PDT 24
Finished	Mar 19 01:34:44 PM PDT 24
Peak memory	372112 kb
Host	smart-983775c4-a94c-447a-a841-8cf07c69ef72
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512089968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3512089968
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.664379091
Short name	T54
Test name
Test status
Simulation time	1033815015 ps
CPU time	5.77 seconds
Started	Mar 19 01:26:15 PM PDT 24
Finished	Mar 19 01:26:21 PM PDT 24
Peak memory	203180 kb
Host	smart-49c45c5d-c1d1-4f00-bcb1-cc7c92e71e18
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664379091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.664379091
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4015540970
Short name	T345
Test name
Test status
Simulation time	12003428213 ps
CPU time	131.02 seconds
Started	Mar 19 01:26:14 PM PDT 24
Finished	Mar 19 01:28:26 PM PDT 24
Peak memory	203320 kb
Host	smart-f84d5be6-0892-4daf-bc61-7ed842451273
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015540970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.4015540970
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.124453847
Short name	T174
Test name
Test status
Simulation time	38204456 ps
CPU time	0.8 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 01:26:17 PM PDT 24
Peak memory	203292 kb
Host	smart-daebab85-90c6-4e76-b607-119f83606fc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124453847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.124453847
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.1554754145
Short name	T797
Test name
Test status
Simulation time	2774402093 ps
CPU time	500.08 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 01:34:36 PM PDT 24
Peak memory	369820 kb
Host	smart-e0a671c1-d11f-454e-9da6-d0d1fc82ff4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554754145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1554754145
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.947290690
Short name	T614
Test name
Test status
Simulation time	46525857 ps
CPU time	1.8 seconds
Started	Mar 19 01:26:10 PM PDT 24
Finished	Mar 19 01:26:12 PM PDT 24
Peak memory	203204 kb
Host	smart-a1660a19-36c3-45d1-80ae-73c6c9164725
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947290690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.947290690
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.3659469167
Short name	T547
Test name
Test status
Simulation time	37584917591 ps
CPU time	3406.95 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 02:23:04 PM PDT 24
Peak memory	373036 kb
Host	smart-6f52e577-21fa-4e56-a4b8-51adef0a52eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659469167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3659469167
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1671190509
Short name	T725
Test name
Test status
Simulation time	2345961284 ps
CPU time	295.66 seconds
Started	Mar 19 01:26:16 PM PDT 24
Finished	Mar 19 01:31:11 PM PDT 24
Peak memory	347436 kb
Host	smart-ef95f89e-478d-4ae0-ae08-5bc50e6be9c5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1671190509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1671190509
Directory	/workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1905577983
Short name	T485
Test name
Test status
Simulation time	4418452987 ps
CPU time	201.11 seconds
Started	Mar 19 01:26:11 PM PDT 24
Finished	Mar 19 01:29:32 PM PDT 24
Peak memory	203300 kb
Host	smart-559ce36a-3fe1-4339-b720-8f73d5e45215
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905577983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1905577983
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.661838713
Short name	T659
Test name
Test status
Simulation time	139747187 ps
CPU time	62.1 seconds
Started	Mar 19 01:26:15 PM PDT 24
Finished	Mar 19 01:27:17 PM PDT 24
Peak memory	337080 kb
Host	smart-e4fe7ccb-6fae-4da2-95eb-7b38c27e350a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661838713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.661838713
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3841697854
Short name	T617
Test name
Test status
Simulation time	11758566403 ps
CPU time	1099.07 seconds
Started	Mar 19 01:26:25 PM PDT 24
Finished	Mar 19 01:44:45 PM PDT 24
Peak memory	367900 kb
Host	smart-0f4b23d2-edd1-4b80-a8ee-d321156c9ebe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841697854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3841697854
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.697589334
Short name	T585
Test name
Test status
Simulation time	57331292 ps
CPU time	0.66 seconds
Started	Mar 19 01:26:31 PM PDT 24
Finished	Mar 19 01:26:31 PM PDT 24
Peak memory	203060 kb
Host	smart-40017408-1a91-46b5-82a3-3760d11c3356
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697589334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.697589334
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.4033931796
Short name	T433
Test name
Test status
Simulation time	1973445281 ps
CPU time	30.84 seconds
Started	Mar 19 01:26:21 PM PDT 24
Finished	Mar 19 01:26:52 PM PDT 24
Peak memory	203248 kb
Host	smart-a3131c2a-ae83-485c-b3fd-5507ddcf3747
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033931796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .4033931796
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.2015934326
Short name	T416
Test name
Test status
Simulation time	7138686607 ps
CPU time	966.26 seconds
Started	Mar 19 01:26:25 PM PDT 24
Finished	Mar 19 01:42:32 PM PDT 24
Peak memory	370960 kb
Host	smart-5b68f841-ce3f-40fb-b121-1a603ae715b0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015934326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2015934326
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.475963273
Short name	T221
Test name
Test status
Simulation time	466122941 ps
CPU time	5.52 seconds
Started	Mar 19 01:26:25 PM PDT 24
Finished	Mar 19 01:26:32 PM PDT 24
Peak memory	203232 kb
Host	smart-9d52008f-3aa2-40b7-a52f-e5908e9c52b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475963273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc alation.475963273
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.2174330152
Short name	T776
Test name
Test status
Simulation time	493112273 ps
CPU time	18.74 seconds
Started	Mar 19 01:26:31 PM PDT 24
Finished	Mar 19 01:26:51 PM PDT 24
Peak memory	268276 kb
Host	smart-a3a2f897-b3f1-4fa0-b475-39faa40d36aa
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174330152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.2174330152
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1887766471
Short name	T619
Test name
Test status
Simulation time	157230240 ps
CPU time	2.71 seconds
Started	Mar 19 01:26:30 PM PDT 24
Finished	Mar 19 01:26:33 PM PDT 24
Peak memory	211496 kb
Host	smart-39830958-d2c3-48b5-bbab-4441e9df1c42
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887766471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.1887766471
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.1423909503
Short name	T886
Test name
Test status
Simulation time	134462228 ps
CPU time	7.78 seconds
Started	Mar 19 01:26:26 PM PDT 24
Finished	Mar 19 01:26:34 PM PDT 24
Peak memory	203244 kb
Host	smart-7f0c0823-dad8-48f5-8769-9758c26126b8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423909503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1423909503
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.1493268816
Short name	T55
Test name
Test status
Simulation time	10093602016 ps
CPU time	676.23 seconds
Started	Mar 19 01:26:21 PM PDT 24
Finished	Mar 19 01:37:37 PM PDT 24
Peak memory	373844 kb
Host	smart-2b9319ad-d6f3-4347-a382-9dfb96442554
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493268816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1493268816
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.4120501047
Short name	T786
Test name
Test status
Simulation time	4658220798 ps
CPU time	11.38 seconds
Started	Mar 19 01:26:20 PM PDT 24
Finished	Mar 19 01:26:32 PM PDT 24
Peak memory	203384 kb
Host	smart-6e3934f3-1c32-438f-a972-c99a71db975b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120501047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.4120501047
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2692055691
Short name	T144
Test name
Test status
Simulation time	30301217957 ps
CPU time	305.56 seconds
Started	Mar 19 01:26:32 PM PDT 24
Finished	Mar 19 01:31:38 PM PDT 24
Peak memory	203312 kb
Host	smart-3fc35f1b-76d3-4a47-b6ef-1598030e02e8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692055691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2692055691
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.2933945054
Short name	T411
Test name
Test status
Simulation time	96400160 ps
CPU time	0.76 seconds
Started	Mar 19 01:26:27 PM PDT 24
Finished	Mar 19 01:26:30 PM PDT 24
Peak memory	203264 kb
Host	smart-7487f464-47c2-411b-ac4a-cebef7877c60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933945054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2933945054
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.3563675128
Short name	T625
Test name
Test status
Simulation time	424705327 ps
CPU time	131.76 seconds
Started	Mar 19 01:26:26 PM PDT 24
Finished	Mar 19 01:28:38 PM PDT 24
Peak memory	358032 kb
Host	smart-f4ee9ed9-1c3f-4d24-8d91-30c57a77d5b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563675128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3563675128
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.3242197260
Short name	T364
Test name
Test status
Simulation time	1519673460 ps
CPU time	131.88 seconds
Started	Mar 19 01:26:32 PM PDT 24
Finished	Mar 19 01:28:44 PM PDT 24
Peak memory	368752 kb
Host	smart-22dec69d-a9c1-4d6e-8710-4a32be18eb55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242197260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3242197260
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.741298463
Short name	T748
Test name
Test status
Simulation time	22352508219 ps
CPU time	1056.21 seconds
Started	Mar 19 01:26:31 PM PDT 24
Finished	Mar 19 01:44:07 PM PDT 24
Peak memory	374240 kb
Host	smart-97382b91-5a50-4643-9266-e352bbed380e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741298463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_stress_all.741298463
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.7049065
Short name	T31
Test name
Test status
Simulation time	4832392748 ps
CPU time	366.97 seconds
Started	Mar 19 01:26:30 PM PDT 24
Finished	Mar 19 01:32:37 PM PDT 24
Peak memory	346924 kb
Host	smart-9fd8fd69-1d73-4b69-bbc6-390e9b2e1e5b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=7049065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.7049065
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4247813111
Short name	T921
Test name
Test status
Simulation time	1749868929 ps
CPU time	165.61 seconds
Started	Mar 19 01:26:32 PM PDT 24
Finished	Mar 19 01:29:18 PM PDT 24
Peak memory	203224 kb
Host	smart-6abd9336-35b0-44ac-92c1-2116b94ce2c0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247813111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.4247813111
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2966184051
Short name	T740
Test name
Test status
Simulation time	147130426 ps
CPU time	15.24 seconds
Started	Mar 19 01:26:21 PM PDT 24
Finished	Mar 19 01:26:36 PM PDT 24
Peak memory	258152 kb
Host	smart-a1e8b930-b667-4385-a544-f8d28928413b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966184051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2966184051
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.43253629
Short name	T891
Test name
Test status
Simulation time	3423377906 ps
CPU time	1046.77 seconds
Started	Mar 19 01:26:39 PM PDT 24
Finished	Mar 19 01:44:06 PM PDT 24
Peak memory	374092 kb
Host	smart-926e2c95-6b1d-4301-ad43-6d2f1dc04ab7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43253629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.sram_ctrl_access_during_key_req.43253629
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.205127116
Short name	T696
Test name
Test status
Simulation time	11849586 ps
CPU time	0.66 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:26:42 PM PDT 24
Peak memory	202156 kb
Host	smart-b257e3ad-9d8a-4602-9f4d-7e48569ec089
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205127116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.205127116
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.557831230
Short name	T398
Test name
Test status
Simulation time	3162724693 ps
CPU time	25.74 seconds
Started	Mar 19 01:26:39 PM PDT 24
Finished	Mar 19 01:27:05 PM PDT 24
Peak memory	203272 kb
Host	smart-4203a4cf-04ef-4f20-92c6-590082fcdfdb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557831230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 557831230
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.3884659948
Short name	T503
Test name
Test status
Simulation time	16476032255 ps
CPU time	735.32 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:38:56 PM PDT 24
Peak memory	370988 kb
Host	smart-c5a05826-6a78-4eb9-995b-a4bbebb2b55c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884659948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.3884659948
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.4058993213
Short name	T825
Test name
Test status
Simulation time	1033912846 ps
CPU time	9.32 seconds
Started	Mar 19 01:26:38 PM PDT 24
Finished	Mar 19 01:26:47 PM PDT 24
Peak memory	203264 kb
Host	smart-881514cf-738c-4741-9fc0-eb4f067281b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058993213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.4058993213
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.4118847568
Short name	T743
Test name
Test status
Simulation time	404653225 ps
CPU time	51.37 seconds
Started	Mar 19 01:26:38 PM PDT 24
Finished	Mar 19 01:27:30 PM PDT 24
Peak memory	321816 kb
Host	smart-3d13d352-a78d-4902-807e-7796057fdcca
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118847568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.4118847568
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2342241215
Short name	T575
Test name
Test status
Simulation time	313198117 ps
CPU time	4.91 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:26:46 PM PDT 24
Peak memory	211508 kb
Host	smart-69aba887-368c-4f92-822b-3c4665514127
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342241215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.2342241215
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.938189350
Short name	T167
Test name
Test status
Simulation time	1333932842 ps
CPU time	5.18 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:26:46 PM PDT 24
Peak memory	203260 kb
Host	smart-7b7e058f-eca4-42a9-83c4-10c92da84aeb
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938189350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.938189350
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.77026958
Short name	T745
Test name
Test status
Simulation time	102555084098 ps
CPU time	1831.4 seconds
Started	Mar 19 01:26:31 PM PDT 24
Finished	Mar 19 01:57:03 PM PDT 24
Peak memory	373764 kb
Host	smart-3e9eb89a-eb0c-4464-a2ad-988ace33f3a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77026958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multipl e_keys.77026958
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.3840514816
Short name	T893
Test name
Test status
Simulation time	73952619 ps
CPU time	1.76 seconds
Started	Mar 19 01:26:38 PM PDT 24
Finished	Mar 19 01:26:40 PM PDT 24
Peak memory	203208 kb
Host	smart-247c12ea-0c08-48fb-8db0-26e01bec8d67
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840514816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3840514816
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2404779187
Short name	T545
Test name
Test status
Simulation time	20132905742 ps
CPU time	252.46 seconds
Started	Mar 19 01:26:37 PM PDT 24
Finished	Mar 19 01:30:50 PM PDT 24
Peak memory	203308 kb
Host	smart-c125d406-3bfb-4078-8833-f5532d941e8d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404779187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.2404779187
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.3085324022
Short name	T325
Test name
Test status
Simulation time	47109418 ps
CPU time	0.75 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:26:42 PM PDT 24
Peak memory	203316 kb
Host	smart-31a66655-47d2-42ce-b727-a216d8069812
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085324022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3085324022
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.1262729372
Short name	T286
Test name
Test status
Simulation time	13743536056 ps
CPU time	1421.25 seconds
Started	Mar 19 01:26:40 PM PDT 24
Finished	Mar 19 01:50:22 PM PDT 24
Peak memory	374468 kb
Host	smart-1a1384e8-1623-4261-987c-ac7df9211076
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262729372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1262729372
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.4222398291
Short name	T380
Test name
Test status
Simulation time	377175028 ps
CPU time	34.49 seconds
Started	Mar 19 01:26:31 PM PDT 24
Finished	Mar 19 01:27:06 PM PDT 24
Peak memory	287928 kb
Host	smart-8adac543-f4c6-4795-bb06-d4bdc22da091
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222398291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.4222398291
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.338728677
Short name	T568
Test name
Test status
Simulation time	7097475309 ps
CPU time	2037.8 seconds
Started	Mar 19 01:26:42 PM PDT 24
Finished	Mar 19 02:00:40 PM PDT 24
Peak memory	375000 kb
Host	smart-74f95f40-3542-4ed6-bff9-a24e2c52a5d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338728677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.338728677
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1064379321
Short name	T117
Test name
Test status
Simulation time	384677166 ps
CPU time	14.52 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:26:55 PM PDT 24
Peak memory	244516 kb
Host	smart-d818930b-c34e-4548-a64e-bb3493411427
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1064379321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1064379321
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1783815386
Short name	T104
Test name
Test status
Simulation time	11136525368 ps
CPU time	311.01 seconds
Started	Mar 19 01:26:38 PM PDT 24
Finished	Mar 19 01:31:49 PM PDT 24
Peak memory	203304 kb
Host	smart-69e0a0f1-d6c5-4c18-95ba-fca7507c25eb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783815386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1783815386
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2809344690
Short name	T754
Test name
Test status
Simulation time	107110179 ps
CPU time	43.62 seconds
Started	Mar 19 01:26:37 PM PDT 24
Finished	Mar 19 01:27:21 PM PDT 24
Peak memory	293212 kb
Host	smart-85313807-11cf-4f01-9184-51fb5c982b72
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809344690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2809344690
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.4183615367
Short name	T903
Test name
Test status
Simulation time	3036574246 ps
CPU time	1624.52 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:54:22 PM PDT 24
Peak memory	372008 kb
Host	smart-a44fd791-13b0-48b6-b23e-b7d188c1ba23
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183615367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.4183615367
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.3103199617
Short name	T442
Test name
Test status
Simulation time	12188001 ps
CPU time	0.62 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:27:22 PM PDT 24
Peak memory	202076 kb
Host	smart-aadbc319-d6b0-45a6-99c5-f17101384df8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103199617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3103199617
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.3428696073
Short name	T171
Test name
Test status
Simulation time	4787922561 ps
CPU time	29.24 seconds
Started	Mar 19 01:26:50 PM PDT 24
Finished	Mar 19 01:27:46 PM PDT 24
Peak memory	203176 kb
Host	smart-1b519fa2-0880-4663-9e9f-fdd3c92abcf5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428696073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3428696073
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.1469854404
Short name	T402
Test name
Test status
Simulation time	12944674424 ps
CPU time	1111.01 seconds
Started	Mar 19 01:26:50 PM PDT 24
Finished	Mar 19 01:45:48 PM PDT 24
Peak memory	374700 kb
Host	smart-72083cad-585a-4327-83be-a8165b7fdf27
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469854404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1469854404
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.2060875273
Short name	T785
Test name
Test status
Simulation time	369311893 ps
CPU time	5.67 seconds
Started	Mar 19 01:26:46 PM PDT 24
Finished	Mar 19 01:27:22 PM PDT 24
Peak memory	203220 kb
Host	smart-428ef26d-f8e0-4a96-9aad-23467d35620a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060875273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2060875273
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.2608356396
Short name	T760
Test name
Test status
Simulation time	71729990 ps
CPU time	18 seconds
Started	Mar 19 01:26:48 PM PDT 24
Finished	Mar 19 01:27:35 PM PDT 24
Peak memory	263508 kb
Host	smart-de48ba75-1ad7-49af-a53f-dc91685169dd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608356396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2608356396
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.60120181
Short name	T258
Test name
Test status
Simulation time	395983174 ps
CPU time	3.09 seconds
Started	Mar 19 01:26:58 PM PDT 24
Finished	Mar 19 01:27:21 PM PDT 24
Peak memory	211464 kb
Host	smart-37dc4812-7001-48c8-983e-09b6563fc818
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60120181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_mem_partial_access.60120181
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.2207720351
Short name	T875
Test name
Test status
Simulation time	453763336 ps
CPU time	8.99 seconds
Started	Mar 19 01:26:55 PM PDT 24
Finished	Mar 19 01:27:26 PM PDT 24
Peak memory	203248 kb
Host	smart-c6e03b4f-ff58-4592-b860-c5ec58ae663b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207720351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2207720351
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.4147201269
Short name	T687
Test name
Test status
Simulation time	32944873291 ps
CPU time	1143.82 seconds
Started	Mar 19 01:26:41 PM PDT 24
Finished	Mar 19 01:45:45 PM PDT 24
Peak memory	366552 kb
Host	smart-87e18b06-b1e4-4a9e-906d-2c4b0f470da1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147201269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.4147201269
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.1881857330
Short name	T620
Test name
Test status
Simulation time	3905658947 ps
CPU time	123.48 seconds
Started	Mar 19 01:26:46 PM PDT 24
Finished	Mar 19 01:29:16 PM PDT 24
Peak memory	347288 kb
Host	smart-c4b2059a-c07e-4bc2-acb5-5a1a12ee1f1f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881857330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1881857330
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.527271768
Short name	T330
Test name
Test status
Simulation time	100782886936 ps
CPU time	553.83 seconds
Started	Mar 19 01:26:48 PM PDT 24
Finished	Mar 19 01:36:25 PM PDT 24
Peak memory	203280 kb
Host	smart-bed2ab57-7028-4862-8017-eb4598625464
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527271768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.sram_ctrl_partial_access_b2b.527271768
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.3567143762
Short name	T223
Test name
Test status
Simulation time	79329563 ps
CPU time	0.76 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:27:23 PM PDT 24
Peak memory	203328 kb
Host	smart-cbf67a93-9c0c-4bc0-ad65-acee27d1836e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567143762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3567143762
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.2879249928
Short name	T632
Test name
Test status
Simulation time	9607514075 ps
CPU time	463.92 seconds
Started	Mar 19 01:26:53 PM PDT 24
Finished	Mar 19 01:35:06 PM PDT 24
Peak memory	367832 kb
Host	smart-ef946aa2-88f8-4bdc-884a-2f3454cb2819
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879249928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2879249928
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.207600598
Short name	T404
Test name
Test status
Simulation time	1830958608 ps
CPU time	72.87 seconds
Started	Mar 19 01:26:49 PM PDT 24
Finished	Mar 19 01:28:25 PM PDT 24
Peak memory	321464 kb
Host	smart-0ef24faf-d451-4837-ac5b-42a71a5a5e51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207600598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.207600598
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.2431038860
Short name	T45
Test name
Test status
Simulation time	69551637369 ps
CPU time	4970.65 seconds
Started	Mar 19 01:26:50 PM PDT 24
Finished	Mar 19 02:50:08 PM PDT 24
Peak memory	376508 kb
Host	smart-839307d3-3bb0-470f-a317-959a26f93fdc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431038860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.2431038860
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1819312038
Short name	T844
Test name
Test status
Simulation time	879133754 ps
CPU time	196.67 seconds
Started	Mar 19 01:26:51 PM PDT 24
Finished	Mar 19 01:30:34 PM PDT 24
Peak memory	350704 kb
Host	smart-92699522-6788-4e81-be02-98588c9130e0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1819312038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1819312038
Directory	/workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.465097195
Short name	T298
Test name
Test status
Simulation time	17908124664 ps
CPU time	295.21 seconds
Started	Mar 19 01:26:50 PM PDT 24
Finished	Mar 19 01:32:12 PM PDT 24
Peak memory	203268 kb
Host	smart-4e5bdc68-91d9-4f1e-bcfd-f6ea39e491a6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465097195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_stress_pipeline.465097195
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2944800149
Short name	T5
Test name
Test status
Simulation time	330597621 ps
CPU time	21.33 seconds
Started	Mar 19 01:26:48 PM PDT 24
Finished	Mar 19 01:27:33 PM PDT 24
Peak memory	268552 kb
Host	smart-152f4a03-3df5-454a-adb4-a9eb8bbc5931
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944800149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2944800149
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2693409457
Short name	T729
Test name
Test status
Simulation time	9083447122 ps
CPU time	294.65 seconds
Started	Mar 19 01:27:01 PM PDT 24
Finished	Mar 19 01:32:22 PM PDT 24
Peak memory	366860 kb
Host	smart-66adde41-011a-465e-a040-f61665486c36
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693409457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2693409457
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.1561582230
Short name	T515
Test name
Test status
Simulation time	23053311 ps
CPU time	0.66 seconds
Started	Mar 19 01:27:08 PM PDT 24
Finished	Mar 19 01:27:28 PM PDT 24
Peak memory	202144 kb
Host	smart-bc0ac0ab-5c01-4594-921d-7bae362a5474
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561582230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1561582230
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.2682621979
Short name	T495
Test name
Test status
Simulation time	8137179865 ps
CPU time	62.08 seconds
Started	Mar 19 01:26:54 PM PDT 24
Finished	Mar 19 01:28:19 PM PDT 24
Peak memory	203332 kb
Host	smart-d32a51ae-0109-42fe-95ad-934d1b467e38
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682621979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .2682621979
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.3984253221
Short name	T457
Test name
Test status
Simulation time	44613940717 ps
CPU time	1517.03 seconds
Started	Mar 19 01:27:02 PM PDT 24
Finished	Mar 19 01:52:45 PM PDT 24
Peak memory	373180 kb
Host	smart-e3af8626-4ab8-43bf-8775-883beeb019ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984253221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3984253221
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3704180501
Short name	T395
Test name
Test status
Simulation time	4965926845 ps
CPU time	8.89 seconds
Started	Mar 19 01:27:03 PM PDT 24
Finished	Mar 19 01:27:37 PM PDT 24
Peak memory	203276 kb
Host	smart-c96fe904-3265-48ea-b734-126a05318970
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704180501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3704180501
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.280002289
Short name	T266
Test name
Test status
Simulation time	120047058 ps
CPU time	7.56 seconds
Started	Mar 19 01:26:56 PM PDT 24
Finished	Mar 19 01:27:35 PM PDT 24
Peak memory	239556 kb
Host	smart-6c72f887-24f6-42ac-b274-8f7d3fa0caa2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280002289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.sram_ctrl_max_throughput.280002289
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1744732673
Short name	T881
Test name
Test status
Simulation time	230460961 ps
CPU time	2.79 seconds
Started	Mar 19 01:27:06 PM PDT 24
Finished	Mar 19 01:27:31 PM PDT 24
Peak memory	211520 kb
Host	smart-2b633621-c1af-47cd-a5f4-8d92f1e83125
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744732673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.1744732673
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.3006846367
Short name	T290
Test name
Test status
Simulation time	194302844 ps
CPU time	4.4 seconds
Started	Mar 19 01:27:02 PM PDT 24
Finished	Mar 19 01:27:32 PM PDT 24
Peak memory	203292 kb
Host	smart-42a11662-b990-4c21-a05e-eed11aedb62c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006846367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3006846367
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.3194551178
Short name	T264
Test name
Test status
Simulation time	2542955466 ps
CPU time	339.24 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:32:57 PM PDT 24
Peak memory	367532 kb
Host	smart-350c6745-cfb0-4c5e-8fb4-fd467efd1619
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194551178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3194551178
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.1004661432
Short name	T488
Test name
Test status
Simulation time	119822910 ps
CPU time	31.4 seconds
Started	Mar 19 01:26:55 PM PDT 24
Finished	Mar 19 01:27:49 PM PDT 24
Peak memory	283104 kb
Host	smart-5b7c058b-e3ce-44d0-9ef5-6f46cdc419ac
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004661432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.1004661432
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2420905133
Short name	T378
Test name
Test status
Simulation time	88751757171 ps
CPU time	590.52 seconds
Started	Mar 19 01:26:56 PM PDT 24
Finished	Mar 19 01:37:18 PM PDT 24
Peak memory	203288 kb
Host	smart-7a57d748-0939-46cd-9d52-3a73e55056c7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420905133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.2420905133
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.2175044000
Short name	T661
Test name
Test status
Simulation time	72151404 ps
CPU time	0.74 seconds
Started	Mar 19 01:27:03 PM PDT 24
Finished	Mar 19 01:27:28 PM PDT 24
Peak memory	203304 kb
Host	smart-c7d666cb-7580-4662-b642-24333cfda858
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175044000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2175044000
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.3946887788
Short name	T887
Test name
Test status
Simulation time	5252500402 ps
CPU time	754.25 seconds
Started	Mar 19 01:27:01 PM PDT 24
Finished	Mar 19 01:40:02 PM PDT 24
Peak memory	372040 kb
Host	smart-271e48a2-0f3c-4fae-bfe4-0bf7f9fbe5a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946887788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3946887788
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.4120071263
Short name	T588
Test name
Test status
Simulation time	121005307 ps
CPU time	77.54 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:28:35 PM PDT 24
Peak memory	338088 kb
Host	smart-61154504-5ac6-4b3b-abcc-16d73a68e257
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120071263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4120071263
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1497302434
Short name	T798
Test name
Test status
Simulation time	9028935670 ps
CPU time	216.96 seconds
Started	Mar 19 01:26:52 PM PDT 24
Finished	Mar 19 01:30:54 PM PDT 24
Peak memory	203364 kb
Host	smart-f4ccfa46-edff-456a-9c34-8dabc5505282
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497302434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1497302434
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.646507401
Short name	T788
Test name
Test status
Simulation time	280780549 ps
CPU time	130.85 seconds
Started	Mar 19 01:26:57 PM PDT 24
Finished	Mar 19 01:29:28 PM PDT 24
Peak memory	362684 kb
Host	smart-097fc0cd-f046-4f36-94cd-6b353787c463
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646507401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.646507401
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3518055066
Short name	T82
Test name
Test status
Simulation time	3250708026 ps
CPU time	1061.81 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:39:03 PM PDT 24
Peak memory	373144 kb
Host	smart-3d32c0bc-efe8-43e2-83ba-d48b2c40f167
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518055066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3518055066
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.1725512807
Short name	T314
Test name
Test status
Simulation time	18332541 ps
CPU time	0.66 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:21:22 PM PDT 24
Peak memory	202340 kb
Host	smart-52fd39e1-bf14-437d-8cf8-2f0b7bd7b4ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725512807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1725512807
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.780748244
Short name	T910
Test name
Test status
Simulation time	808504574 ps
CPU time	50.15 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:22:09 PM PDT 24
Peak memory	203236 kb
Host	smart-5e1fe709-7730-4a79-be38-22e20469f82d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780748244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.780748244
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.2922438650
Short name	T37
Test name
Test status
Simulation time	16493709714 ps
CPU time	1584.5 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:47:44 PM PDT 24
Peak memory	357684 kb
Host	smart-7100931c-992e-4888-b88b-1e0b153cd7b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922438650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2922438650
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.1637102568
Short name	T234
Test name
Test status
Simulation time	786117382 ps
CPU time	8.64 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:31 PM PDT 24
Peak memory	203292 kb
Host	smart-da55587f-2589-4c68-8db6-30e3f5b4cd1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637102568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.1637102568
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.1873606460
Short name	T166
Test name
Test status
Simulation time	270152165 ps
CPU time	53.58 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:22:14 PM PDT 24
Peak memory	306436 kb
Host	smart-ddddf0e6-dd4b-4763-a8bc-df62f06bb7f8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873606460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1873606460
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.481038531
Short name	T618
Test name
Test status
Simulation time	734218464 ps
CPU time	5.17 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:21:26 PM PDT 24
Peak memory	211428 kb
Host	smart-c70ecabc-30f1-41a8-809d-39827131c236
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481038531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_mem_partial_access.481038531
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.3243133917
Short name	T289
Test name
Test status
Simulation time	1191257789 ps
CPU time	10.03 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:32 PM PDT 24
Peak memory	203316 kb
Host	smart-28c48675-bdd6-4d2c-b6cb-333b4c492ebf
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243133917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3243133917
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.4059803416
Short name	T185
Test name
Test status
Simulation time	3835586776 ps
CPU time	451.41 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:28:57 PM PDT 24
Peak memory	373028 kb
Host	smart-6172336f-663b-4b04-93a9-784f64390c1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059803416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.4059803416
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.1284415534
Short name	T819
Test name
Test status
Simulation time	459978800 ps
CPU time	27.95 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:21:52 PM PDT 24
Peak memory	276432 kb
Host	smart-53962852-c913-476e-9de6-562f866f248b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284415534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.1284415534
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3008040318
Short name	T706
Test name
Test status
Simulation time	15488697878 ps
CPU time	278.97 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:26:03 PM PDT 24
Peak memory	203280 kb
Host	smart-6ad5bbcf-dde3-4610-8da9-7efc0a4dc882
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008040318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3008040318
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.1221902244
Short name	T831
Test name
Test status
Simulation time	31165083 ps
CPU time	0.73 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:21:22 PM PDT 24
Peak memory	203272 kb
Host	smart-e4fc6ed0-0316-4431-acdc-0f4f11751dbb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221902244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1221902244
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.3533298635
Short name	T388
Test name
Test status
Simulation time	2227264837 ps
CPU time	470.42 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:29:10 PM PDT 24
Peak memory	343428 kb
Host	smart-2ee3a786-6458-4a9f-b2d1-727f71212617
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533298635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3533298635
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_sec_cm.4034760359
Short name	T26
Test name
Test status
Simulation time	1646573522 ps
CPU time	3.52 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:21:24 PM PDT 24
Peak memory	221928 kb
Host	smart-18190e34-cc69-462b-8dcd-acc67d09e90d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034760359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.4034760359
Directory	/workspace/4.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.3712795467
Short name	T170
Test name
Test status
Simulation time	6706294476 ps
CPU time	114.82 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:23:17 PM PDT 24
Peak memory	345164 kb
Host	smart-6760bd7f-7b08-4a11-8b44-8a6e8156dcae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712795467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3712795467
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all.512423777
Short name	T808
Test name
Test status
Simulation time	98141345757 ps
CPU time	2363.97 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 02:00:46 PM PDT 24
Peak memory	376752 kb
Host	smart-d173d766-57f8-4edf-8f40-ab304f1021d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512423777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_stress_all.512423777
Directory	/workspace/4.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.396291614
Short name	T49
Test name
Test status
Simulation time	4123375618 ps
CPU time	785.38 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:34:25 PM PDT 24
Peak memory	377288 kb
Host	smart-723c5f17-fe32-4eba-a32e-6f5190baa2cd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=396291614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.396291614
Directory	/workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2868628174
Short name	T541
Test name
Test status
Simulation time	2759523817 ps
CPU time	251.29 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:25:35 PM PDT 24
Peak memory	203284 kb
Host	smart-1d52e342-c02b-4293-82a3-21e708d683f7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868628174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2868628174
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2120364646
Short name	T200
Test name
Test status
Simulation time	599534189 ps
CPU time	105.07 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:23:06 PM PDT 24
Peak memory	368776 kb
Host	smart-280dac74-f1aa-488f-adc6-ffc633e775f7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120364646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2120364646
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.983340720
Short name	T11
Test name
Test status
Simulation time	13093735 ps
CPU time	0.63 seconds
Started	Mar 19 01:27:18 PM PDT 24
Finished	Mar 19 01:27:29 PM PDT 24
Peak memory	202120 kb
Host	smart-5cc56f31-cae0-4ebc-8e22-c28bc30b6053
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983340720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.983340720
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.2040465617
Short name	T803
Test name
Test status
Simulation time	1486192496 ps
CPU time	31.96 seconds
Started	Mar 19 01:27:06 PM PDT 24
Finished	Mar 19 01:28:00 PM PDT 24
Peak memory	203196 kb
Host	smart-c69fceb4-ecdd-45b4-966e-31c8e9746f42
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040465617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2040465617
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.3951631248
Short name	T757
Test name
Test status
Simulation time	21250004663 ps
CPU time	1783.97 seconds
Started	Mar 19 01:27:15 PM PDT 24
Finished	Mar 19 01:57:12 PM PDT 24
Peak memory	374024 kb
Host	smart-4b1661a4-6f0a-4f55-9b68-5fd468e504f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951631248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3951631248
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.35989378
Short name	T664
Test name
Test status
Simulation time	3642893365 ps
CPU time	9.4 seconds
Started	Mar 19 01:27:17 PM PDT 24
Finished	Mar 19 01:27:37 PM PDT 24
Peak memory	203292 kb
Host	smart-a42afff6-6a2c-4206-a590-d6ec910d4dae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35989378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esca lation.35989378
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.1076209791
Short name	T566
Test name
Test status
Simulation time	545459613 ps
CPU time	122.51 seconds
Started	Mar 19 01:27:13 PM PDT 24
Finished	Mar 19 01:29:30 PM PDT 24
Peak memory	363776 kb
Host	smart-5c5c2d7c-a767-4aa5-84fd-9fb90ca2595f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076209791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.1076209791
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3857420693
Short name	T779
Test name
Test status
Simulation time	610916043 ps
CPU time	5.41 seconds
Started	Mar 19 01:27:17 PM PDT 24
Finished	Mar 19 01:27:33 PM PDT 24
Peak memory	211400 kb
Host	smart-04817a8d-9ccf-4665-bf74-b308f390b05d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857420693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.3857420693
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.1119396580
Short name	T443
Test name
Test status
Simulation time	900569110 ps
CPU time	5.66 seconds
Started	Mar 19 01:27:18 PM PDT 24
Finished	Mar 19 01:27:34 PM PDT 24
Peak memory	203240 kb
Host	smart-a096d5d2-c021-47ee-9a06-e44e45a14120
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119396580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.1119396580
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_multiple_keys.3559932011
Short name	T220
Test name
Test status
Simulation time	15081257411 ps
CPU time	594.26 seconds
Started	Mar 19 01:27:08 PM PDT 24
Finished	Mar 19 01:37:22 PM PDT 24
Peak memory	373964 kb
Host	smart-67636a54-6901-4242-95c5-77ead44b521d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559932011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3559932011
Directory	/workspace/40.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.2363096820
Short name	T164
Test name
Test status
Simulation time	141972434 ps
CPU time	33.65 seconds
Started	Mar 19 01:27:16 PM PDT 24
Finished	Mar 19 01:28:02 PM PDT 24
Peak memory	299200 kb
Host	smart-2d355f99-4e48-4172-b6ec-13e16a760aa2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363096820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2363096820
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2708911923
Short name	T214
Test name
Test status
Simulation time	7265406596 ps
CPU time	209.61 seconds
Started	Mar 19 01:27:14 PM PDT 24
Finished	Mar 19 01:30:57 PM PDT 24
Peak memory	203376 kb
Host	smart-7c19bb5a-c2c7-4b34-85db-5642e018c7d9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708911923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.2708911923
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.1325421648
Short name	T584
Test name
Test status
Simulation time	42176517 ps
CPU time	0.8 seconds
Started	Mar 19 01:27:17 PM PDT 24
Finished	Mar 19 01:27:29 PM PDT 24
Peak memory	203244 kb
Host	smart-4b219549-d06f-481d-9fc7-2dc7d7954948
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325421648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1325421648
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.1691381942
Short name	T271
Test name
Test status
Simulation time	6235697234 ps
CPU time	606.7 seconds
Started	Mar 19 01:27:17 PM PDT 24
Finished	Mar 19 01:37:35 PM PDT 24
Peak memory	373780 kb
Host	smart-3f8c8505-d033-4fd1-9d55-fcaea0c5c3d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691381942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1691381942
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.1467762503
Short name	T751
Test name
Test status
Simulation time	134734377 ps
CPU time	17.05 seconds
Started	Mar 19 01:27:06 PM PDT 24
Finished	Mar 19 01:27:45 PM PDT 24
Peak memory	258924 kb
Host	smart-90499421-80b1-4336-adda-41e3cbcee653
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467762503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1467762503
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all.3954365101
Short name	T746
Test name
Test status
Simulation time	26608385628 ps
CPU time	2923.46 seconds
Started	Mar 19 01:27:18 PM PDT 24
Finished	Mar 19 02:16:12 PM PDT 24
Peak memory	383580 kb
Host	smart-bd3d4644-0640-48a8-976e-db7f851b1ac8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954365101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3954365101
Directory	/workspace/40.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1714828820
Short name	T292
Test name
Test status
Simulation time	10014778080 ps
CPU time	164.52 seconds
Started	Mar 19 01:27:18 PM PDT 24
Finished	Mar 19 01:30:12 PM PDT 24
Peak memory	374324 kb
Host	smart-5cbacae9-1ada-4432-8bfb-c4fb043f731d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1714828820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1714828820
Directory	/workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2857512248
Short name	T917
Test name
Test status
Simulation time	14657091390 ps
CPU time	294.01 seconds
Started	Mar 19 01:27:11 PM PDT 24
Finished	Mar 19 01:32:22 PM PDT 24
Peak memory	203340 kb
Host	smart-92c9280d-8424-4684-8f30-805e9cbda0ab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857512248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.2857512248
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1929385646
Short name	T671
Test name
Test status
Simulation time	51449105 ps
CPU time	2.98 seconds
Started	Mar 19 01:27:10 PM PDT 24
Finished	Mar 19 01:27:31 PM PDT 24
Peak memory	219596 kb
Host	smart-cdab2402-3e47-4498-9348-1b0a1df6dc8d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929385646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1929385646
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2541045384
Short name	T294
Test name
Test status
Simulation time	14962565603 ps
CPU time	1218.55 seconds
Started	Mar 19 01:27:22 PM PDT 24
Finished	Mar 19 01:47:47 PM PDT 24
Peak memory	374072 kb
Host	smart-a5717739-b077-4f3b-af8a-42d3197e6d5f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541045384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.2541045384
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.1807916741
Short name	T815
Test name
Test status
Simulation time	14902158 ps
CPU time	0.67 seconds
Started	Mar 19 01:27:27 PM PDT 24
Finished	Mar 19 01:27:29 PM PDT 24
Peak memory	202144 kb
Host	smart-9b986461-7a5f-40ac-b952-efa8887de93a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807916741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1807916741
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.2602267693
Short name	T598
Test name
Test status
Simulation time	2941620537 ps
CPU time	45.82 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:28:14 PM PDT 24
Peak memory	203216 kb
Host	smart-92e21546-1bf4-4282-b9d6-ccea29f9b690
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602267693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .2602267693
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.3277166855
Short name	T216
Test name
Test status
Simulation time	2673192024 ps
CPU time	1301.66 seconds
Started	Mar 19 01:27:22 PM PDT 24
Finished	Mar 19 01:49:10 PM PDT 24
Peak memory	367872 kb
Host	smart-abd5efd6-63ed-4a19-befd-cd3c435bbdde
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277166855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.3277166855
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.3108228341
Short name	T125
Test name
Test status
Simulation time	810927099 ps
CPU time	8.55 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:27:37 PM PDT 24
Peak memory	203204 kb
Host	smart-6ce45e22-da24-4893-aff1-2b4324e0d33c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108228341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3108228341
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.2480308910
Short name	T578
Test name
Test status
Simulation time	116477793 ps
CPU time	102.81 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:29:11 PM PDT 24
Peak memory	335932 kb
Host	smart-31c2aea9-5144-4f30-9f3d-c247816d50fc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480308910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.2480308910
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4080194857
Short name	T836
Test name
Test status
Simulation time	625506996 ps
CPU time	5.4 seconds
Started	Mar 19 01:27:25 PM PDT 24
Finished	Mar 19 01:27:33 PM PDT 24
Peak memory	211464 kb
Host	smart-5a8a9c7d-e854-418e-8a49-c8e9e4a36dec
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080194857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.4080194857
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.3996714952
Short name	T656
Test name
Test status
Simulation time	556025262 ps
CPU time	8.03 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:27:36 PM PDT 24
Peak memory	203136 kb
Host	smart-886ad422-832b-437d-aa56-a042e18235c0
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996714952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3996714952
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.3991730924
Short name	T376
Test name
Test status
Simulation time	1161504305 ps
CPU time	25.54 seconds
Started	Mar 19 01:27:16 PM PDT 24
Finished	Mar 19 01:27:53 PM PDT 24
Peak memory	203236 kb
Host	smart-87ed1b0b-be43-40ca-afb2-7140b2f94108
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991730924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.3991730924
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.362715053
Short name	T146
Test name
Test status
Simulation time	3752150404 ps
CPU time	81.43 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:28:49 PM PDT 24
Peak memory	331936 kb
Host	smart-b15b63e7-db5d-474f-990f-86f321780bdd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362715053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.362715053
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2190060401
Short name	T407
Test name
Test status
Simulation time	23632709906 ps
CPU time	206.99 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:30:55 PM PDT 24
Peak memory	203276 kb
Host	smart-cf6da867-81fd-4cf9-803e-d387ac2eb75f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190060401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2190060401
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.3565134908
Short name	T504
Test name
Test status
Simulation time	28956664 ps
CPU time	0.76 seconds
Started	Mar 19 01:27:20 PM PDT 24
Finished	Mar 19 01:27:29 PM PDT 24
Peak memory	203268 kb
Host	smart-e44876de-8aba-4013-ac03-83a619d8d0b0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565134908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3565134908
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.2822903218
Short name	T741
Test name
Test status
Simulation time	151807278 ps
CPU time	162.28 seconds
Started	Mar 19 01:27:17 PM PDT 24
Finished	Mar 19 01:30:10 PM PDT 24
Peak memory	368680 kb
Host	smart-1e36ec71-be2d-4639-ad47-b9fdcf3f2ee6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822903218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2822903218
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.1621384441
Short name	T524
Test name
Test status
Simulation time	28809001214 ps
CPU time	1853.05 seconds
Started	Mar 19 01:27:27 PM PDT 24
Finished	Mar 19 01:58:21 PM PDT 24
Peak memory	375124 kb
Host	smart-f894b0d6-2afd-43e6-936f-9ba47c49a374
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621384441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1621384441
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2559596507
Short name	T895
Test name
Test status
Simulation time	3218693107 ps
CPU time	266.02 seconds
Started	Mar 19 01:27:26 PM PDT 24
Finished	Mar 19 01:31:54 PM PDT 24
Peak memory	379920 kb
Host	smart-0cb95895-76b9-4b57-a5d3-a77273167970
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2559596507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2559596507
Directory	/workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1142097911
Short name	T647
Test name
Test status
Simulation time	8367199025 ps
CPU time	213.27 seconds
Started	Mar 19 01:27:20 PM PDT 24
Finished	Mar 19 01:31:01 PM PDT 24
Peak memory	203300 kb
Host	smart-a945c121-edc5-4dab-a4b1-d5d9c4811bed
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142097911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1142097911
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3412278582
Short name	T832
Test name
Test status
Simulation time	262428686 ps
CPU time	98.29 seconds
Started	Mar 19 01:27:21 PM PDT 24
Finished	Mar 19 01:29:06 PM PDT 24
Peak memory	344392 kb
Host	smart-76af8ef3-5dd8-4a6b-a82c-4aee568239b2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412278582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3412278582
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1726912691
Short name	T708
Test name
Test status
Simulation time	1518669133 ps
CPU time	457.73 seconds
Started	Mar 19 01:27:43 PM PDT 24
Finished	Mar 19 01:35:21 PM PDT 24
Peak memory	353076 kb
Host	smart-bad25a2f-945a-4505-a38d-9e381208b97d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726912691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.1726912691
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.3383789423
Short name	T122
Test name
Test status
Simulation time	12162317 ps
CPU time	0.64 seconds
Started	Mar 19 01:27:49 PM PDT 24
Finished	Mar 19 01:27:50 PM PDT 24
Peak memory	202116 kb
Host	smart-f2256c8d-504e-48ec-b5b6-40ae52b5f491
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383789423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3383789423
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.2105241020
Short name	T880
Test name
Test status
Simulation time	8232541742 ps
CPU time	32.4 seconds
Started	Mar 19 01:27:31 PM PDT 24
Finished	Mar 19 01:28:04 PM PDT 24
Peak memory	203248 kb
Host	smart-d80c2d5d-1f04-4c7f-9621-d08f5a0328bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105241020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .2105241020
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.2306926765
Short name	T796
Test name
Test status
Simulation time	6621964857 ps
CPU time	247.21 seconds
Started	Mar 19 01:27:43 PM PDT 24
Finished	Mar 19 01:31:50 PM PDT 24
Peak memory	327960 kb
Host	smart-b6197c98-c16b-4b22-adbd-bb91a693f90a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306926765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2306926765
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.2127839681
Short name	T674
Test name
Test status
Simulation time	322046817 ps
CPU time	5.09 seconds
Started	Mar 19 01:27:44 PM PDT 24
Finished	Mar 19 01:27:49 PM PDT 24
Peak memory	203112 kb
Host	smart-49d55f3c-9278-47a1-82cb-57963ae8c842
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127839681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2127839681
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.670944321
Short name	T62
Test name
Test status
Simulation time	251455430 ps
CPU time	144.91 seconds
Started	Mar 19 01:27:36 PM PDT 24
Finished	Mar 19 01:30:01 PM PDT 24
Peak memory	361716 kb
Host	smart-81d13e90-7d57-41b7-9ad6-df43749034b1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670944321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_max_throughput.670944321
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2482959551
Short name	T374
Test name
Test status
Simulation time	97302743 ps
CPU time	3.26 seconds
Started	Mar 19 01:27:48 PM PDT 24
Finished	Mar 19 01:27:51 PM PDT 24
Peak memory	211476 kb
Host	smart-975772b3-58a9-4e77-a67c-9dab0fc30e2f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482959551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.2482959551
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.3911874751
Short name	T551
Test name
Test status
Simulation time	598598381 ps
CPU time	10.49 seconds
Started	Mar 19 01:27:49 PM PDT 24
Finished	Mar 19 01:28:00 PM PDT 24
Peak memory	203240 kb
Host	smart-b4ad369a-ee0f-4bfd-a8b2-d448aa8b571f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911874751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.3911874751
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.744036616
Short name	T211
Test name
Test status
Simulation time	8403938864 ps
CPU time	781.98 seconds
Started	Mar 19 01:27:32 PM PDT 24
Finished	Mar 19 01:40:35 PM PDT 24
Peak memory	363884 kb
Host	smart-474c5393-1a4b-4b85-8b1d-d0493de2a6b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744036616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip le_keys.744036616
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.1176304234
Short name	T458
Test name
Test status
Simulation time	104306822 ps
CPU time	26.02 seconds
Started	Mar 19 01:27:32 PM PDT 24
Finished	Mar 19 01:27:58 PM PDT 24
Peak memory	271352 kb
Host	smart-4616e4ad-9fef-48c0-b966-833141df43d4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176304234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.1176304234
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3010864168
Short name	T926
Test name
Test status
Simulation time	42616504351 ps
CPU time	280.29 seconds
Started	Mar 19 01:27:34 PM PDT 24
Finished	Mar 19 01:32:14 PM PDT 24
Peak memory	203340 kb
Host	smart-e9071bf3-2e92-4872-922b-385e53abd9d3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010864168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.3010864168
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.2163609521
Short name	T268
Test name
Test status
Simulation time	80908288 ps
CPU time	0.8 seconds
Started	Mar 19 01:27:43 PM PDT 24
Finished	Mar 19 01:27:44 PM PDT 24
Peak memory	203260 kb
Host	smart-ba93cea7-982b-4d53-ab48-5964ee91ed6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163609521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2163609521
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.2860337489
Short name	T21
Test name
Test status
Simulation time	362247739 ps
CPU time	42.24 seconds
Started	Mar 19 01:27:48 PM PDT 24
Finished	Mar 19 01:28:30 PM PDT 24
Peak memory	289204 kb
Host	smart-12ebf38b-3bc6-4e3f-8963-273cb130874a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860337489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2860337489
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.1629476284
Short name	T417
Test name
Test status
Simulation time	2256370071 ps
CPU time	6.68 seconds
Started	Mar 19 01:27:32 PM PDT 24
Finished	Mar 19 01:27:38 PM PDT 24
Peak memory	203288 kb
Host	smart-2b8ec91d-16e1-417c-ad7b-94d97ae3ca33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629476284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1629476284
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.2107097996
Short name	T684
Test name
Test status
Simulation time	62186144457 ps
CPU time	6051.4 seconds
Started	Mar 19 01:27:48 PM PDT 24
Finished	Mar 19 03:08:40 PM PDT 24
Peak memory	382256 kb
Host	smart-165deef6-746c-4e06-b5e0-193f222f9646
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107097996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.2107097996
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1798199602
Short name	T252
Test name
Test status
Simulation time	2116543046 ps
CPU time	205.83 seconds
Started	Mar 19 01:27:31 PM PDT 24
Finished	Mar 19 01:30:57 PM PDT 24
Peak memory	203220 kb
Host	smart-975d6417-5467-49d3-ac38-b6d1ae39aaa1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798199602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1798199602
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3670904032
Short name	T770
Test name
Test status
Simulation time	53387337 ps
CPU time	4.3 seconds
Started	Mar 19 01:27:36 PM PDT 24
Finished	Mar 19 01:27:40 PM PDT 24
Peak memory	221144 kb
Host	smart-a68aa1f3-d26d-40e0-b00b-1786bd61492d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670904032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3670904032
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3106074821
Short name	T557
Test name
Test status
Simulation time	800561041 ps
CPU time	336.09 seconds
Started	Mar 19 01:28:01 PM PDT 24
Finished	Mar 19 01:33:37 PM PDT 24
Peak memory	371232 kb
Host	smart-f53dbb54-8de0-4e60-9f4e-543f247c5255
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106074821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3106074821
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.1730372648
Short name	T348
Test name
Test status
Simulation time	22116337 ps
CPU time	0.68 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:28:09 PM PDT 24
Peak memory	202164 kb
Host	smart-9ff93adb-7969-4d24-b82c-2a2390661448
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730372648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1730372648
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.648030454
Short name	T525
Test name
Test status
Simulation time	6959641912 ps
CPU time	29.91 seconds
Started	Mar 19 01:27:49 PM PDT 24
Finished	Mar 19 01:28:19 PM PDT 24
Peak memory	203296 kb
Host	smart-bcf07db1-26f3-4282-ab47-2a2ba25fca66
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648030454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection. 648030454
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.2174372151
Short name	T605
Test name
Test status
Simulation time	784640433 ps
CPU time	1.32 seconds
Started	Mar 19 01:28:01 PM PDT 24
Finished	Mar 19 01:28:03 PM PDT 24
Peak memory	202956 kb
Host	smart-1bd156d1-c34f-47d4-ad63-d7fe09b1b5a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174372151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2174372151
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.717645446
Short name	T436
Test name
Test status
Simulation time	928210436 ps
CPU time	112.73 seconds
Started	Mar 19 01:27:54 PM PDT 24
Finished	Mar 19 01:29:47 PM PDT 24
Peak memory	360624 kb
Host	smart-1fd0c55d-49c7-4678-a6f2-dfa7a4f55521
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717645446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.sram_ctrl_max_throughput.717645446
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1794466179
Short name	T197
Test name
Test status
Simulation time	171395436 ps
CPU time	5.31 seconds
Started	Mar 19 01:28:02 PM PDT 24
Finished	Mar 19 01:28:07 PM PDT 24
Peak memory	211492 kb
Host	smart-59f53b2f-0970-4b37-809c-edff2580f91c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794466179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1794466179
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.1080058907
Short name	T842
Test name
Test status
Simulation time	2360191032 ps
CPU time	9.81 seconds
Started	Mar 19 01:28:04 PM PDT 24
Finished	Mar 19 01:28:14 PM PDT 24
Peak memory	203328 kb
Host	smart-b286eefa-80a2-4d8f-8606-cf936028081f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080058907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.1080058907
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.393816489
Short name	T934
Test name
Test status
Simulation time	39796724805 ps
CPU time	428.97 seconds
Started	Mar 19 01:27:51 PM PDT 24
Finished	Mar 19 01:35:01 PM PDT 24
Peak memory	374752 kb
Host	smart-84d3cf53-5cf2-49c5-a159-52352d2d9a7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393816489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip le_keys.393816489
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.828864742
Short name	T612
Test name
Test status
Simulation time	223876163 ps
CPU time	11.89 seconds
Started	Mar 19 01:27:59 PM PDT 24
Finished	Mar 19 01:28:11 PM PDT 24
Peak memory	203236 kb
Host	smart-c3c78f45-3484-439c-944a-eac023136a06
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828864742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s ram_ctrl_partial_access.828864742
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3114915563
Short name	T888
Test name
Test status
Simulation time	40694600384 ps
CPU time	273.44 seconds
Started	Mar 19 01:27:56 PM PDT 24
Finished	Mar 19 01:32:29 PM PDT 24
Peak memory	203316 kb
Host	smart-cf9a661f-a465-4e32-b6ae-59aec726648b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114915563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3114915563
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.4060336944
Short name	T806
Test name
Test status
Simulation time	28633398 ps
CPU time	0.8 seconds
Started	Mar 19 01:28:02 PM PDT 24
Finished	Mar 19 01:28:03 PM PDT 24
Peak memory	203256 kb
Host	smart-9de29526-dc36-47ea-8793-b84443f7d04f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060336944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.4060336944
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.4181950755
Short name	T455
Test name
Test status
Simulation time	4263402668 ps
CPU time	332.02 seconds
Started	Mar 19 01:28:04 PM PDT 24
Finished	Mar 19 01:33:36 PM PDT 24
Peak memory	375068 kb
Host	smart-04d215f2-a6c2-4bfd-ace8-81b93f3fc7ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181950755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.4181950755
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.2411060861
Short name	T601
Test name
Test status
Simulation time	3227284897 ps
CPU time	9.52 seconds
Started	Mar 19 01:27:52 PM PDT 24
Finished	Mar 19 01:28:01 PM PDT 24
Peak memory	203200 kb
Host	smart-5eb6eeb3-f635-4b06-a227-28871aaaf071
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411060861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2411060861
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.3539495458
Short name	T461
Test name
Test status
Simulation time	43516505667 ps
CPU time	1454.72 seconds
Started	Mar 19 01:28:01 PM PDT 24
Finished	Mar 19 01:52:16 PM PDT 24
Peak memory	375600 kb
Host	smart-a7bf19d6-6204-4e4e-9a4e-59e2b601d9de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539495458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.3539495458
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.226747481
Short name	T51
Test name
Test status
Simulation time	2082491253 ps
CPU time	199.02 seconds
Started	Mar 19 01:28:00 PM PDT 24
Finished	Mar 19 01:31:19 PM PDT 24
Peak memory	377100 kb
Host	smart-af742a73-0414-475d-917a-d991e2e1ad7a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=226747481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.226747481
Directory	/workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1115828907
Short name	T421
Test name
Test status
Simulation time	1947845420 ps
CPU time	183.75 seconds
Started	Mar 19 01:27:53 PM PDT 24
Finished	Mar 19 01:30:57 PM PDT 24
Peak memory	203264 kb
Host	smart-4a958a5a-ea06-4986-b531-88bd6471bbc3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115828907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1115828907
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.570765150
Short name	T892
Test name
Test status
Simulation time	74091452 ps
CPU time	10.5 seconds
Started	Mar 19 01:27:57 PM PDT 24
Finished	Mar 19 01:28:07 PM PDT 24
Peak memory	252260 kb
Host	smart-39ab5448-bda3-484f-832f-6463fb97b545
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570765150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.570765150
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3194842487
Short name	T516
Test name
Test status
Simulation time	2762250100 ps
CPU time	1192.04 seconds
Started	Mar 19 01:28:13 PM PDT 24
Finished	Mar 19 01:48:06 PM PDT 24
Peak memory	369968 kb
Host	smart-10f731fd-67c5-4e23-b9d9-be25e586c91c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194842487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3194842487
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.573059516
Short name	T697
Test name
Test status
Simulation time	43133685 ps
CPU time	0.67 seconds
Started	Mar 19 01:28:12 PM PDT 24
Finished	Mar 19 01:28:13 PM PDT 24
Peak memory	202200 kb
Host	smart-35bf5e6d-d8ce-4fb4-b749-12016e962bed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573059516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.573059516
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.521362108
Short name	T549
Test name
Test status
Simulation time	18128720748 ps
CPU time	75.72 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:29:26 PM PDT 24
Peak memory	203208 kb
Host	smart-6987e165-d31c-424b-997f-fa1c4ff8d333
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521362108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 521362108
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.2048119440
Short name	T855
Test name
Test status
Simulation time	2096704300 ps
CPU time	366.85 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:34:17 PM PDT 24
Peak memory	369868 kb
Host	smart-9d47c984-6c7c-49f3-b818-6714de404931
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048119440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.2048119440
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.3328744915
Short name	T775
Test name
Test status
Simulation time	624839100 ps
CPU time	7 seconds
Started	Mar 19 01:28:11 PM PDT 24
Finished	Mar 19 01:28:18 PM PDT 24
Peak memory	203220 kb
Host	smart-17264da2-a358-4805-9df5-f0d190a61eaa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328744915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.3328744915
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.1394979443
Short name	T296
Test name
Test status
Simulation time	107113595 ps
CPU time	77.24 seconds
Started	Mar 19 01:28:11 PM PDT 24
Finished	Mar 19 01:29:28 PM PDT 24
Peak memory	315908 kb
Host	smart-cec32957-9023-4b63-a211-5a0956afa8f7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394979443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1394979443
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2797916760
Short name	T326
Test name
Test status
Simulation time	695247968 ps
CPU time	5.53 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:28:16 PM PDT 24
Peak memory	211592 kb
Host	smart-8302a100-09e3-486c-9f4d-df7ff16989c8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797916760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.2797916760
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.836059437
Short name	T359
Test name
Test status
Simulation time	687695387 ps
CPU time	10.37 seconds
Started	Mar 19 01:28:12 PM PDT 24
Finished	Mar 19 01:28:23 PM PDT 24
Peak memory	203312 kb
Host	smart-d10e81a9-f7fc-47cb-a741-64f10e44c071
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836059437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _mem_walk.836059437
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.1851233598
Short name	T817
Test name
Test status
Simulation time	3702983870 ps
CPU time	1259.65 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:49:09 PM PDT 24
Peak memory	375080 kb
Host	smart-c76db475-8363-4ce2-94d3-518d09ae9d5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851233598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.1851233598
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.3553333375
Short name	T319
Test name
Test status
Simulation time	305293156 ps
CPU time	16.35 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:28:26 PM PDT 24
Peak memory	203256 kb
Host	smart-9f962edf-b896-4cac-9644-fd608e4f13e0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553333375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.3553333375
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1088062579
Short name	T343
Test name
Test status
Simulation time	16519973270 ps
CPU time	242.76 seconds
Started	Mar 19 01:28:11 PM PDT 24
Finished	Mar 19 01:32:14 PM PDT 24
Peak memory	203332 kb
Host	smart-4c2d2418-b018-4505-94a3-e2e928361048
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088062579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1088062579
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.2495260388
Short name	T328
Test name
Test status
Simulation time	29804289 ps
CPU time	0.75 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:28:10 PM PDT 24
Peak memory	203300 kb
Host	smart-33719156-d95d-4fcc-8bdc-79b049b5d34f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495260388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2495260388
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.994169631
Short name	T633
Test name
Test status
Simulation time	5218455977 ps
CPU time	214.07 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:31:45 PM PDT 24
Peak memory	348364 kb
Host	smart-9cd1e2f7-9020-4d96-a38a-4022407dd829
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994169631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.994169631
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.1229980140
Short name	T657
Test name
Test status
Simulation time	38510546 ps
CPU time	1.16 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:28:10 PM PDT 24
Peak memory	203000 kb
Host	smart-6888b99d-4e20-4cf5-ba90-1e69fea589dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229980140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1229980140
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.794801252
Short name	T44
Test name
Test status
Simulation time	51923452556 ps
CPU time	2935.16 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 02:17:05 PM PDT 24
Peak memory	383204 kb
Host	smart-ef272bf0-8137-47e0-96db-a179e3556d72
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794801252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_stress_all.794801252
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3128604143
Short name	T118
Test name
Test status
Simulation time	1300620593 ps
CPU time	60.91 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:29:10 PM PDT 24
Peak memory	318520 kb
Host	smart-38d0f0b9-9683-468e-aa0c-b306be244585
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3128604143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3128604143
Directory	/workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2269420790
Short name	T864
Test name
Test status
Simulation time	2773328956 ps
CPU time	129.49 seconds
Started	Mar 19 01:28:09 PM PDT 24
Finished	Mar 19 01:30:19 PM PDT 24
Peak memory	203300 kb
Host	smart-9c2b5035-04f8-48aa-a57d-c10c58828d49
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269420790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.2269420790
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1813165392
Short name	T464
Test name
Test status
Simulation time	481190419 ps
CPU time	83.94 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:29:34 PM PDT 24
Peak memory	325900 kb
Host	smart-291ef35f-39af-457a-8fba-8a82f1959283
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813165392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1813165392
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1611781055
Short name	T39
Test name
Test status
Simulation time	4512350377 ps
CPU time	551.78 seconds
Started	Mar 19 01:28:18 PM PDT 24
Finished	Mar 19 01:37:30 PM PDT 24
Peak memory	367796 kb
Host	smart-b01e6a13-caac-412c-ba27-8c0f326ae779
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611781055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.1611781055
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.2872487366
Short name	T849
Test name
Test status
Simulation time	23872437 ps
CPU time	0.67 seconds
Started	Mar 19 01:28:24 PM PDT 24
Finished	Mar 19 01:28:25 PM PDT 24
Peak memory	203012 kb
Host	smart-9421eca8-1422-4216-b668-50c13abc136a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872487366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2872487366
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.219916322
Short name	T807
Test name
Test status
Simulation time	5813680984 ps
CPU time	62.7 seconds
Started	Mar 19 01:28:10 PM PDT 24
Finished	Mar 19 01:29:13 PM PDT 24
Peak memory	203188 kb
Host	smart-64ce8e22-8ca2-4909-886b-dd02559f85d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219916322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 219916322
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.3171106339
Short name	T254
Test name
Test status
Simulation time	55599193305 ps
CPU time	1465.42 seconds
Started	Mar 19 01:28:15 PM PDT 24
Finished	Mar 19 01:52:41 PM PDT 24
Peak memory	373692 kb
Host	smart-8a0b0c0e-320c-459a-b20a-241ef2cc8197
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171106339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3171106339
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.2057660399
Short name	T718
Test name
Test status
Simulation time	649228788 ps
CPU time	7.2 seconds
Started	Mar 19 01:28:16 PM PDT 24
Finished	Mar 19 01:28:23 PM PDT 24
Peak memory	203232 kb
Host	smart-c035eb87-17ed-4c78-9623-99e0cb0abd55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057660399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2057660399
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.4255263384
Short name	T639
Test name
Test status
Simulation time	648770725 ps
CPU time	137.34 seconds
Started	Mar 19 01:28:16 PM PDT 24
Finished	Mar 19 01:30:33 PM PDT 24
Peak memory	360456 kb
Host	smart-55b65693-486a-41ad-b267-07d9fb4c96e2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255263384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.4255263384
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3559986552
Short name	T539
Test name
Test status
Simulation time	154281011 ps
CPU time	4.87 seconds
Started	Mar 19 01:28:14 PM PDT 24
Finished	Mar 19 01:28:19 PM PDT 24
Peak memory	211496 kb
Host	smart-150913db-8ad4-4404-8d20-da0d128bf633
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559986552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3559986552
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.2229486779
Short name	T567
Test name
Test status
Simulation time	455296842 ps
CPU time	9.85 seconds
Started	Mar 19 01:28:18 PM PDT 24
Finished	Mar 19 01:28:28 PM PDT 24
Peak memory	203244 kb
Host	smart-3e3a4089-3b11-487e-8cb3-4a4ec3462695
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229486779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.2229486779
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.3502512120
Short name	T382
Test name
Test status
Simulation time	13716530589 ps
CPU time	1009.96 seconds
Started	Mar 19 01:28:08 PM PDT 24
Finished	Mar 19 01:44:59 PM PDT 24
Peak memory	370940 kb
Host	smart-52739900-e060-4190-a038-6a2055e3ede0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502512120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.3502512120
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.1943942183
Short name	T362
Test name
Test status
Simulation time	3943432148 ps
CPU time	93.71 seconds
Started	Mar 19 01:28:15 PM PDT 24
Finished	Mar 19 01:29:49 PM PDT 24
Peak memory	346644 kb
Host	smart-a74c3e6a-3bcd-4569-9e13-c3f398a364f6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943942183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1943942183
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1307001529
Short name	T205
Test name
Test status
Simulation time	6459675962 ps
CPU time	368.25 seconds
Started	Mar 19 01:28:15 PM PDT 24
Finished	Mar 19 01:34:23 PM PDT 24
Peak memory	203288 kb
Host	smart-6ffc720b-0962-484a-9178-ce7d3bbb742b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307001529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1307001529
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.3245110253
Short name	T755
Test name
Test status
Simulation time	58728228 ps
CPU time	0.84 seconds
Started	Mar 19 01:28:15 PM PDT 24
Finished	Mar 19 01:28:16 PM PDT 24
Peak memory	203256 kb
Host	smart-7ed2dcd3-92b9-44ef-8358-bca3346a2fab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245110253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3245110253
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.3581846090
Short name	T920
Test name
Test status
Simulation time	2150464722 ps
CPU time	342.24 seconds
Started	Mar 19 01:28:18 PM PDT 24
Finished	Mar 19 01:34:01 PM PDT 24
Peak memory	338996 kb
Host	smart-bf7fa9d4-9c3c-4fc5-8637-1e13c0923468
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581846090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3581846090
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.1539144708
Short name	T841
Test name
Test status
Simulation time	90035997 ps
CPU time	36.68 seconds
Started	Mar 19 01:28:12 PM PDT 24
Finished	Mar 19 01:28:50 PM PDT 24
Peak memory	292812 kb
Host	smart-c2c81498-223b-4eec-a6af-dbf4878ba125
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539144708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1539144708
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.3582670874
Short name	T737
Test name
Test status
Simulation time	175022951256 ps
CPU time	4785.81 seconds
Started	Mar 19 01:28:21 PM PDT 24
Finished	Mar 19 02:48:07 PM PDT 24
Peak memory	384164 kb
Host	smart-09657b9c-9474-4d9c-8a58-8b0f978a5936
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582670874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.3582670874
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.872257260
Short name	T916
Test name
Test status
Simulation time	4251951371 ps
CPU time	456.99 seconds
Started	Mar 19 01:28:20 PM PDT 24
Finished	Mar 19 01:35:57 PM PDT 24
Peak memory	380220 kb
Host	smart-c02f0bfc-aead-43bd-977b-d0c92e5d7250
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=872257260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.872257260
Directory	/workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.985125256
Short name	T373
Test name
Test status
Simulation time	2494548699 ps
CPU time	237.31 seconds
Started	Mar 19 01:28:14 PM PDT 24
Finished	Mar 19 01:32:11 PM PDT 24
Peak memory	203276 kb
Host	smart-57229e9a-c1a3-479e-b0b9-af1598d62d93
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985125256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .sram_ctrl_stress_pipeline.985125256
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1034579990
Short name	T712
Test name
Test status
Simulation time	109400037 ps
CPU time	46.98 seconds
Started	Mar 19 01:28:16 PM PDT 24
Finished	Mar 19 01:29:03 PM PDT 24
Peak memory	300756 kb
Host	smart-3edf3d69-05dc-4793-ae1c-7d905204e763
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034579990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1034579990
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.551650647
Short name	T521
Test name
Test status
Simulation time	1303532381 ps
CPU time	284.56 seconds
Started	Mar 19 01:28:29 PM PDT 24
Finished	Mar 19 01:33:13 PM PDT 24
Peak memory	353392 kb
Host	smart-f66d8017-f0ef-4ee2-bc64-5d478ecd6146
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551650647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sram_ctrl_access_during_key_req.551650647
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.359781194
Short name	T193
Test name
Test status
Simulation time	19453698 ps
CPU time	0.66 seconds
Started	Mar 19 01:28:35 PM PDT 24
Finished	Mar 19 01:28:36 PM PDT 24
Peak memory	202344 kb
Host	smart-28ba1afc-de5b-4a74-bdc9-b5e6e7b3105d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359781194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.359781194
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.4216896684
Short name	T694
Test name
Test status
Simulation time	439736664 ps
CPU time	28.13 seconds
Started	Mar 19 01:28:21 PM PDT 24
Finished	Mar 19 01:28:49 PM PDT 24
Peak memory	203176 kb
Host	smart-c4380418-21f1-448f-974b-444c84914b39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216896684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .4216896684
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.3474116233
Short name	T692
Test name
Test status
Simulation time	21505351365 ps
CPU time	1547.18 seconds
Started	Mar 19 01:28:30 PM PDT 24
Finished	Mar 19 01:54:17 PM PDT 24
Peak memory	371888 kb
Host	smart-e8e0b8c5-7da4-4bbf-a776-50634830b02e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474116233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3474116233
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.2586586828
Short name	T334
Test name
Test status
Simulation time	1758310687 ps
CPU time	7.51 seconds
Started	Mar 19 01:28:30 PM PDT 24
Finished	Mar 19 01:28:37 PM PDT 24
Peak memory	203108 kb
Host	smart-632452fc-92e7-4495-84f3-272e13c8a92a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586586828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.2586586828
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.695948433
Short name	T904
Test name
Test status
Simulation time	121075561 ps
CPU time	74.29 seconds
Started	Mar 19 01:28:24 PM PDT 24
Finished	Mar 19 01:29:39 PM PDT 24
Peak memory	331048 kb
Host	smart-fa703bad-0885-4227-aa6e-1b7eca0439b7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695948433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.sram_ctrl_max_throughput.695948433
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.941570046
Short name	T654
Test name
Test status
Simulation time	151218830 ps
CPU time	5.51 seconds
Started	Mar 19 01:28:29 PM PDT 24
Finished	Mar 19 01:28:35 PM PDT 24
Peak memory	211392 kb
Host	smart-1192c70e-426a-4257-91e3-b6b1396b86c9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941570046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_mem_partial_access.941570046
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.185620816
Short name	T468
Test name
Test status
Simulation time	1442960458 ps
CPU time	5.07 seconds
Started	Mar 19 01:28:28 PM PDT 24
Finished	Mar 19 01:28:33 PM PDT 24
Peak memory	203296 kb
Host	smart-5a50babe-0406-4d79-8b93-4fb87abd2e96
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185620816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.185620816
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.451152658
Short name	T283
Test name
Test status
Simulation time	13940257721 ps
CPU time	336.75 seconds
Started	Mar 19 01:28:26 PM PDT 24
Finished	Mar 19 01:34:03 PM PDT 24
Peak memory	336040 kb
Host	smart-b1ef2f21-d85c-4736-a7ec-a3a93c44714a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451152658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.451152658
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.814621236
Short name	T339
Test name
Test status
Simulation time	69689370 ps
CPU time	2.09 seconds
Started	Mar 19 01:28:24 PM PDT 24
Finished	Mar 19 01:28:27 PM PDT 24
Peak memory	205744 kb
Host	smart-e45a6f5b-189b-4941-a5a5-19f65333564c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814621236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.814621236
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3512898277
Short name	T392
Test name
Test status
Simulation time	5933979942 ps
CPU time	421.2 seconds
Started	Mar 19 01:28:23 PM PDT 24
Finished	Mar 19 01:35:25 PM PDT 24
Peak memory	203384 kb
Host	smart-0ad205a3-f5b3-4129-9ded-ae0bf20e7d8d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512898277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3512898277
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.3009367157
Short name	T327
Test name
Test status
Simulation time	47362140 ps
CPU time	0.75 seconds
Started	Mar 19 01:28:29 PM PDT 24
Finished	Mar 19 01:28:30 PM PDT 24
Peak memory	203260 kb
Host	smart-f80fc4c3-193e-4d45-97de-2d2b0a8cda8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009367157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3009367157
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.3969127143
Short name	T413
Test name
Test status
Simulation time	38322505268 ps
CPU time	1191.65 seconds
Started	Mar 19 01:28:30 PM PDT 24
Finished	Mar 19 01:48:22 PM PDT 24
Peak memory	375016 kb
Host	smart-3f0d6018-7433-4d84-b7a2-d43c7aea94c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969127143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3969127143
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.3498505072
Short name	T523
Test name
Test status
Simulation time	142260467 ps
CPU time	6.65 seconds
Started	Mar 19 01:28:25 PM PDT 24
Finished	Mar 19 01:28:32 PM PDT 24
Peak memory	203176 kb
Host	smart-c31c2fb3-05ba-4da2-b2f4-7498218a2629
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498505072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3498505072
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all.1619572777
Short name	T265
Test name
Test status
Simulation time	411699553746 ps
CPU time	4082.34 seconds
Started	Mar 19 01:28:36 PM PDT 24
Finished	Mar 19 02:36:39 PM PDT 24
Peak memory	375648 kb
Host	smart-0f405660-601b-46e0-9d25-2c4270fb3d64
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619572777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1619572777
Directory	/workspace/46.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3996349085
Short name	T930
Test name
Test status
Simulation time	14766718705 ps
CPU time	273.48 seconds
Started	Mar 19 01:28:21 PM PDT 24
Finished	Mar 19 01:32:55 PM PDT 24
Peak memory	203308 kb
Host	smart-6e045bfa-8f76-4d17-92e5-c5ad05494318
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996349085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3996349085
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3740839433
Short name	T473
Test name
Test status
Simulation time	89018956 ps
CPU time	3.24 seconds
Started	Mar 19 01:28:22 PM PDT 24
Finished	Mar 19 01:28:26 PM PDT 24
Peak memory	219560 kb
Host	smart-29658081-b1f6-4327-82b7-bb41614800f6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740839433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3740839433
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2713156438
Short name	T203
Test name
Test status
Simulation time	5767647132 ps
CPU time	272.93 seconds
Started	Mar 19 01:28:38 PM PDT 24
Finished	Mar 19 01:33:11 PM PDT 24
Peak memory	340696 kb
Host	smart-aeb435f5-fe00-4283-a468-9b44a63e6e55
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713156438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.2713156438
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.1799908561
Short name	T879
Test name
Test status
Simulation time	40398117 ps
CPU time	0.64 seconds
Started	Mar 19 01:28:44 PM PDT 24
Finished	Mar 19 01:28:44 PM PDT 24
Peak memory	203044 kb
Host	smart-0aac2b5b-c70e-4bf4-ae8f-ccfd4665802e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799908561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1799908561
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.4275800983
Short name	T883
Test name
Test status
Simulation time	498020214 ps
CPU time	25.84 seconds
Started	Mar 19 01:28:39 PM PDT 24
Finished	Mar 19 01:29:04 PM PDT 24
Peak memory	203240 kb
Host	smart-71271c03-df16-4cfb-a574-6d635df59abf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275800983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .4275800983
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.1932030944
Short name	T829
Test name
Test status
Simulation time	4641534579 ps
CPU time	45.45 seconds
Started	Mar 19 01:28:44 PM PDT 24
Finished	Mar 19 01:29:29 PM PDT 24
Peak memory	280712 kb
Host	smart-4f2d40e7-a817-4fad-8298-c97575e07968
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932030944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1932030944
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.2487973792
Short name	T615
Test name
Test status
Simulation time	740855863 ps
CPU time	5.12 seconds
Started	Mar 19 01:28:36 PM PDT 24
Finished	Mar 19 01:28:41 PM PDT 24
Peak memory	203180 kb
Host	smart-46010fae-5c55-4918-a1c6-c889afaa036f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487973792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.2487973792
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.305390780
Short name	T845
Test name
Test status
Simulation time	302897753 ps
CPU time	25.1 seconds
Started	Mar 19 01:28:38 PM PDT 24
Finished	Mar 19 01:29:03 PM PDT 24
Peak memory	277008 kb
Host	smart-af432739-9582-40e3-8997-abce864d1699
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305390780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.sram_ctrl_max_throughput.305390780
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3275723827
Short name	T491
Test name
Test status
Simulation time	158338063 ps
CPU time	5.73 seconds
Started	Mar 19 01:28:42 PM PDT 24
Finished	Mar 19 01:28:48 PM PDT 24
Peak memory	211440 kb
Host	smart-f4b435e7-a62d-47cd-b7b0-b5982e200d22
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275723827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.3275723827
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.3123238090
Short name	T637
Test name
Test status
Simulation time	89544498 ps
CPU time	4.49 seconds
Started	Mar 19 01:28:43 PM PDT 24
Finished	Mar 19 01:28:48 PM PDT 24
Peak memory	203204 kb
Host	smart-3850d0cf-3fda-4323-adf6-24f705bdb6ec
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123238090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.3123238090
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.1794900184
Short name	T583
Test name
Test status
Simulation time	1298202049 ps
CPU time	86.06 seconds
Started	Mar 19 01:28:37 PM PDT 24
Finished	Mar 19 01:30:03 PM PDT 24
Peak memory	304712 kb
Host	smart-cd608567-c4a4-46fc-abc9-ff994a7d40f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794900184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1794900184
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.2100187906
Short name	T204
Test name
Test status
Simulation time	5414790763 ps
CPU time	111.31 seconds
Started	Mar 19 01:28:38 PM PDT 24
Finished	Mar 19 01:30:30 PM PDT 24
Peak memory	365548 kb
Host	smart-a903d54b-c2b7-4025-b73d-a6b6108a6c98
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100187906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2100187906
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1705857566
Short name	T482
Test name
Test status
Simulation time	99075562476 ps
CPU time	213.02 seconds
Started	Mar 19 01:28:38 PM PDT 24
Finished	Mar 19 01:32:11 PM PDT 24
Peak memory	203312 kb
Host	smart-5869ed3b-aa65-4d72-92aa-ceb256688863
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705857566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1705857566
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.2293540615
Short name	T611
Test name
Test status
Simulation time	145893541 ps
CPU time	0.78 seconds
Started	Mar 19 01:28:41 PM PDT 24
Finished	Mar 19 01:28:42 PM PDT 24
Peak memory	203344 kb
Host	smart-751a4ad4-c61e-4248-bac8-02d7f3aeeff0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293540615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2293540615
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.4106198783
Short name	T456
Test name
Test status
Simulation time	8353214548 ps
CPU time	794.53 seconds
Started	Mar 19 01:28:45 PM PDT 24
Finished	Mar 19 01:41:59 PM PDT 24
Peak memory	374884 kb
Host	smart-a2339b11-871e-4aac-9017-2d2848b59d47
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106198783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.4106198783
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.1589371855
Short name	T332
Test name
Test status
Simulation time	1488745161 ps
CPU time	33.79 seconds
Started	Mar 19 01:28:39 PM PDT 24
Finished	Mar 19 01:29:12 PM PDT 24
Peak memory	289296 kb
Host	smart-edb06195-1b2d-48b6-a5b6-d0c434ee46a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589371855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1589371855
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.175120321
Short name	T128
Test name
Test status
Simulation time	15763884926 ps
CPU time	1441.48 seconds
Started	Mar 19 01:28:43 PM PDT 24
Finished	Mar 19 01:52:44 PM PDT 24
Peak memory	370052 kb
Host	smart-206e472b-d47c-4311-9cfa-82e5c7868639
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175120321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.175120321
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1568623974
Short name	T635
Test name
Test status
Simulation time	2438604131 ps
CPU time	841.85 seconds
Started	Mar 19 01:28:42 PM PDT 24
Finished	Mar 19 01:42:44 PM PDT 24
Peak memory	377164 kb
Host	smart-d9d8aba2-75de-413b-b59f-879f355d04b0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1568623974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1568623974
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2078447424
Short name	T711
Test name
Test status
Simulation time	16397406716 ps
CPU time	223.82 seconds
Started	Mar 19 01:28:39 PM PDT 24
Finished	Mar 19 01:32:23 PM PDT 24
Peak memory	203224 kb
Host	smart-8b109e62-bee6-4dbf-af33-60b06b0c8f2d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078447424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2078447424
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.781108337
Short name	T249
Test name
Test status
Simulation time	284343970 ps
CPU time	106.78 seconds
Started	Mar 19 01:28:39 PM PDT 24
Finished	Mar 19 01:30:26 PM PDT 24
Peak memory	347468 kb
Host	smart-eede23a6-c341-44d5-a0dd-f44f5881f352
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781108337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.781108337
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1725744431
Short name	T563
Test name
Test status
Simulation time	1975988155 ps
CPU time	125.37 seconds
Started	Mar 19 01:28:49 PM PDT 24
Finished	Mar 19 01:30:55 PM PDT 24
Peak memory	300376 kb
Host	smart-e8912d6e-d8dd-4f7e-8876-766f4532ceec
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725744431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1725744431
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.3541515371
Short name	T777
Test name
Test status
Simulation time	26762053 ps
CPU time	0.65 seconds
Started	Mar 19 01:28:55 PM PDT 24
Finished	Mar 19 01:28:55 PM PDT 24
Peak memory	202108 kb
Host	smart-ed890bb8-feb7-415e-b607-79e2319f8b66
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541515371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3541515371
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.128422025
Short name	T884
Test name
Test status
Simulation time	4608244723 ps
CPU time	70.36 seconds
Started	Mar 19 01:28:50 PM PDT 24
Finished	Mar 19 01:30:01 PM PDT 24
Peak memory	203284 kb
Host	smart-b127ff1a-06b6-4d72-99de-69343b48f9fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128422025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection. 128422025
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.2173214488
Short name	T360
Test name
Test status
Simulation time	1333708251 ps
CPU time	751.07 seconds
Started	Mar 19 01:28:49 PM PDT 24
Finished	Mar 19 01:41:20 PM PDT 24
Peak memory	373852 kb
Host	smart-fdee3cf1-26bb-41b0-ba24-5667180b8329
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173214488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2173214488
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.1913673790
Short name	T207
Test name
Test status
Simulation time	1099366803 ps
CPU time	7.67 seconds
Started	Mar 19 01:28:51 PM PDT 24
Finished	Mar 19 01:28:58 PM PDT 24
Peak memory	203224 kb
Host	smart-f3ab116b-d846-4e14-8604-344d211f93a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913673790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.1913673790
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.3650838190
Short name	T869
Test name
Test status
Simulation time	143580697 ps
CPU time	33.51 seconds
Started	Mar 19 01:28:48 PM PDT 24
Finished	Mar 19 01:29:22 PM PDT 24
Peak memory	285028 kb
Host	smart-74f6dcdd-ad00-4a24-b351-3de33663e7de
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650838190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3650838190
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1607434673
Short name	T780
Test name
Test status
Simulation time	1304677237 ps
CPU time	5.46 seconds
Started	Mar 19 01:28:55 PM PDT 24
Finished	Mar 19 01:29:01 PM PDT 24
Peak memory	211424 kb
Host	smart-d0b6029e-5967-43c1-9a36-ce039c53c906
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607434673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.1607434673
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.178293541
Short name	T318
Test name
Test status
Simulation time	349905112 ps
CPU time	4.27 seconds
Started	Mar 19 01:28:56 PM PDT 24
Finished	Mar 19 01:29:01 PM PDT 24
Peak memory	203256 kb
Host	smart-8aa4138a-6266-41d6-829c-63a976828265
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178293541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.178293541
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.317395286
Short name	T506
Test name
Test status
Simulation time	17039378461 ps
CPU time	1046.83 seconds
Started	Mar 19 01:28:43 PM PDT 24
Finished	Mar 19 01:46:10 PM PDT 24
Peak memory	375984 kb
Host	smart-dc59d5b7-bb1b-4fe1-8b9d-0baa0e84b340
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317395286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.317395286
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.2748245049
Short name	T191
Test name
Test status
Simulation time	51004563 ps
CPU time	1.02 seconds
Started	Mar 19 01:28:50 PM PDT 24
Finished	Mar 19 01:28:51 PM PDT 24
Peak memory	203028 kb
Host	smart-5c83af2c-8e29-4738-8f19-961cfd9935da
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748245049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.2748245049
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.65419319
Short name	T201
Test name
Test status
Simulation time	21952247271 ps
CPU time	369.06 seconds
Started	Mar 19 01:28:48 PM PDT 24
Finished	Mar 19 01:34:57 PM PDT 24
Peak memory	203308 kb
Host	smart-884b6e4b-0255-4a1a-b851-6c29a0601611
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65419319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_partial_access_b2b.65419319
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.2517777212
Short name	T438
Test name
Test status
Simulation time	155575028 ps
CPU time	0.77 seconds
Started	Mar 19 01:28:56 PM PDT 24
Finished	Mar 19 01:28:57 PM PDT 24
Peak memory	203276 kb
Host	smart-85c6bde6-7adf-481b-a439-5cb3a1f1bb49
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517777212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2517777212
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.297441074
Short name	T358
Test name
Test status
Simulation time	4130640485 ps
CPU time	1926.77 seconds
Started	Mar 19 01:28:49 PM PDT 24
Finished	Mar 19 02:00:56 PM PDT 24
Peak memory	374892 kb
Host	smart-c5ed4be4-b823-430f-b408-940b9d032f4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297441074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.297441074
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.2994830262
Short name	T793
Test name
Test status
Simulation time	983101346 ps
CPU time	10.73 seconds
Started	Mar 19 01:28:42 PM PDT 24
Finished	Mar 19 01:28:53 PM PDT 24
Peak memory	240520 kb
Host	smart-415f007b-0806-488c-ad2b-5d47684da1cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994830262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2994830262
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.4092486898
Short name	T301
Test name
Test status
Simulation time	32819515826 ps
CPU time	3101.19 seconds
Started	Mar 19 01:28:55 PM PDT 24
Finished	Mar 19 02:20:37 PM PDT 24
Peak memory	375128 kb
Host	smart-01b74b0d-d75f-4149-8fcf-d589d3da07d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092486898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.4092486898
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2997286893
Short name	T114
Test name
Test status
Simulation time	210945273 ps
CPU time	6.71 seconds
Started	Mar 19 01:28:57 PM PDT 24
Finished	Mar 19 01:29:04 PM PDT 24
Peak memory	211560 kb
Host	smart-3de85d72-11c9-499d-a5e4-303968fdcf6f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2997286893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2997286893
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1522869599
Short name	T768
Test name
Test status
Simulation time	9875136514 ps
CPU time	213.5 seconds
Started	Mar 19 01:28:49 PM PDT 24
Finished	Mar 19 01:32:22 PM PDT 24
Peak memory	203336 kb
Host	smart-75a4f765-5d9f-4411-9ea5-e72f3a0f470d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522869599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1522869599
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1819270521
Short name	T152
Test name
Test status
Simulation time	328404165 ps
CPU time	28.58 seconds
Started	Mar 19 01:28:49 PM PDT 24
Finished	Mar 19 01:29:18 PM PDT 24
Peak memory	291236 kb
Host	smart-a11db6ba-eabd-466b-a8f3-595448647b33
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819270521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1819270521
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.342563557
Short name	T695
Test name
Test status
Simulation time	1885766361 ps
CPU time	712.55 seconds
Started	Mar 19 01:29:01 PM PDT 24
Finished	Mar 19 01:40:54 PM PDT 24
Peak memory	374016 kb
Host	smart-20c3647a-19d4-49c5-8134-d6ea9a106c3b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342563557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_access_during_key_req.342563557
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.2753749356
Short name	T492
Test name
Test status
Simulation time	47540676 ps
CPU time	0.67 seconds
Started	Mar 19 01:29:09 PM PDT 24
Finished	Mar 19 01:29:10 PM PDT 24
Peak memory	202144 kb
Host	smart-e24837ab-344b-4f7e-895d-ecc5eb8a0a12
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753749356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2753749356
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.749477463
Short name	T397
Test name
Test status
Simulation time	474900911 ps
CPU time	24.5 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:29:26 PM PDT 24
Peak memory	203200 kb
Host	smart-9e47e810-0e43-4c77-8b4e-02228ed9f366
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749477463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 749477463
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.4114029073
Short name	T613
Test name
Test status
Simulation time	3942636420 ps
CPU time	1768.49 seconds
Started	Mar 19 01:29:03 PM PDT 24
Finished	Mar 19 01:58:32 PM PDT 24
Peak memory	374968 kb
Host	smart-8e804d39-1773-4d9f-b55e-af340a4ac629
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114029073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.4114029073
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.1147725363
Short name	T147
Test name
Test status
Simulation time	1107448962 ps
CPU time	4.58 seconds
Started	Mar 19 01:29:03 PM PDT 24
Finished	Mar 19 01:29:07 PM PDT 24
Peak memory	203084 kb
Host	smart-ce9828dd-a1eb-485d-86c6-18fc00c887ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147725363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1147725363
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.1697485815
Short name	T391
Test name
Test status
Simulation time	69341381 ps
CPU time	9.38 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:29:11 PM PDT 24
Peak memory	251312 kb
Host	smart-4a28d185-8976-49ed-8081-a0cf13bb5ef2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697485815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1697485815
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2478670607
Short name	T774
Test name
Test status
Simulation time	581835740 ps
CPU time	5.12 seconds
Started	Mar 19 01:29:03 PM PDT 24
Finished	Mar 19 01:29:08 PM PDT 24
Peak memory	211532 kb
Host	smart-0fc82d7b-4cee-425b-ba1b-f1b39efb6efc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478670607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2478670607
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.3893653423
Short name	T602
Test name
Test status
Simulation time	75305207 ps
CPU time	4.32 seconds
Started	Mar 19 01:29:01 PM PDT 24
Finished	Mar 19 01:29:06 PM PDT 24
Peak memory	203240 kb
Host	smart-e51b9772-ef7e-4541-97a3-bcd602a9c3fc
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893653423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3893653423
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.4037769335
Short name	T907
Test name
Test status
Simulation time	53332564336 ps
CPU time	837.09 seconds
Started	Mar 19 01:28:55 PM PDT 24
Finished	Mar 19 01:42:53 PM PDT 24
Peak memory	374876 kb
Host	smart-05939a72-3a63-4946-8ac4-afb74f0fe0d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037769335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.4037769335
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.2410200007
Short name	T474
Test name
Test status
Simulation time	258710766 ps
CPU time	30.38 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:29:32 PM PDT 24
Peak memory	281740 kb
Host	smart-4dfe6679-7b11-46ae-becb-b12a57fc75a7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410200007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2410200007
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3849750481
Short name	T430
Test name
Test status
Simulation time	2934429109 ps
CPU time	205.88 seconds
Started	Mar 19 01:29:01 PM PDT 24
Finished	Mar 19 01:32:27 PM PDT 24
Peak memory	203348 kb
Host	smart-f7b63ad9-ae38-4ccc-9eb9-ced11b970e10
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849750481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3849750481
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.3446245843
Short name	T905
Test name
Test status
Simulation time	119011458 ps
CPU time	0.75 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:29:03 PM PDT 24
Peak memory	203308 kb
Host	smart-66ccc991-c94f-48db-9659-917e68c54139
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446245843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3446245843
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.3448529370
Short name	T483
Test name
Test status
Simulation time	65367281334 ps
CPU time	1269.88 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:50:12 PM PDT 24
Peak memory	364000 kb
Host	smart-2f54385d-dbd5-4a7a-bb1b-ad63d6476c91
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448529370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3448529370
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.3528816677
Short name	T675
Test name
Test status
Simulation time	147745723 ps
CPU time	20.1 seconds
Started	Mar 19 01:28:55 PM PDT 24
Finished	Mar 19 01:29:15 PM PDT 24
Peak memory	270524 kb
Host	smart-10547bcb-8120-4668-80a5-88dce87f5a33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528816677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3528816677
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all.3902744116
Short name	T424
Test name
Test status
Simulation time	234163485105 ps
CPU time	3257.6 seconds
Started	Mar 19 01:29:01 PM PDT 24
Finished	Mar 19 02:23:19 PM PDT 24
Peak memory	383292 kb
Host	smart-c4cd6afe-0b68-4fc7-a2fc-44b084fea716
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902744116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.3902744116
Directory	/workspace/49.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.502533171
Short name	T30
Test name
Test status
Simulation time	1468656432 ps
CPU time	649.4 seconds
Started	Mar 19 01:29:01 PM PDT 24
Finished	Mar 19 01:39:50 PM PDT 24
Peak memory	374952 kb
Host	smart-8ca689fc-0b43-46f9-8885-8b66d234ebf6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=502533171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.502533171
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3777012961
Short name	T450
Test name
Test status
Simulation time	5161279167 ps
CPU time	240.15 seconds
Started	Mar 19 01:29:00 PM PDT 24
Finished	Mar 19 01:33:01 PM PDT 24
Peak memory	203344 kb
Host	smart-9d6a0fed-e67e-4799-9c9a-0caf0bdea27c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777012961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3777012961
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1153652522
Short name	T790
Test name
Test status
Simulation time	38193128 ps
CPU time	1.38 seconds
Started	Mar 19 01:29:02 PM PDT 24
Finished	Mar 19 01:29:04 PM PDT 24
Peak memory	211428 kb
Host	smart-f1a920ef-edcc-40c4-8ce2-b427ebd28ead
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153652522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1153652522
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1466114634
Short name	T935
Test name
Test status
Simulation time	1965465055 ps
CPU time	848.57 seconds
Started	Mar 19 01:21:19 PM PDT 24
Finished	Mar 19 01:35:27 PM PDT 24
Peak memory	372944 kb
Host	smart-a1a4b3c9-bcb1-439e-95ef-2591897c62fe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466114634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.1466114634
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.3020608951
Short name	T769
Test name
Test status
Simulation time	13255276 ps
CPU time	0.64 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	202120 kb
Host	smart-f85301db-1da6-4ba7-b055-93f93e71158c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020608951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3020608951
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.3326392173
Short name	T281
Test name
Test status
Simulation time	13392610211 ps
CPU time	34.39 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:21:57 PM PDT 24
Peak memory	203208 kb
Host	smart-5c2069a6-f8c6-43e5-87e3-33c122264735
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326392173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3326392173
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.88260747
Short name	T763
Test name
Test status
Simulation time	10863458394 ps
CPU time	1021.35 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:38:25 PM PDT 24
Peak memory	373928 kb
Host	smart-aa22bcc3-7c49-47d5-8c37-de801cced6dd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88260747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.88260747
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2144278416
Short name	T439
Test name
Test status
Simulation time	247810568 ps
CPU time	3.01 seconds
Started	Mar 19 01:21:20 PM PDT 24
Finished	Mar 19 01:21:23 PM PDT 24
Peak memory	203264 kb
Host	smart-6137e35e-e9db-4782-ad89-7da43db6d173
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144278416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.2144278416
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.3147779706
Short name	T470
Test name
Test status
Simulation time	1584423012 ps
CPU time	173.88 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:24:17 PM PDT 24
Peak memory	369832 kb
Host	smart-59294a90-1e89-4c49-ad6b-7ef0eb6a1954
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147779706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.3147779706
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.190365229
Short name	T594
Test name
Test status
Simulation time	64079360 ps
CPU time	4.2 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:21:32 PM PDT 24
Peak memory	211508 kb
Host	smart-cd02b4fd-bf29-4d4b-8cc3-d591f9411658
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190365229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_mem_partial_access.190365229
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.272266210
Short name	T702
Test name
Test status
Simulation time	1396896537 ps
CPU time	5.62 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:31 PM PDT 24
Peak memory	203296 kb
Host	smart-dfb9140d-2b93-48d5-85e6-e35b2703f25b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272266210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.272266210
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.649530089
Short name	T418
Test name
Test status
Simulation time	54354340003 ps
CPU time	766.36 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:34:10 PM PDT 24
Peak memory	352492 kb
Host	smart-feaf1b93-8f1e-47c2-bc14-4979994b690b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649530089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.649530089
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.31034639
Short name	T20
Test name
Test status
Simulation time	587069849 ps
CPU time	10.69 seconds
Started	Mar 19 01:21:21 PM PDT 24
Finished	Mar 19 01:21:32 PM PDT 24
Peak memory	203216 kb
Host	smart-15785494-9be6-4ef4-8c4d-f082f95e2f42
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sra m_ctrl_partial_access.31034639
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1845423314
Short name	T278
Test name
Test status
Simulation time	21046202837 ps
CPU time	391 seconds
Started	Mar 19 01:21:22 PM PDT 24
Finished	Mar 19 01:27:53 PM PDT 24
Peak memory	203324 kb
Host	smart-668e6cf9-977f-4c92-a9d0-4eafbf591305
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845423314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1845423314
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.2887438406
Short name	T465
Test name
Test status
Simulation time	28331103 ps
CPU time	0.79 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	203216 kb
Host	smart-21f5772c-c36b-4354-b16a-c30c47fa0c78
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887438406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2887438406
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.2486967989
Short name	T623
Test name
Test status
Simulation time	99136381535 ps
CPU time	1375.51 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:44:23 PM PDT 24
Peak memory	374348 kb
Host	smart-899b32b1-6b1c-4e53-835c-864c4d208750
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486967989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2486967989
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.247807336
Short name	T490
Test name
Test status
Simulation time	541776709 ps
CPU time	58.42 seconds
Started	Mar 19 01:21:23 PM PDT 24
Finished	Mar 19 01:22:22 PM PDT 24
Peak memory	318412 kb
Host	smart-e3126b81-0c41-4baa-82aa-6ad7090487c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247807336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.247807336
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.712245950
Short name	T822
Test name
Test status
Simulation time	33533780531 ps
CPU time	1329.79 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:43:38 PM PDT 24
Peak memory	375980 kb
Host	smart-9ca32595-558e-494e-89c7-ccc2152ec2e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712245950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_stress_all.712245950
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3243500000
Short name	T115
Test name
Test status
Simulation time	600854989 ps
CPU time	56.54 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:22:25 PM PDT 24
Peak memory	298536 kb
Host	smart-ccd418ce-c496-4b81-a44d-7405f4714c17
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3243500000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3243500000
Directory	/workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2442310412
Short name	T124
Test name
Test status
Simulation time	10189112781 ps
CPU time	253.81 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:25:38 PM PDT 24
Peak memory	203328 kb
Host	smart-fac47e9f-5ba6-4cd9-ae28-e79b869bde19
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442310412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2442310412
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3566189405
Short name	T673
Test name
Test status
Simulation time	603856464 ps
CPU time	85.02 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:22:51 PM PDT 24
Peak memory	323768 kb
Host	smart-9c3331d4-9f9c-488c-871e-f62275122f91
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566189405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3566189405
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3829346379
Short name	T245
Test name
Test status
Simulation time	460163949 ps
CPU time	96.03 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:23:00 PM PDT 24
Peak memory	321508 kb
Host	smart-b9868351-9891-45dd-8c49-f1817795a5f8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829346379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.3829346379
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.272874682
Short name	T690
Test name
Test status
Simulation time	44311682 ps
CPU time	0.63 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:26 PM PDT 24
Peak memory	202308 kb
Host	smart-bd1dea4c-cc03-4e95-a29a-7dd8a4e344eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272874682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.272874682
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.4054583693
Short name	T248
Test name
Test status
Simulation time	5127793581 ps
CPU time	59.53 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:22:25 PM PDT 24
Peak memory	203216 kb
Host	smart-52f94f9c-fbd4-4f2f-8e90-08da6aa08433
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054583693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 4054583693
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.2278220773
Short name	T38
Test name
Test status
Simulation time	3197468808 ps
CPU time	1116.31 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:40:01 PM PDT 24
Peak memory	368444 kb
Host	smart-3b2d3393-6e2c-49ab-8b59-d391a7faaebf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278220773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.2278220773
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2404021385
Short name	T642
Test name
Test status
Simulation time	366566388 ps
CPU time	3.7 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	203220 kb
Host	smart-20d8dab3-0407-4fc3-8f05-91eb31041943
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404021385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.2404021385
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.3653181170
Short name	T262
Test name
Test status
Simulation time	43410433 ps
CPU time	2.49 seconds
Started	Mar 19 01:21:29 PM PDT 24
Finished	Mar 19 01:21:31 PM PDT 24
Peak memory	216672 kb
Host	smart-0856f5f5-4a54-43a5-8356-a7351c6736ea
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653181170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.3653181170
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.767310405
Short name	T361
Test name
Test status
Simulation time	47033899 ps
CPU time	2.81 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	211464 kb
Host	smart-3091e4cf-cc0e-4b12-a824-b0a06b3f5e78
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767310405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_mem_partial_access.767310405
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.2210497677
Short name	T558
Test name
Test status
Simulation time	266793331 ps
CPU time	8.06 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:21:36 PM PDT 24
Peak memory	203232 kb
Host	smart-b4f6d558-7130-4b99-b94a-e6f0ff5e6690
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210497677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2210497677
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.823336976
Short name	T610
Test name
Test status
Simulation time	4937791641 ps
CPU time	994.97 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:38:01 PM PDT 24
Peak memory	371940 kb
Host	smart-d48cda98-6584-463c-aa0b-206e73999abd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823336976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl e_keys.823336976
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.2062685553
Short name	T172
Test name
Test status
Simulation time	111711328 ps
CPU time	5.28 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:21:34 PM PDT 24
Peak memory	224204 kb
Host	smart-38c349ac-2766-4f54-9fec-7104da1b3013
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062685553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2062685553
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1085949475
Short name	T487
Test name
Test status
Simulation time	15599973226 ps
CPU time	388.49 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:27:53 PM PDT 24
Peak memory	203312 kb
Host	smart-e932aa7f-e7aa-4cd0-b71a-fabd87c5d571
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085949475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.1085949475
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.2430525698
Short name	T159
Test name
Test status
Simulation time	42875113 ps
CPU time	0.82 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 01:21:28 PM PDT 24
Peak memory	203256 kb
Host	smart-14119a9b-daf3-4c5b-9a47-42af4e8411e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430525698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2430525698
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.2445612550
Short name	T429
Test name
Test status
Simulation time	42991828420 ps
CPU time	678.96 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:32:43 PM PDT 24
Peak memory	375116 kb
Host	smart-08be8cbd-2d71-4e60-958c-8b93b045f4c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445612550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2445612550
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.3478331229
Short name	T931
Test name
Test status
Simulation time	1294759836 ps
CPU time	152.39 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:24:01 PM PDT 24
Peak memory	367652 kb
Host	smart-a4368f79-201e-4f5b-b576-7a5b71275e0a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478331229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3478331229
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.1622895687
Short name	T668
Test name
Test status
Simulation time	49923241772 ps
CPU time	3262.71 seconds
Started	Mar 19 01:21:27 PM PDT 24
Finished	Mar 19 02:15:50 PM PDT 24
Peak memory	376208 kb
Host	smart-c81c1982-29d3-4310-ad9f-86b64511f414
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622895687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1622895687
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3692032333
Short name	T437
Test name
Test status
Simulation time	3872320036 ps
CPU time	220.42 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:25:08 PM PDT 24
Peak memory	203304 kb
Host	smart-4472f261-2f0d-498d-8707-39103aab96ba
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692032333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3692032333
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.574650087
Short name	T727
Test name
Test status
Simulation time	1473069728 ps
CPU time	113.6 seconds
Started	Mar 19 01:21:24 PM PDT 24
Finished	Mar 19 01:23:18 PM PDT 24
Peak memory	353328 kb
Host	smart-c2d6c43d-cf56-4a1e-8c36-354f7231d42e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574650087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.574650087
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3219389902
Short name	T449
Test name
Test status
Simulation time	1095341021 ps
CPU time	420.78 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:28:27 PM PDT 24
Peak memory	368276 kb
Host	smart-4b0ddd24-2387-44ff-b341-df7b1d56aab2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219389902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.3219389902
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.641903239
Short name	T469
Test name
Test status
Simulation time	33872221 ps
CPU time	0.63 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:21:31 PM PDT 24
Peak memory	202200 kb
Host	smart-513d758e-c2d3-4dfd-a5e6-a6bf80e93302
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641903239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.641903239
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.3015990276
Short name	T595
Test name
Test status
Simulation time	9521189115 ps
CPU time	72.67 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:22:39 PM PDT 24
Peak memory	203204 kb
Host	smart-6ab1d331-a643-4d5e-b4bc-fad61675f520
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015990276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 3015990276
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.2678583116
Short name	T580
Test name
Test status
Simulation time	6489496340 ps
CPU time	343.15 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:27:11 PM PDT 24
Peak memory	365820 kb
Host	smart-6a94be3e-fd3a-499f-883e-e4d519625490
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678583116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2678583116
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.731090603
Short name	T658
Test name
Test status
Simulation time	584266009 ps
CPU time	6.8 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:32 PM PDT 24
Peak memory	203232 kb
Host	smart-750bab51-d8a4-447c-b686-19d357bb9c73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731090603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.731090603
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.971452513
Short name	T867
Test name
Test status
Simulation time	280972853 ps
CPU time	66.05 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:22:34 PM PDT 24
Peak memory	330924 kb
Host	smart-f83464e6-a6a2-4bce-84d5-8a339ced2173
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971452513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_max_throughput.971452513
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3733819330
Short name	T577
Test name
Test status
Simulation time	173880887 ps
CPU time	5.43 seconds
Started	Mar 19 01:21:28 PM PDT 24
Finished	Mar 19 01:21:34 PM PDT 24
Peak memory	211400 kb
Host	smart-9c62dec5-5272-4050-9b34-7ffb19993691
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733819330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.3733819330
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.1333220660
Short name	T340
Test name
Test status
Simulation time	5614886085 ps
CPU time	12.54 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:21:39 PM PDT 24
Peak memory	203312 kb
Host	smart-fe160dd3-9d8c-497b-ac97-6f6e7ee3fd57
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333220660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.1333220660
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.1073101015
Short name	T309
Test name
Test status
Simulation time	3023164384 ps
CPU time	1057.13 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:39:04 PM PDT 24
Peak memory	364872 kb
Host	smart-fa14ac39-4a19-491d-bb02-c7a0ebe48144
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073101015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.1073101015
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.3237700911
Short name	T14
Test name
Test status
Simulation time	1935884017 ps
CPU time	52.07 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:22:18 PM PDT 24
Peak memory	293612 kb
Host	smart-9f707c85-7ab7-401d-9ee5-5292b2cf08dd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237700911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3237700911
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.1616577225
Short name	T913
Test name
Test status
Simulation time	42764563 ps
CPU time	0.76 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:26 PM PDT 24
Peak memory	203340 kb
Host	smart-88d55c6d-8848-4c30-ba1b-52e24f571cf7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616577225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1616577225
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.1140225902
Short name	T750
Test name
Test status
Simulation time	6157480527 ps
CPU time	717.64 seconds
Started	Mar 19 01:21:29 PM PDT 24
Finished	Mar 19 01:33:26 PM PDT 24
Peak memory	375036 kb
Host	smart-44011324-1e13-4e63-8b02-a04257c2538c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140225902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1140225902
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.4082646542
Short name	T253
Test name
Test status
Simulation time	635181336 ps
CPU time	24.69 seconds
Started	Mar 19 01:21:29 PM PDT 24
Finished	Mar 19 01:21:54 PM PDT 24
Peak memory	267872 kb
Host	smart-2d36196b-50cd-4aac-aa3f-e04d692245d2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082646542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4082646542
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.725855490
Short name	T686
Test name
Test status
Simulation time	5091657479 ps
CPU time	569.52 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:31:01 PM PDT 24
Peak memory	372380 kb
Host	smart-569c3b99-a4c7-4768-9454-827d961afb2e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=725855490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.725855490
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2597799214
Short name	T500
Test name
Test status
Simulation time	2782214885 ps
CPU time	259.62 seconds
Started	Mar 19 01:21:26 PM PDT 24
Finished	Mar 19 01:25:45 PM PDT 24
Peak memory	203340 kb
Host	smart-5f9c54ee-854f-4a5f-8966-22437cac1d30
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597799214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.2597799214
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1029222758
Short name	T356
Test name
Test status
Simulation time	103516478 ps
CPU time	4.93 seconds
Started	Mar 19 01:21:25 PM PDT 24
Finished	Mar 19 01:21:30 PM PDT 24
Peak memory	226764 kb
Host	smart-ab40c8e5-c557-49c4-8e0f-2660452322ea
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029222758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1029222758
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.796569012
Short name	T401
Test name
Test status
Simulation time	1835943293 ps
CPU time	201.7 seconds
Started	Mar 19 01:21:39 PM PDT 24
Finished	Mar 19 01:25:01 PM PDT 24
Peak memory	359484 kb
Host	smart-0c954d52-154b-41e9-b2fe-83f091d72b64
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796569012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.796569012
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.987178505
Short name	T186
Test name
Test status
Simulation time	32077836 ps
CPU time	0.62 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 01:21:39 PM PDT 24
Peak memory	202376 kb
Host	smart-0738131b-aa3b-47a8-8d28-3e774b5417f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987178505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.987178505
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.3631966794
Short name	T679
Test name
Test status
Simulation time	2659836631 ps
CPU time	46.74 seconds
Started	Mar 19 01:21:30 PM PDT 24
Finished	Mar 19 01:22:17 PM PDT 24
Peak memory	203264 kb
Host	smart-0a86b779-0f0c-40c8-a736-2c5f33bbf4cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631966794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 3631966794
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.1776386411
Short name	T552
Test name
Test status
Simulation time	20322322251 ps
CPU time	251.12 seconds
Started	Mar 19 01:21:35 PM PDT 24
Finished	Mar 19 01:25:47 PM PDT 24
Peak memory	323108 kb
Host	smart-2db926f6-0467-4dc5-9d59-3b3b8f2da82a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776386411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1776386411
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.1960769320
Short name	T463
Test name
Test status
Simulation time	476422446 ps
CPU time	2.74 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:21:33 PM PDT 24
Peak memory	203256 kb
Host	smart-3f73d03b-a78b-49d0-a72d-b09e0f68fbc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960769320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.1960769320
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.1985076067
Short name	T273
Test name
Test status
Simulation time	580230417 ps
CPU time	101.17 seconds
Started	Mar 19 01:21:32 PM PDT 24
Finished	Mar 19 01:23:13 PM PDT 24
Peak memory	341152 kb
Host	smart-809f7fa4-87b3-4b0e-ac00-e52fdab3c411
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985076067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1985076067
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.790686072
Short name	T518
Test name
Test status
Simulation time	303269241 ps
CPU time	4.63 seconds
Started	Mar 19 01:21:36 PM PDT 24
Finished	Mar 19 01:21:41 PM PDT 24
Peak memory	211380 kb
Host	smart-092bb23d-9e4f-435d-8ddc-1ded7d5945ab
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790686072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. sram_ctrl_mem_partial_access.790686072
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.818252581
Short name	T811
Test name
Test status
Simulation time	567199375 ps
CPU time	10.03 seconds
Started	Mar 19 01:21:35 PM PDT 24
Finished	Mar 19 01:21:45 PM PDT 24
Peak memory	203252 kb
Host	smart-ac8e8b26-e9b6-4f2c-8d2d-0290d7e4608d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818252581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.818252581
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.1023041310
Short name	T830
Test name
Test status
Simulation time	9612712059 ps
CPU time	386.66 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:27:57 PM PDT 24
Peak memory	327004 kb
Host	smart-a2119f88-a72f-42a3-bce7-19caf196697d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023041310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.1023041310
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.1824584420
Short name	T257
Test name
Test status
Simulation time	82196727 ps
CPU time	13.12 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:21:44 PM PDT 24
Peak memory	250300 kb
Host	smart-331f0caf-0cd6-4496-ae9d-cba04e474b56
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824584420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1824584420
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.351117271
Short name	T232
Test name
Test status
Simulation time	3352872405 ps
CPU time	239.01 seconds
Started	Mar 19 01:21:31 PM PDT 24
Finished	Mar 19 01:25:30 PM PDT 24
Peak memory	203268 kb
Host	smart-175dc9c6-ec1b-4c2d-a9a5-57b7827f40e9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351117271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.351117271
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.3026415681
Short name	T399
Test name
Test status
Simulation time	93627811 ps
CPU time	0.77 seconds
Started	Mar 19 01:21:36 PM PDT 24
Finished	Mar 19 01:21:37 PM PDT 24
Peak memory	203300 kb
Host	smart-c2bb27a9-8479-4536-8a55-607c4002f6c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026415681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3026415681
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_regwen.1981942579
Short name	T27
Test name
Test status
Simulation time	6772035937 ps
CPU time	44.99 seconds
Started	Mar 19 01:21:37 PM PDT 24
Finished	Mar 19 01:22:22 PM PDT 24
Peak memory	264664 kb
Host	smart-6133dec6-111b-4011-9cdf-882283968530
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981942579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1981942579
Directory	/workspace/8.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.3885279526
Short name	T471
Test name
Test status
Simulation time	350938349 ps
CPU time	20.56 seconds
Started	Mar 19 01:21:30 PM PDT 24
Finished	Mar 19 01:21:51 PM PDT 24
Peak memory	274980 kb
Host	smart-0b9036d3-1d34-4c8c-8208-1023f7c34020
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885279526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3885279526
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.1537076550
Short name	T734
Test name
Test status
Simulation time	19772878643 ps
CPU time	1820.06 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 01:51:58 PM PDT 24
Peak memory	375960 kb
Host	smart-e9bd02bb-54ba-43f1-b3ba-c1293e6d5bff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537076550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1537076550
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1052324879
Short name	T105
Test name
Test status
Simulation time	7473050266 ps
CPU time	201.8 seconds
Started	Mar 19 01:21:34 PM PDT 24
Finished	Mar 19 01:24:56 PM PDT 24
Peak memory	203296 kb
Host	smart-b6105cd2-50d3-4025-b2b5-c4305d9199c5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052324879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1052324879
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2982403523
Short name	T244
Test name
Test status
Simulation time	551255829 ps
CPU time	90.24 seconds
Started	Mar 19 01:21:30 PM PDT 24
Finished	Mar 19 01:23:00 PM PDT 24
Peak memory	353460 kb
Host	smart-0e8cff61-0ea7-4b68-9d89-f2c74af2df77
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982403523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2982403523
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4086557276
Short name	T313
Test name
Test status
Simulation time	4674871966 ps
CPU time	969.84 seconds
Started	Mar 19 01:21:43 PM PDT 24
Finished	Mar 19 01:37:53 PM PDT 24
Peak memory	368964 kb
Host	smart-8f2f9bc4-374c-49cc-99d8-108655b04fb7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086557276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.4086557276
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.4114658367
Short name	T238
Test name
Test status
Simulation time	41526184 ps
CPU time	0.66 seconds
Started	Mar 19 01:21:48 PM PDT 24
Finished	Mar 19 01:21:51 PM PDT 24
Peak memory	203092 kb
Host	smart-447ade09-7ea9-4095-9087-b0eff67ab5a8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114658367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.4114658367
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.3503716029
Short name	T543
Test name
Test status
Simulation time	7903270241 ps
CPU time	39.84 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 01:22:18 PM PDT 24
Peak memory	203260 kb
Host	smart-5f92deb6-abd0-4130-825e-bdc740eead39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503716029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3503716029
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.704129032
Short name	T501
Test name
Test status
Simulation time	21257899466 ps
CPU time	1478.12 seconds
Started	Mar 19 01:21:41 PM PDT 24
Finished	Mar 19 01:46:19 PM PDT 24
Peak memory	361640 kb
Host	smart-6467dc74-05c2-43a3-8ec8-5822c676e53e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704129032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable .704129032
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.2065496307
Short name	T726
Test name
Test status
Simulation time	135425717 ps
CPU time	1.11 seconds
Started	Mar 19 01:21:45 PM PDT 24
Finished	Mar 19 01:21:46 PM PDT 24
Peak memory	203012 kb
Host	smart-0031b08b-9dc4-4db6-8cb5-5b1cfe3a72ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065496307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.2065496307
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.2676884459
Short name	T878
Test name
Test status
Simulation time	229097562 ps
CPU time	2.26 seconds
Started	Mar 19 01:21:43 PM PDT 24
Finished	Mar 19 01:21:46 PM PDT 24
Peak memory	216092 kb
Host	smart-7892e929-dbd6-4a25-88b5-5f94d6de7ca5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676884459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2676884459
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2100523718
Short name	T626
Test name
Test status
Simulation time	415415561 ps
CPU time	2.76 seconds
Started	Mar 19 01:21:43 PM PDT 24
Finished	Mar 19 01:21:46 PM PDT 24
Peak memory	211504 kb
Host	smart-fe1b0e51-53c7-4bb4-bcf6-2618a7c45e00
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100523718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2100523718
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.622165827
Short name	T885
Test name
Test status
Simulation time	444674629 ps
CPU time	9.26 seconds
Started	Mar 19 01:21:46 PM PDT 24
Finished	Mar 19 01:21:55 PM PDT 24
Peak memory	203288 kb
Host	smart-2a0703ca-6db1-4565-b8f0-5e60989c7f2e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622165827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.622165827
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.2970552263
Short name	T445
Test name
Test status
Simulation time	48338914453 ps
CPU time	1037.24 seconds
Started	Mar 19 01:21:36 PM PDT 24
Finished	Mar 19 01:38:53 PM PDT 24
Peak memory	370968 kb
Host	smart-ffe341aa-fb6f-4654-af1f-fab4f7eb8dde
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970552263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2970552263
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.1687398569
Short name	T403
Test name
Test status
Simulation time	762897154 ps
CPU time	95.26 seconds
Started	Mar 19 01:21:36 PM PDT 24
Finished	Mar 19 01:23:11 PM PDT 24
Peak memory	344708 kb
Host	smart-2bb01826-99ef-48df-821c-8eeb739be09e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687398569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1687398569
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1485707319
Short name	T778
Test name
Test status
Simulation time	1755412990 ps
CPU time	124.71 seconds
Started	Mar 19 01:21:36 PM PDT 24
Finished	Mar 19 01:23:41 PM PDT 24
Peak memory	203276 kb
Host	smart-2c5259fd-6c8d-422b-8d90-81638c08056a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485707319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.1485707319
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.768563496
Short name	T896
Test name
Test status
Simulation time	27762137 ps
CPU time	0.8 seconds
Started	Mar 19 01:21:44 PM PDT 24
Finished	Mar 19 01:21:45 PM PDT 24
Peak memory	203212 kb
Host	smart-014736a6-0b8f-4cd8-aa88-025c09d18526
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768563496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.768563496
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.2406470886
Short name	T911
Test name
Test status
Simulation time	16126614168 ps
CPU time	1399.53 seconds
Started	Mar 19 01:21:42 PM PDT 24
Finished	Mar 19 01:45:02 PM PDT 24
Peak memory	373016 kb
Host	smart-5584ffec-647c-4243-9289-682c8282a2e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406470886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2406470886
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.4227173271
Short name	T406
Test name
Test status
Simulation time	539163071 ps
CPU time	75.85 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 01:22:54 PM PDT 24
Peak memory	328460 kb
Host	smart-a59a13be-b4eb-4abe-8974-f57976a9d1e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227173271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4227173271
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.3059760519
Short name	T423
Test name
Test status
Simulation time	5906406757 ps
CPU time	2017.7 seconds
Started	Mar 19 01:21:53 PM PDT 24
Finished	Mar 19 01:55:32 PM PDT 24
Peak memory	376044 kb
Host	smart-6a581ca5-63d4-49b8-b378-153a9e02a5ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059760519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.3059760519
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.14184105
Short name	T653
Test name
Test status
Simulation time	966953285 ps
CPU time	254.26 seconds
Started	Mar 19 01:21:42 PM PDT 24
Finished	Mar 19 01:25:56 PM PDT 24
Peak memory	358680 kb
Host	smart-a6b6342a-8765-4f35-947b-1cdfcff2e87c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=14184105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.14184105
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3026054988
Short name	T742
Test name
Test status
Simulation time	29853068066 ps
CPU time	298.41 seconds
Started	Mar 19 01:21:38 PM PDT 24
Finished	Mar 19 01:26:36 PM PDT 24
Peak memory	203288 kb
Host	smart-ec4a576c-726b-403f-bab7-23d54d8e41ea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026054988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3026054988
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2558951029
Short name	T229
Test name
Test status
Simulation time	565427928 ps
CPU time	141.58 seconds
Started	Mar 19 01:21:44 PM PDT 24
Finished	Mar 19 01:24:06 PM PDT 24
Peak memory	362656 kb
Host	smart-ded5ff25-fb9b-4400-baf8-399b166484dc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558951029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2558951029
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest