Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14078730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60155749

1

T1

4143

T3

222

T4

1115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37026439	1			T1	2238		T3	589		T4	2947
values[0x0]	17196427	1			T1	1143		T3	209		T4	977
values[0x1]	20011613	1			T1	1204		T3	393		T4	2042

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7017722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67216757

1

T1

4364

T3

715

T4

3541

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	254097	1			T1	26		T3	8		T5	92
valid_sources[0x01]	340629	1			T1	17		T4	3		T5	121
valid_sources[0x02]	262709	1			T1	15		T3	6		T4	5
valid_sources[0x03]	267181	1			T1	20		T4	58		T5	141
valid_sources[0x04]	299974	1			T1	26		T3	1		T4	45
valid_sources[0x05]	299612	1			T1	19		T4	23		T5	112
valid_sources[0x06]	270698	1			T1	15		T3	5		T4	44
valid_sources[0x07]	271406	1			T1	33		T3	3		T5	137
valid_sources[0x08]	245153	1			T1	13		T3	1		T5	141
valid_sources[0x09]	343041	1			T1	15		T4	71		T5	106
valid_sources[0x0a]	280834	1			T1	20		T3	12		T4	95
valid_sources[0x0b]	251182	1			T1	15		T4	18		T5	107
valid_sources[0x0c]	255782	1			T1	20		T5	131		T6	21
valid_sources[0x0d]	279673	1			T1	14		T3	6		T4	5
valid_sources[0x0e]	294206	1			T1	15		T3	4		T5	120
valid_sources[0x0f]	337330	1			T1	25		T4	22		T5	113
valid_sources[0x10]	327728	1			T1	16		T3	1		T4	12
valid_sources[0x11]	297866	1			T1	20		T3	2		T4	59
valid_sources[0x12]	311544	1			T1	22		T3	11		T5	105
valid_sources[0x13]	297148	1			T1	19		T3	17		T5	98
valid_sources[0x14]	246134	1			T1	14		T3	1		T4	27
valid_sources[0x15]	287948	1			T1	17		T4	31		T5	100
valid_sources[0x16]	277938	1			T1	20		T3	17		T5	110
valid_sources[0x17]	286488	1			T1	16		T3	7		T4	24
valid_sources[0x18]	318883	1			T1	17		T4	16		T5	117
valid_sources[0x19]	331219	1			T1	17		T3	6		T5	118
valid_sources[0x1a]	259360	1			T1	20		T4	23		T5	120
valid_sources[0x1b]	331013	1			T1	22		T3	8		T4	46
valid_sources[0x1c]	280899	1			T1	20		T3	26		T4	46
valid_sources[0x1d]	312364	1			T1	17		T3	7		T4	75
valid_sources[0x1e]	323089	1			T1	17		T3	11		T4	24
valid_sources[0x1f]	259450	1			T1	21		T4	3		T5	125
valid_sources[0x20]	350403	1			T1	14		T3	2		T4	42
valid_sources[0x21]	277858	1			T1	19		T4	42		T5	116
valid_sources[0x22]	316564	1			T1	20		T5	121		T11	368
valid_sources[0x23]	259973	1			T1	17		T3	1		T4	32
valid_sources[0x24]	349070	1			T1	27		T3	2		T4	96
valid_sources[0x25]	258048	1			T1	15		T4	38		T5	107
valid_sources[0x26]	252519	1			T1	14		T4	55		T5	86
valid_sources[0x27]	299104	1			T1	25		T3	9		T5	117
valid_sources[0x28]	278554	1			T1	16		T3	2		T4	52
valid_sources[0x29]	294566	1			T1	18		T4	1		T5	105
valid_sources[0x2a]	299105	1			T1	18		T5	130		T6	4
valid_sources[0x2b]	307423	1			T1	15		T3	22		T4	19
valid_sources[0x2c]	258411	1			T1	21		T3	4		T5	100
valid_sources[0x2d]	283308	1			T1	25		T3	2		T4	16
valid_sources[0x2e]	259334	1			T1	9		T3	6		T4	63
valid_sources[0x2f]	248496	1			T1	18		T3	23		T4	32
valid_sources[0x30]	280237	1			T1	14		T3	14		T4	1
valid_sources[0x31]	284670	1			T1	22		T3	19		T5	116
valid_sources[0x32]	303253	1			T1	15		T3	5		T4	87
valid_sources[0x33]	336264	1			T1	24		T3	1		T4	51
valid_sources[0x34]	302372	1			T1	18		T5	126		T11	545
valid_sources[0x35]	281250	1			T1	12		T3	4		T5	141
valid_sources[0x36]	266535	1			T1	26		T3	29		T4	2
valid_sources[0x37]	267868	1			T1	18		T4	5		T5	112
valid_sources[0x38]	293192	1			T1	21		T3	3		T4	58
valid_sources[0x39]	316661	1			T1	18		T4	29		T5	94
valid_sources[0x3a]	276147	1			T1	16		T3	5		T4	12
valid_sources[0x3b]	287163	1			T1	12		T5	124		T11	507
valid_sources[0x3c]	289995	1			T1	17		T3	1		T4	46
valid_sources[0x3d]	310455	1			T1	22		T3	4		T4	57
valid_sources[0x3e]	262972	1			T1	14		T5	114		T6	19
valid_sources[0x3f]	273859	1			T1	23		T3	1		T5	119
valid_sources[0x40]	272102	1			T1	21		T3	29		T4	8
valid_sources[0x41]	261554	1			T1	11		T3	7		T4	19
valid_sources[0x42]	297320	1			T1	11		T3	18		T4	54
valid_sources[0x43]	264146	1			T1	24		T5	110		T6	15
valid_sources[0x44]	298693	1			T1	30		T4	2		T5	96
valid_sources[0x45]	254145	1			T1	15		T4	22		T5	107
valid_sources[0x46]	304761	1			T1	18		T4	45		T5	116
valid_sources[0x47]	354907	1			T1	23		T4	57		T5	105
valid_sources[0x48]	248370	1			T1	24		T3	27		T4	117
valid_sources[0x49]	309819	1			T1	9		T3	32		T4	24
valid_sources[0x4a]	270773	1			T1	11		T3	1		T4	18
valid_sources[0x4b]	302228	1			T1	11		T3	2		T4	48
valid_sources[0x4c]	305552	1			T1	15		T3	13		T4	15
valid_sources[0x4d]	254775	1			T1	19		T4	34		T5	120
valid_sources[0x4e]	261686	1			T1	12		T4	38		T5	124
valid_sources[0x4f]	314313	1			T1	14		T4	31		T5	109
valid_sources[0x50]	357201	1			T1	27		T3	5		T4	31
valid_sources[0x51]	257859	1			T1	15		T5	114		T6	4
valid_sources[0x52]	294961	1			T1	18		T4	23		T5	95
valid_sources[0x53]	303589	1			T1	20		T4	10		T5	117
valid_sources[0x54]	308110	1			T1	16		T5	110		T11	634
valid_sources[0x55]	340047	1			T1	18		T3	1		T4	72
valid_sources[0x56]	266563	1			T1	18		T4	18		T5	129
valid_sources[0x57]	318886	1			T1	20		T3	6		T5	112
valid_sources[0x58]	286377	1			T1	15		T5	100		T11	572
valid_sources[0x59]	304113	1			T1	25		T3	4		T5	103
valid_sources[0x5a]	271330	1			T1	9		T3	10		T4	13
valid_sources[0x5b]	326393	1			T1	18		T3	10		T4	3
valid_sources[0x5c]	250999	1			T1	23		T3	7		T4	85
valid_sources[0x5d]	249959	1			T1	16		T4	11		T5	108
valid_sources[0x5e]	284585	1			T1	14		T3	3		T5	97
valid_sources[0x5f]	266616	1			T1	16		T3	7		T4	29
valid_sources[0x60]	246991	1			T1	21		T3	7		T4	29
valid_sources[0x61]	275762	1			T1	22		T3	2		T5	104
valid_sources[0x62]	268647	1			T1	13		T5	111		T11	457
valid_sources[0x63]	409952	1			T1	14		T4	15		T5	114
valid_sources[0x64]	278634	1			T1	21		T4	53		T5	115
valid_sources[0x65]	280295	1			T1	28		T5	123		T6	10
valid_sources[0x66]	277214	1			T1	17		T3	11		T4	22
valid_sources[0x67]	254464	1			T1	16		T3	3		T5	118
valid_sources[0x68]	299359	1			T1	14		T3	24		T4	14
valid_sources[0x69]	284853	1			T1	15		T4	38		T5	128
valid_sources[0x6a]	353651	1			T1	14		T5	103		T11	620
valid_sources[0x6b]	276291	1			T1	15		T4	5		T5	114
valid_sources[0x6c]	268854	1			T1	16		T4	4		T5	109
valid_sources[0x6d]	326309	1			T1	18		T3	7		T4	37
valid_sources[0x6e]	326514	1			T1	19		T3	3		T4	1
valid_sources[0x6f]	289053	1			T1	21		T4	1		T5	111
valid_sources[0x70]	254852	1			T1	20		T3	1		T4	32
valid_sources[0x71]	252508	1			T1	20		T4	38		T5	131
valid_sources[0x72]	298548	1			T1	12		T3	10		T4	56
valid_sources[0x73]	276417	1			T1	22		T5	129		T6	26
valid_sources[0x74]	336723	1			T1	20		T4	45		T5	111
valid_sources[0x75]	294490	1			T1	24		T3	10		T4	20
valid_sources[0x76]	306711	1			T1	26		T3	5		T4	8
valid_sources[0x77]	290702	1			T1	25		T3	7		T5	80
valid_sources[0x78]	330488	1			T1	18		T5	110		T6	19
valid_sources[0x79]	275821	1			T1	11		T3	27		T4	13
valid_sources[0x7a]	316866	1			T1	22		T3	16		T4	24
valid_sources[0x7b]	317094	1			T1	22		T3	1		T4	63
valid_sources[0x7c]	306211	1			T1	15		T4	33		T5	131
valid_sources[0x7d]	339800	1			T1	13		T4	5		T5	100
valid_sources[0x7e]	284605	1			T1	11		T4	28		T5	94
valid_sources[0x7f]	317604	1			T1	15		T5	106		T11	504
valid_sources[0x80]	349587	1			T1	19		T4	23		T5	130

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29993265

1

T1

2018

T3

119

T4

558

values[0x0]

all_enables

biggest_size

15082136

1

T1

1075

T3

60

T4

283

values[0x1]

all_enables

biggest_size

15080348

1

T1

1050

T3

43

T4

274

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121071

1

T10

8

T4

1

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45197	1			T7	10		T8	22		T18	18
values[0x0]	52453	1			T1	1		T2	1		T3	1
values[0x1]	56139	1			T1	1		T3	1		T10	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

128549

1

T10

9

T4

1

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	459	1			T47	1		T86	1		T62	1
valid_sources[0x01]	706	1			T15	1		T140	1		T33	14
valid_sources[0x02]	638	1			T47	3		T147	20		T33	14
valid_sources[0x03]	501	1			T81	1		T33	11		T127	1
valid_sources[0x04]	645	1			T62	1		T33	9		T28	1
valid_sources[0x05]	809	1			T19	3		T33	9		T39	7
valid_sources[0x06]	515	1			T9	1		T33	11		T28	1
valid_sources[0x07]	572	1			T141	1		T62	5		T33	9
valid_sources[0x08]	497	1			T33	7		T148	2		T149	2
valid_sources[0x09]	432	1			T15	1		T19	5		T47	3
valid_sources[0x0a]	697	1			T33	15		T35	1		T150	2
valid_sources[0x0b]	593	1			T33	10		T35	7		T151	1
valid_sources[0x0c]	732	1			T11	1		T33	11		T45	2
valid_sources[0x0d]	576	1			T62	1		T33	7		T152	2
valid_sources[0x0e]	680	1			T16	1		T9	2		T62	2
valid_sources[0x0f]	497	1			T11	1		T33	11		T153	1
valid_sources[0x10]	595	1			T154	7		T47	1		T33	9
valid_sources[0x11]	685	1			T15	2		T47	2		T62	3
valid_sources[0x12]	534	1			T11	1		T19	1		T9	1
valid_sources[0x13]	565	1			T62	1		T33	11		T27	1
valid_sources[0x14]	577	1			T9	1		T62	2		T33	14
valid_sources[0x15]	611	1			T140	1		T62	2		T33	13
valid_sources[0x16]	607	1			T7	2		T9	1		T33	8
valid_sources[0x17]	538	1			T33	8		T155	3		T35	8
valid_sources[0x18]	419	1			T141	1		T33	10		T155	1
valid_sources[0x19]	467	1			T47	1		T33	6		T45	2
valid_sources[0x1a]	430	1			T156	1		T33	6		T157	1
valid_sources[0x1b]	677	1			T17	48		T62	1		T33	5
valid_sources[0x1c]	592	1			T33	4		T50	15		T158	1
valid_sources[0x1d]	497	1			T2	1		T47	1		T33	13
valid_sources[0x1e]	488	1			T15	2		T62	3		T33	10
valid_sources[0x1f]	589	1			T47	1		T100	2		T33	12
valid_sources[0x20]	559	1			T7	2		T47	1		T33	8
valid_sources[0x21]	473	1			T9	1		T33	6		T20	1
valid_sources[0x22]	454	1			T33	14		T27	1		T155	1
valid_sources[0x23]	704	1			T33	6		T58	1		T153	1
valid_sources[0x24]	550	1			T159	1		T33	12		T56	11
valid_sources[0x25]	555	1			T47	1		T62	1		T33	5
valid_sources[0x26]	516	1			T141	2		T33	7		T31	54
valid_sources[0x27]	608	1			T7	3		T110	1		T62	2
valid_sources[0x28]	693	1			T47	1		T33	7		T87	1
valid_sources[0x29]	637	1			T33	14		T39	5		T155	2
valid_sources[0x2a]	504	1			T33	12		T153	1		T28	2
valid_sources[0x2b]	506	1			T62	1		T33	13		T45	1
valid_sources[0x2c]	506	1			T33	12		T45	1		T155	6
valid_sources[0x2d]	455	1			T47	1		T33	11		T20	1
valid_sources[0x2e]	444	1			T62	3		T33	9		T27	1
valid_sources[0x2f]	458	1			T141	2		T33	9		T27	1
valid_sources[0x30]	503	1			T30	3		T33	10		T157	3
valid_sources[0x31]	647	1			T66	1		T33	11		T41	1
valid_sources[0x32]	605	1			T33	11		T50	19		T160	1
valid_sources[0x33]	503	1			T9	1		T33	14		T161	2
valid_sources[0x34]	463	1			T19	2		T47	2		T33	15
valid_sources[0x35]	523	1			T9	1		T33	8		T153	1
valid_sources[0x36]	478	1			T140	2		T33	9		T20	1
valid_sources[0x37]	570	1			T47	1		T33	9		T45	2
valid_sources[0x38]	629	1			T33	10		T153	1		T162	1
valid_sources[0x39]	672	1			T33	7		T60	1		T27	1
valid_sources[0x3a]	380	1			T140	1		T33	7		T157	2
valid_sources[0x3b]	743	1			T33	10		T155	1		T35	3
valid_sources[0x3c]	525	1			T33	6		T24	1		T155	1
valid_sources[0x3d]	767	1			T140	1		T33	12		T106	144
valid_sources[0x3e]	585	1			T23	1		T62	1		T33	12
valid_sources[0x3f]	871	1			T163	2		T33	17		T45	1
valid_sources[0x40]	580	1			T33	10		T45	1		T28	1
valid_sources[0x41]	1143	1			T47	1		T33	13		T155	1
valid_sources[0x42]	483	1			T33	10		T20	1		T41	1
valid_sources[0x43]	451	1			T164	1		T33	2		T157	1
valid_sources[0x44]	740	1			T33	8		T165	1		T35	1
valid_sources[0x45]	592	1			T62	1		T33	15		T60	1
valid_sources[0x46]	492	1			T141	2		T33	6		T27	1
valid_sources[0x47]	468	1			T33	11		T165	1		T50	39
valid_sources[0x48]	691	1			T47	1		T62	1		T33	5
valid_sources[0x49]	707	1			T140	1		T33	9		T56	1
valid_sources[0x4a]	750	1			T47	1		T33	10		T166	4
valid_sources[0x4b]	636	1			T9	1		T33	9		T34	19
valid_sources[0x4c]	580	1			T6	1		T30	1		T33	11
valid_sources[0x4d]	707	1			T32	1		T141	1		T62	2
valid_sources[0x4e]	535	1			T19	2		T33	13		T153	1
valid_sources[0x4f]	503	1			T7	2		T62	7		T33	9
valid_sources[0x50]	633	1			T33	6		T153	1		T28	1
valid_sources[0x51]	518	1			T9	1		T47	1		T62	1
valid_sources[0x52]	927	1			T47	1		T167	2		T62	1
valid_sources[0x53]	810	1			T62	1		T33	8		T28	1
valid_sources[0x54]	434	1			T9	1		T62	1		T33	12
valid_sources[0x55]	617	1			T9	1		T30	2		T33	11
valid_sources[0x56]	542	1			T7	2		T62	4		T33	6
valid_sources[0x57]	489	1			T140	2		T33	11		T63	3
valid_sources[0x58]	651	1			T9	2		T140	1		T47	1
valid_sources[0x59]	486	1			T30	9		T33	3		T24	2
valid_sources[0x5a]	701	1			T18	134		T9	1		T81	3
valid_sources[0x5b]	484	1			T33	7		T155	6		T35	3
valid_sources[0x5c]	396	1			T100	1		T33	9		T168	1
valid_sources[0x5d]	528	1			T33	21		T157	1		T169	3
valid_sources[0x5e]	580	1			T9	1		T47	2		T62	5
valid_sources[0x5f]	506	1			T9	1		T47	1		T30	4
valid_sources[0x60]	531	1			T47	1		T33	7		T162	1
valid_sources[0x61]	588	1			T7	1		T33	14		T127	9
valid_sources[0x62]	807	1			T15	2		T9	2		T33	8
valid_sources[0x63]	473	1			T3	1		T33	15		T63	5
valid_sources[0x64]	462	1			T62	2		T33	5		T27	2
valid_sources[0x65]	479	1			T33	6		T35	2		T50	10
valid_sources[0x66]	756	1			T33	6		T20	1		T27	1
valid_sources[0x67]	510	1			T33	11		T166	1		T22	1
valid_sources[0x68]	998	1			T81	5		T30	1		T33	14
valid_sources[0x69]	814	1			T62	1		T33	5		T45	1
valid_sources[0x6a]	512	1			T47	1		T33	9		T24	4
valid_sources[0x6b]	506	1			T140	1		T33	10		T28	1
valid_sources[0x6c]	484	1			T33	5		T157	2		T27	1
valid_sources[0x6d]	529	1			T9	1		T47	1		T62	3
valid_sources[0x6e]	639	1			T23	1		T33	13		T162	1
valid_sources[0x6f]	802	1			T33	10		T170	3		T171	1
valid_sources[0x70]	382	1			T140	1		T47	1		T141	1
valid_sources[0x71]	536	1			T33	10		T28	1		T165	1
valid_sources[0x72]	509	1			T29	30		T62	1		T172	1
valid_sources[0x73]	389	1			T15	1		T33	12		T171	1
valid_sources[0x74]	744	1			T81	1		T62	1		T33	9
valid_sources[0x75]	523	1			T47	1		T33	14		T20	2
valid_sources[0x76]	476	1			T30	1		T33	13		T162	1
valid_sources[0x77]	567	1			T62	2		T33	11		T27	1
valid_sources[0x78]	586	1			T9	2		T33	10		T165	2
valid_sources[0x79]	703	1			T33	16		T162	1		T173	1
valid_sources[0x7a]	554	1			T62	1		T33	13		T41	1
valid_sources[0x7b]	491	1			T19	3		T9	1		T47	1
valid_sources[0x7c]	740	1			T33	5		T27	1		T28	2
valid_sources[0x7d]	687	1			T140	1		T141	3		T33	5
valid_sources[0x7e]	653	1			T1	2		T47	1		T81	1
valid_sources[0x7f]	882	1			T33	10		T127	1		T28	1
valid_sources[0x80]	495	1			T5	14		T33	9		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33637

1

T7

7

T8

10

T18

10

values[0x0]

all_enables

biggest_size

44540

1

T10

6

T4

1

T5

2

values[0x1]

all_enables

biggest_size

42894

1

T10

2

T5

1

T11

1