Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13773966

1

T1

442

T3

969

T4

4851

full_word

55380448

1

T1

4143

T3

222

T4

1115

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69154134	1			T1	4585		T3	1191		T4	5966
auto[TlIntgErrCmd]	94	1			T107	6		T108	4		T109	6
auto[TlIntgErrData]	88	1			T107	8		T108	3		T109	8
auto[TlIntgErrBoth]	98	1			T107	6		T108	3		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31879613

1

T1

2238

T3

589

T4

2947

auto[1]

37274801

1

T1

2347

T3

602

T4

3019

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6597149	1			T1	220		T3	470		T4	2389
auto[TlIntgErrNone]	partial	auto[1]	7176556	1			T1	222		T3	499		T4	2462
auto[TlIntgErrNone]	full_word	auto[0]	25282318	1			T1	2018		T3	119		T4	558
auto[TlIntgErrNone]	full_word	auto[1]	30098111	1			T1	2125		T3	103		T4	557
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T107	3		T108	2		T109	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T107	3		T108	2		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T128	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T107	6		T108	2		T109	3
auto[TlIntgErrData]	partial	auto[1]	32	1			T107	2		T108	1		T109	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T109	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T128	1		T129	2		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T107	3		T108	1		T109	4
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T107	2		T108	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T129	1		T132	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T107	1		T108	1		T109	1