Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	615849	1			T1	588		T3	6		T6	297
auto[1]	11566801	1			T1	161		T3	3		T6	71
auto[2]	504806	1			T1	605		T3	4		T6	253
auto[3]	11458771	1			T1	110		T3	4		T6	39

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15580603	1			T1	1102		T6	513		T11	205
auto[1]	2329824	1			T1	150		T3	2		T6	68
auto[2]	2320591	1			T1	183		T3	2		T6	69
auto[3]	3915209	1			T1	29		T3	13		T6	10

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9121669

1

T1

1464

T3

17

T6

659

auto[1]

15024558

1

T6

1

T11

16872

T13

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	290622	1			T1	467		T6	242		T8	11
auto[0]	auto[0]	auto[1]	29459	1			T1	55		T3	1		T6	24
auto[0]	auto[0]	auto[2]	29657	1			T1	59		T6	24		T78	1
auto[0]	auto[0]	auto[3]	6939	1			T1	7		T3	5		T6	6
auto[0]	auto[1]	auto[0]	3494745	1			T1	89		T6	43		T11	1
auto[0]	auto[1]	auto[1]	356709	1			T1	49		T6	24		T13	439
auto[0]	auto[1]	auto[2]	345930	1			T1	16		T3	1		T6	2
auto[0]	auto[1]	auto[3]	56558	1			T1	7		T3	2		T6	2
auto[0]	auto[2]	auto[0]	247065	1			T1	502		T6	213		T8	9
auto[0]	auto[2]	auto[1]	24981	1			T1	39		T3	1		T6	19
auto[0]	auto[2]	auto[2]	24730	1			T1	55		T6	20		T8	1
auto[0]	auto[2]	auto[3]	5680	1			T1	9		T3	3		T6	1
auto[0]	auto[3]	auto[0]	3450201	1			T1	44		T6	15		T13	1809
auto[0]	auto[3]	auto[1]	342869	1			T1	7		T6	1		T13	423
auto[0]	auto[3]	auto[2]	355630	1			T1	53		T3	1		T6	22
auto[0]	auto[3]	auto[3]	59894	1			T1	6		T3	3		T6	1
auto[1]	auto[0]	auto[0]	8801	1			T81	16		T33	1		T48	11
auto[1]	auto[0]	auto[1]	38683	1			T81	2		T48	3		T27	1
auto[1]	auto[0]	auto[2]	38392	1			T6	1		T81	1		T48	3
auto[1]	auto[0]	auto[3]	173296	1			T78	1		T144	13868		T145	10205
auto[1]	auto[1]	auto[0]	4044063	1			T11	96		T13	3		T14	31
auto[1]	auto[1]	auto[1]	759088	1			T11	1449		T14	4		T15	1
auto[1]	auto[1]	auto[2]	748375	1			T11	494		T13	1		T14	1
auto[1]	auto[1]	auto[3]	1761333	1			T11	6481		T13	1		T78	1
auto[1]	auto[2]	auto[0]	7886	1			T8	1		T81	24		T33	1
auto[1]	auto[2]	auto[1]	34477	1			T81	3		T48	1		T46	1
auto[1]	auto[2]	auto[2]	29302	1			T144	2039		T145	1550		T146	1
auto[1]	auto[2]	auto[3]	130685	1			T79	1		T144	9240		T145	6972
auto[1]	auto[3]	auto[0]	4037220	1			T11	108		T13	2		T14	28
auto[1]	auto[3]	auto[1]	743558	1			T11	477		T65	1		T19	1
auto[1]	auto[3]	auto[2]	748575	1			T11	1409		T13	2		T14	2
auto[1]	auto[3]	auto[3]	1720824	1			T11	6358		T14	1		T18	2