Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	308862768	114501	0	0
ctrl_regwen_rd_A	308862768	3921	0	0
exec_rd_A	308862768	3179	0	0
exec_regwen_rd_A	308862768	3445	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308862768	114501	0	0
T20	169784	0	0	0
T31	37098	0	0	0
T33	170358	2487	0	0
T34	0	471	0	0
T35	0	1903	0	0
T48	469609	0	0	0
T49	0	2898	0	0
T50	0	1797	0	0
T51	0	6090	0	0
T52	0	3024	0	0
T53	0	1394	0	0
T54	0	4702	0	0
T55	0	1941	0	0
T56	327646	0	0	0
T57	7139	0	0	0
T58	377010	0	0	0
T59	3812	0	0	0
T60	43216	0	0	0
T61	52581	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308862768	3921	0	0
T52	167542	413	0	0
T53	42761	0	0	0
T68	0	4	0	0
T69	0	33	0	0
T70	0	73	0	0
T112	0	242	0	0
T113	0	94	0	0
T114	0	245	0	0
T115	0	29	0	0
T116	0	239	0	0
T117	0	276	0	0
T118	8212	0	0	0
T119	179995	0	0	0
T120	19106	0	0	0
T121	520989	0	0	0
T122	14772	0	0	0
T123	1706	0	0	0
T124	938	0	0	0
T125	34548	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308862768	3179	0	0
T52	167542	328	0	0
T53	42761	0	0	0
T68	0	29	0	0
T69	0	19	0	0
T70	0	78	0	0
T112	0	152	0	0
T113	0	91	0	0
T114	0	176	0	0
T115	0	51	0	0
T116	0	145	0	0
T117	0	170	0	0
T118	8212	0	0	0
T119	179995	0	0	0
T120	19106	0	0	0
T121	520989	0	0	0
T122	14772	0	0	0
T123	1706	0	0	0
T124	938	0	0	0
T125	34548	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308862768	3445	0	0
T52	167542	351	0	0
T53	42761	0	0	0
T69	0	27	0	0
T70	0	69	0	0
T112	0	236	0	0
T113	0	96	0	0
T114	0	150	0	0
T115	0	43	0	0
T116	0	131	0	0
T117	0	244	0	0
T118	8212	0	0	0
T119	179995	0	0	0
T120	19106	0	0	0
T121	520989	0	0	0
T122	14772	0	0	0
T123	1706	0	0	0
T124	938	0	0	0
T125	34548	0	0	0
T126	0	65	0	0