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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.36 100.00 97.77 100.00 100.00 99.71 99.70 98.33


Total test records in report: 1020
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T794 /workspace/coverage/default/20.sram_ctrl_lc_escalation.1001109163 Mar 21 01:39:33 PM PDT 24 Mar 21 01:39:42 PM PDT 24 2608519562 ps
T795 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2303890134 Mar 21 01:38:07 PM PDT 24 Mar 21 01:42:34 PM PDT 24 3793511484 ps
T796 /workspace/coverage/default/21.sram_ctrl_smoke.538852513 Mar 21 01:39:31 PM PDT 24 Mar 21 01:39:33 PM PDT 24 137552112 ps
T797 /workspace/coverage/default/0.sram_ctrl_smoke.4016723986 Mar 21 01:37:44 PM PDT 24 Mar 21 01:38:07 PM PDT 24 13643324912 ps
T798 /workspace/coverage/default/8.sram_ctrl_alert_test.1844738101 Mar 21 01:38:39 PM PDT 24 Mar 21 01:38:40 PM PDT 24 41149878 ps
T799 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.344549856 Mar 21 01:39:30 PM PDT 24 Mar 21 01:42:00 PM PDT 24 1603932136 ps
T800 /workspace/coverage/default/19.sram_ctrl_max_throughput.2408738840 Mar 21 01:39:17 PM PDT 24 Mar 21 01:40:43 PM PDT 24 460845330 ps
T801 /workspace/coverage/default/39.sram_ctrl_lc_escalation.1491748016 Mar 21 01:41:31 PM PDT 24 Mar 21 01:41:37 PM PDT 24 2430004328 ps
T802 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1142530829 Mar 21 01:41:17 PM PDT 24 Mar 21 01:45:18 PM PDT 24 3388988770 ps
T803 /workspace/coverage/default/17.sram_ctrl_executable.2369394496 Mar 21 01:39:12 PM PDT 24 Mar 21 01:47:05 PM PDT 24 4430467392 ps
T804 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2909076488 Mar 21 01:40:11 PM PDT 24 Mar 21 01:40:21 PM PDT 24 1397182340 ps
T805 /workspace/coverage/default/0.sram_ctrl_executable.3511143477 Mar 21 01:37:54 PM PDT 24 Mar 21 01:40:38 PM PDT 24 4319693915 ps
T806 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.298027816 Mar 21 01:37:54 PM PDT 24 Mar 21 01:37:57 PM PDT 24 175086421 ps
T807 /workspace/coverage/default/5.sram_ctrl_max_throughput.1149413498 Mar 21 01:38:07 PM PDT 24 Mar 21 01:38:25 PM PDT 24 310502032 ps
T808 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.248905877 Mar 21 01:39:58 PM PDT 24 Mar 21 01:45:37 PM PDT 24 3727540593 ps
T809 /workspace/coverage/default/23.sram_ctrl_stress_all.1640404100 Mar 21 01:39:42 PM PDT 24 Mar 21 03:27:07 PM PDT 24 855211556567 ps
T810 /workspace/coverage/default/38.sram_ctrl_stress_all.120654174 Mar 21 01:41:30 PM PDT 24 Mar 21 01:55:09 PM PDT 24 18215287785 ps
T811 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2343483995 Mar 21 01:39:15 PM PDT 24 Mar 21 02:03:21 PM PDT 24 3741284192 ps
T812 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1666900371 Mar 21 01:42:35 PM PDT 24 Mar 21 01:48:24 PM PDT 24 16043432358 ps
T813 /workspace/coverage/default/24.sram_ctrl_multiple_keys.1948767496 Mar 21 01:40:00 PM PDT 24 Mar 21 01:47:30 PM PDT 24 2156332636 ps
T814 /workspace/coverage/default/44.sram_ctrl_stress_all.3393182162 Mar 21 01:42:15 PM PDT 24 Mar 21 02:24:00 PM PDT 24 34082534160 ps
T815 /workspace/coverage/default/25.sram_ctrl_mem_walk.1238838176 Mar 21 01:39:59 PM PDT 24 Mar 21 01:40:08 PM PDT 24 454088848 ps
T816 /workspace/coverage/default/7.sram_ctrl_max_throughput.1440615416 Mar 21 01:38:20 PM PDT 24 Mar 21 01:38:42 PM PDT 24 86463647 ps
T817 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2016184148 Mar 21 01:41:20 PM PDT 24 Mar 21 01:54:53 PM PDT 24 4389961608 ps
T818 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2309429992 Mar 21 01:41:49 PM PDT 24 Mar 21 01:48:36 PM PDT 24 31849950830 ps
T819 /workspace/coverage/default/15.sram_ctrl_bijection.3542086177 Mar 21 01:39:04 PM PDT 24 Mar 21 01:39:57 PM PDT 24 9936649536 ps
T820 /workspace/coverage/default/39.sram_ctrl_executable.2893607209 Mar 21 01:41:31 PM PDT 24 Mar 21 01:57:20 PM PDT 24 38815972217 ps
T821 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3655641210 Mar 21 01:38:57 PM PDT 24 Mar 21 01:42:54 PM PDT 24 2648006636 ps
T822 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1786965223 Mar 21 01:42:13 PM PDT 24 Mar 21 01:43:47 PM PDT 24 1374872871 ps
T823 /workspace/coverage/default/7.sram_ctrl_mem_walk.2938929614 Mar 21 01:38:18 PM PDT 24 Mar 21 01:38:28 PM PDT 24 590273099 ps
T824 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2350172224 Mar 21 01:40:49 PM PDT 24 Mar 21 01:43:03 PM PDT 24 933537683 ps
T825 /workspace/coverage/default/16.sram_ctrl_lc_escalation.2971927332 Mar 21 01:39:07 PM PDT 24 Mar 21 01:39:10 PM PDT 24 135987463 ps
T826 /workspace/coverage/default/29.sram_ctrl_executable.3968820837 Mar 21 01:40:19 PM PDT 24 Mar 21 01:48:36 PM PDT 24 1669684860 ps
T827 /workspace/coverage/default/10.sram_ctrl_smoke.3386490576 Mar 21 01:38:37 PM PDT 24 Mar 21 01:40:30 PM PDT 24 3554716787 ps
T828 /workspace/coverage/default/32.sram_ctrl_partial_access.1376938434 Mar 21 01:40:51 PM PDT 24 Mar 21 01:41:04 PM PDT 24 641130899 ps
T829 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2304293988 Mar 21 01:39:05 PM PDT 24 Mar 21 01:39:12 PM PDT 24 197023567 ps
T830 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1471156420 Mar 21 01:38:03 PM PDT 24 Mar 21 01:45:17 PM PDT 24 33508433011 ps
T831 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2237706130 Mar 21 01:42:36 PM PDT 24 Mar 21 01:42:37 PM PDT 24 29789514 ps
T832 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2416576782 Mar 21 01:42:38 PM PDT 24 Mar 21 01:56:58 PM PDT 24 2421775649 ps
T833 /workspace/coverage/default/33.sram_ctrl_stress_all.322830234 Mar 21 01:40:49 PM PDT 24 Mar 21 02:11:19 PM PDT 24 69602919821 ps
T834 /workspace/coverage/default/27.sram_ctrl_mem_walk.2331736678 Mar 21 01:40:10 PM PDT 24 Mar 21 01:40:15 PM PDT 24 1146699186 ps
T835 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.394056046 Mar 21 01:38:54 PM PDT 24 Mar 21 01:44:57 PM PDT 24 9469499563 ps
T836 /workspace/coverage/default/24.sram_ctrl_alert_test.1111841175 Mar 21 01:39:56 PM PDT 24 Mar 21 01:39:57 PM PDT 24 23735646 ps
T837 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.140091660 Mar 21 01:39:44 PM PDT 24 Mar 21 01:43:18 PM PDT 24 8516996228 ps
T838 /workspace/coverage/default/6.sram_ctrl_partial_access.3969140397 Mar 21 01:38:13 PM PDT 24 Mar 21 01:38:24 PM PDT 24 595635219 ps
T839 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2581167774 Mar 21 01:41:05 PM PDT 24 Mar 21 01:43:21 PM PDT 24 211681918 ps
T840 /workspace/coverage/default/12.sram_ctrl_alert_test.174753833 Mar 21 01:38:57 PM PDT 24 Mar 21 01:38:58 PM PDT 24 24922479 ps
T841 /workspace/coverage/default/3.sram_ctrl_multiple_keys.1111931047 Mar 21 01:38:01 PM PDT 24 Mar 21 01:54:21 PM PDT 24 11916403397 ps
T842 /workspace/coverage/default/47.sram_ctrl_smoke.3655407403 Mar 21 01:42:46 PM PDT 24 Mar 21 01:43:12 PM PDT 24 709249327 ps
T843 /workspace/coverage/default/35.sram_ctrl_smoke.2784682482 Mar 21 01:41:07 PM PDT 24 Mar 21 01:41:58 PM PDT 24 2107280155 ps
T844 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2409058511 Mar 21 01:41:04 PM PDT 24 Mar 21 01:44:37 PM PDT 24 2447078465 ps
T845 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3334622345 Mar 21 01:38:06 PM PDT 24 Mar 21 01:40:37 PM PDT 24 5357239911 ps
T846 /workspace/coverage/default/45.sram_ctrl_executable.3026558278 Mar 21 01:42:23 PM PDT 24 Mar 21 01:53:11 PM PDT 24 20601458504 ps
T847 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3449635052 Mar 21 01:38:09 PM PDT 24 Mar 21 01:38:19 PM PDT 24 1206616103 ps
T848 /workspace/coverage/default/17.sram_ctrl_alert_test.2746788057 Mar 21 01:39:10 PM PDT 24 Mar 21 01:39:11 PM PDT 24 45876786 ps
T849 /workspace/coverage/default/35.sram_ctrl_partial_access.2980544158 Mar 21 01:41:07 PM PDT 24 Mar 21 01:41:51 PM PDT 24 806461362 ps
T850 /workspace/coverage/default/29.sram_ctrl_ram_cfg.2912719159 Mar 21 01:40:19 PM PDT 24 Mar 21 01:40:20 PM PDT 24 35924379 ps
T851 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3624403892 Mar 21 01:42:13 PM PDT 24 Mar 21 01:47:19 PM PDT 24 8593574770 ps
T852 /workspace/coverage/default/3.sram_ctrl_regwen.2617120707 Mar 21 01:38:01 PM PDT 24 Mar 21 01:49:17 PM PDT 24 32285175923 ps
T853 /workspace/coverage/default/10.sram_ctrl_multiple_keys.2611882219 Mar 21 01:38:53 PM PDT 24 Mar 21 01:58:11 PM PDT 24 201333833018 ps
T854 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3795762237 Mar 21 01:37:59 PM PDT 24 Mar 21 01:38:00 PM PDT 24 51395046 ps
T855 /workspace/coverage/default/43.sram_ctrl_ram_cfg.27735108 Mar 21 01:42:14 PM PDT 24 Mar 21 01:42:14 PM PDT 24 74721978 ps
T856 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2526115570 Mar 21 01:41:33 PM PDT 24 Mar 21 01:46:01 PM PDT 24 3743822766 ps
T857 /workspace/coverage/default/14.sram_ctrl_executable.2178480117 Mar 21 01:39:01 PM PDT 24 Mar 21 02:02:26 PM PDT 24 84614798919 ps
T858 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1970431116 Mar 21 01:43:07 PM PDT 24 Mar 21 01:58:53 PM PDT 24 3907907647 ps
T859 /workspace/coverage/default/4.sram_ctrl_smoke.2047385244 Mar 21 01:38:07 PM PDT 24 Mar 21 01:38:27 PM PDT 24 963549273 ps
T860 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1067601661 Mar 21 01:40:50 PM PDT 24 Mar 21 01:44:05 PM PDT 24 2230800296 ps
T861 /workspace/coverage/default/12.sram_ctrl_partial_access.4074179442 Mar 21 01:38:58 PM PDT 24 Mar 21 01:39:25 PM PDT 24 1295439452 ps
T862 /workspace/coverage/default/33.sram_ctrl_partial_access.2617278880 Mar 21 01:40:51 PM PDT 24 Mar 21 01:41:08 PM PDT 24 630712413 ps
T863 /workspace/coverage/default/38.sram_ctrl_regwen.3886436707 Mar 21 01:41:32 PM PDT 24 Mar 21 01:47:40 PM PDT 24 9169649520 ps
T864 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2805454275 Mar 21 01:38:39 PM PDT 24 Mar 21 01:38:42 PM PDT 24 88571608 ps
T865 /workspace/coverage/default/8.sram_ctrl_multiple_keys.889097155 Mar 21 01:38:38 PM PDT 24 Mar 21 02:02:13 PM PDT 24 23181091637 ps
T866 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2461208809 Mar 21 01:40:09 PM PDT 24 Mar 21 01:40:10 PM PDT 24 73800404 ps
T867 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1216027419 Mar 21 01:39:57 PM PDT 24 Mar 21 01:41:48 PM PDT 24 1174921039 ps
T868 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1547776879 Mar 21 01:38:55 PM PDT 24 Mar 21 01:43:32 PM PDT 24 11232899137 ps
T869 /workspace/coverage/default/27.sram_ctrl_alert_test.3516488583 Mar 21 01:40:06 PM PDT 24 Mar 21 01:40:07 PM PDT 24 30626531 ps
T870 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.391005322 Mar 21 01:41:31 PM PDT 24 Mar 21 01:41:47 PM PDT 24 200820323 ps
T871 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2034917895 Mar 21 01:40:10 PM PDT 24 Mar 21 01:41:10 PM PDT 24 122282755 ps
T872 /workspace/coverage/default/46.sram_ctrl_smoke.924191735 Mar 21 01:42:23 PM PDT 24 Mar 21 01:42:37 PM PDT 24 142692016 ps
T873 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.333341376 Mar 21 01:40:18 PM PDT 24 Mar 21 01:40:26 PM PDT 24 238914464 ps
T874 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.15919100 Mar 21 01:42:16 PM PDT 24 Mar 21 01:42:22 PM PDT 24 698190668 ps
T875 /workspace/coverage/default/42.sram_ctrl_multiple_keys.140424045 Mar 21 01:41:59 PM PDT 24 Mar 21 01:50:17 PM PDT 24 2420093989 ps
T876 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3389337646 Mar 21 01:41:17 PM PDT 24 Mar 21 01:49:01 PM PDT 24 87263220015 ps
T877 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.589788095 Mar 21 01:37:57 PM PDT 24 Mar 21 01:52:35 PM PDT 24 2881725961 ps
T878 /workspace/coverage/default/29.sram_ctrl_lc_escalation.2844621611 Mar 21 01:40:18 PM PDT 24 Mar 21 01:40:24 PM PDT 24 1338965743 ps
T879 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.335795369 Mar 21 01:39:01 PM PDT 24 Mar 21 01:45:01 PM PDT 24 10596684265 ps
T880 /workspace/coverage/default/38.sram_ctrl_bijection.2295927492 Mar 21 01:41:18 PM PDT 24 Mar 21 01:42:38 PM PDT 24 26954434522 ps
T881 /workspace/coverage/default/22.sram_ctrl_mem_walk.1882422958 Mar 21 01:39:46 PM PDT 24 Mar 21 01:39:51 PM PDT 24 147124230 ps
T882 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1251042398 Mar 21 01:38:55 PM PDT 24 Mar 21 01:44:45 PM PDT 24 4534441643 ps
T883 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1339093196 Mar 21 01:38:39 PM PDT 24 Mar 21 01:56:19 PM PDT 24 14560395189 ps
T884 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1416750117 Mar 21 01:40:32 PM PDT 24 Mar 21 01:41:17 PM PDT 24 133917292 ps
T885 /workspace/coverage/default/32.sram_ctrl_regwen.1052144143 Mar 21 01:40:53 PM PDT 24 Mar 21 01:45:50 PM PDT 24 14157102949 ps
T886 /workspace/coverage/default/16.sram_ctrl_multiple_keys.2711582081 Mar 21 01:38:57 PM PDT 24 Mar 21 01:54:40 PM PDT 24 179966125468 ps
T887 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1427967613 Mar 21 01:39:43 PM PDT 24 Mar 21 01:39:48 PM PDT 24 276652029 ps
T888 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4048521856 Mar 21 01:38:58 PM PDT 24 Mar 21 01:39:01 PM PDT 24 85540553 ps
T889 /workspace/coverage/default/37.sram_ctrl_mem_walk.2538480700 Mar 21 01:41:21 PM PDT 24 Mar 21 01:41:31 PM PDT 24 135808665 ps
T890 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2759828673 Mar 21 01:41:58 PM PDT 24 Mar 21 01:44:17 PM PDT 24 2717420132 ps
T891 /workspace/coverage/default/6.sram_ctrl_regwen.2447125793 Mar 21 01:38:21 PM PDT 24 Mar 21 01:52:08 PM PDT 24 37889279929 ps
T892 /workspace/coverage/default/48.sram_ctrl_executable.465975227 Mar 21 01:42:55 PM PDT 24 Mar 21 01:49:11 PM PDT 24 1400711784 ps
T893 /workspace/coverage/default/45.sram_ctrl_multiple_keys.4127167661 Mar 21 01:42:12 PM PDT 24 Mar 21 01:49:04 PM PDT 24 2148644151 ps
T894 /workspace/coverage/default/11.sram_ctrl_mem_walk.1855343302 Mar 21 01:39:01 PM PDT 24 Mar 21 01:39:11 PM PDT 24 608986539 ps
T895 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4125073876 Mar 21 01:38:52 PM PDT 24 Mar 21 01:57:12 PM PDT 24 1959969232 ps
T896 /workspace/coverage/default/41.sram_ctrl_mem_walk.1116067477 Mar 21 01:41:58 PM PDT 24 Mar 21 01:42:03 PM PDT 24 73252985 ps
T897 /workspace/coverage/default/48.sram_ctrl_multiple_keys.1133516514 Mar 21 01:42:54 PM PDT 24 Mar 21 01:54:49 PM PDT 24 52277712731 ps
T898 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3449235651 Mar 21 01:38:09 PM PDT 24 Mar 21 01:38:15 PM PDT 24 163186513 ps
T899 /workspace/coverage/default/42.sram_ctrl_executable.2402619266 Mar 21 01:42:09 PM PDT 24 Mar 21 02:00:15 PM PDT 24 48697484355 ps
T900 /workspace/coverage/default/36.sram_ctrl_smoke.388699353 Mar 21 01:41:07 PM PDT 24 Mar 21 01:41:25 PM PDT 24 2355339217 ps
T901 /workspace/coverage/default/2.sram_ctrl_alert_test.4063606878 Mar 21 01:38:04 PM PDT 24 Mar 21 01:38:05 PM PDT 24 14396568 ps
T902 /workspace/coverage/default/0.sram_ctrl_regwen.1675178309 Mar 21 01:37:54 PM PDT 24 Mar 21 01:59:37 PM PDT 24 4701689761 ps
T903 /workspace/coverage/default/22.sram_ctrl_stress_all.3267557925 Mar 21 01:39:42 PM PDT 24 Mar 21 03:01:47 PM PDT 24 208448200081 ps
T904 /workspace/coverage/default/2.sram_ctrl_max_throughput.3989189440 Mar 21 01:37:58 PM PDT 24 Mar 21 01:39:51 PM PDT 24 842583888 ps
T905 /workspace/coverage/default/33.sram_ctrl_alert_test.454405701 Mar 21 01:41:07 PM PDT 24 Mar 21 01:41:08 PM PDT 24 13923094 ps
T906 /workspace/coverage/default/43.sram_ctrl_multiple_keys.331956805 Mar 21 01:42:14 PM PDT 24 Mar 21 01:58:26 PM PDT 24 3733460906 ps
T907 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1491753865 Mar 21 01:40:51 PM PDT 24 Mar 21 02:07:11 PM PDT 24 5382506652 ps
T908 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4037996190 Mar 21 01:38:12 PM PDT 24 Mar 21 01:40:23 PM PDT 24 9056850777 ps
T909 /workspace/coverage/default/28.sram_ctrl_executable.971935135 Mar 21 01:40:18 PM PDT 24 Mar 21 01:46:21 PM PDT 24 3678071180 ps
T910 /workspace/coverage/default/30.sram_ctrl_bijection.3665776496 Mar 21 01:40:33 PM PDT 24 Mar 21 01:41:11 PM PDT 24 6386685515 ps
T911 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.641897436 Mar 21 01:41:07 PM PDT 24 Mar 21 01:44:43 PM PDT 24 5050009335 ps
T912 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1214939902 Mar 21 01:40:48 PM PDT 24 Mar 21 01:45:40 PM PDT 24 11560913326 ps
T913 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.876383773 Mar 21 01:39:42 PM PDT 24 Mar 21 01:43:38 PM PDT 24 9471202875 ps
T914 /workspace/coverage/default/10.sram_ctrl_executable.814621379 Mar 21 01:38:53 PM PDT 24 Mar 21 02:04:27 PM PDT 24 3923422741 ps
T915 /workspace/coverage/default/36.sram_ctrl_regwen.2694884154 Mar 21 01:41:19 PM PDT 24 Mar 21 01:59:35 PM PDT 24 1918039881 ps
T916 /workspace/coverage/default/48.sram_ctrl_stress_all.442008784 Mar 21 01:42:54 PM PDT 24 Mar 21 01:56:19 PM PDT 24 87934197470 ps
T917 /workspace/coverage/default/7.sram_ctrl_bijection.1644594352 Mar 21 01:38:22 PM PDT 24 Mar 21 01:39:31 PM PDT 24 4357441975 ps
T918 /workspace/coverage/default/17.sram_ctrl_partial_access.209915763 Mar 21 01:39:05 PM PDT 24 Mar 21 01:39:15 PM PDT 24 215903856 ps
T919 /workspace/coverage/default/18.sram_ctrl_multiple_keys.1326942556 Mar 21 01:39:11 PM PDT 24 Mar 21 01:57:54 PM PDT 24 10747381727 ps
T920 /workspace/coverage/default/15.sram_ctrl_mem_walk.3968654749 Mar 21 01:39:01 PM PDT 24 Mar 21 01:39:07 PM PDT 24 1868016424 ps
T921 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1227904089 Mar 21 01:38:25 PM PDT 24 Mar 21 01:44:38 PM PDT 24 8402717421 ps
T922 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.525084385 Mar 21 01:40:31 PM PDT 24 Mar 21 01:43:57 PM PDT 24 2184640571 ps
T923 /workspace/coverage/default/49.sram_ctrl_bijection.1357654423 Mar 21 01:43:09 PM PDT 24 Mar 21 01:44:00 PM PDT 24 13519344768 ps
T924 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1656736429 Mar 21 01:40:51 PM PDT 24 Mar 21 01:45:22 PM PDT 24 1444615643 ps
T925 /workspace/coverage/default/28.sram_ctrl_alert_test.4122012289 Mar 21 01:40:18 PM PDT 24 Mar 21 01:40:19 PM PDT 24 50639280 ps
T926 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2851204171 Mar 21 01:40:23 PM PDT 24 Mar 21 01:41:24 PM PDT 24 2442987297 ps
T927 /workspace/coverage/default/1.sram_ctrl_stress_all.2051920221 Mar 21 01:37:56 PM PDT 24 Mar 21 01:50:27 PM PDT 24 90545954972 ps
T928 /workspace/coverage/default/38.sram_ctrl_partial_access.101293864 Mar 21 01:41:19 PM PDT 24 Mar 21 01:41:20 PM PDT 24 47726780 ps
T929 /workspace/coverage/default/4.sram_ctrl_lc_escalation.3629088408 Mar 21 01:38:16 PM PDT 24 Mar 21 01:38:22 PM PDT 24 1903940877 ps
T117 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1863588589 Mar 21 01:38:58 PM PDT 24 Mar 21 01:39:09 PM PDT 24 747878192 ps
T930 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2068439018 Mar 21 01:42:06 PM PDT 24 Mar 21 01:47:04 PM PDT 24 45202211268 ps
T931 /workspace/coverage/default/6.sram_ctrl_ram_cfg.2656419480 Mar 21 01:38:19 PM PDT 24 Mar 21 01:38:20 PM PDT 24 316519040 ps
T68 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.79219786 Mar 21 03:03:34 PM PDT 24 Mar 21 03:03:35 PM PDT 24 49694752 ps
T932 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.556906575 Mar 21 03:03:36 PM PDT 24 Mar 21 03:03:37 PM PDT 24 264184265 ps
T69 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3680822387 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:23 PM PDT 24 54336653 ps
T104 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1311007923 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:05 PM PDT 24 51232989 ps
T933 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2617650004 Mar 21 03:03:34 PM PDT 24 Mar 21 03:03:36 PM PDT 24 106319193 ps
T70 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1017736240 Mar 21 03:03:53 PM PDT 24 Mar 21 03:03:57 PM PDT 24 853006172 ps
T71 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1429140414 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:45 PM PDT 24 206882072 ps
T934 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2271450466 Mar 21 03:03:42 PM PDT 24 Mar 21 03:03:46 PM PDT 24 152522072 ps
T96 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3943740182 Mar 21 03:02:32 PM PDT 24 Mar 21 03:02:33 PM PDT 24 26024499 ps
T126 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1452844582 Mar 21 03:04:07 PM PDT 24 Mar 21 03:04:09 PM PDT 24 68378123 ps
T935 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1740685247 Mar 21 03:03:30 PM PDT 24 Mar 21 03:03:31 PM PDT 24 33346133 ps
T105 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1300355858 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:05 PM PDT 24 12704659 ps
T936 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.657617952 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:47 PM PDT 24 408747244 ps
T107 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.152297127 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:37 PM PDT 24 148215435 ps
T72 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2807107933 Mar 21 03:02:53 PM PDT 24 Mar 21 03:02:56 PM PDT 24 207805842 ps
T73 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3303932362 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:44 PM PDT 24 13095291 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1118076432 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:24 PM PDT 24 258592087 ps
T75 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3846882587 Mar 21 03:04:10 PM PDT 24 Mar 21 03:04:15 PM PDT 24 4938995095 ps
T97 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2593419872 Mar 21 03:02:23 PM PDT 24 Mar 21 03:02:23 PM PDT 24 17047544 ps
T937 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.114489112 Mar 21 03:03:59 PM PDT 24 Mar 21 03:04:02 PM PDT 24 101675464 ps
T938 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.870395014 Mar 21 03:02:53 PM PDT 24 Mar 21 03:02:56 PM PDT 24 121782594 ps
T108 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3381779135 Mar 21 03:03:44 PM PDT 24 Mar 21 03:03:46 PM PDT 24 177559036 ps
T939 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2858177047 Mar 21 03:03:37 PM PDT 24 Mar 21 03:03:37 PM PDT 24 15337713 ps
T109 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3426405077 Mar 21 03:03:54 PM PDT 24 Mar 21 03:03:57 PM PDT 24 1046002842 ps
T940 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3144212689 Mar 21 03:03:34 PM PDT 24 Mar 21 03:03:36 PM PDT 24 58435679 ps
T134 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2369910535 Mar 21 03:03:44 PM PDT 24 Mar 21 03:03:46 PM PDT 24 192955869 ps
T941 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4012610280 Mar 21 03:02:32 PM PDT 24 Mar 21 03:02:33 PM PDT 24 86704400 ps
T98 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2360812364 Mar 21 03:03:03 PM PDT 24 Mar 21 03:03:08 PM PDT 24 3801470511 ps
T942 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.377612636 Mar 21 03:02:14 PM PDT 24 Mar 21 03:02:15 PM PDT 24 141576761 ps
T943 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3219334359 Mar 21 03:03:20 PM PDT 24 Mar 21 03:03:22 PM PDT 24 32382801 ps
T944 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1679399605 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:35 PM PDT 24 15769734 ps
T945 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1716930515 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:05 PM PDT 24 26806396 ps
T946 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.177005004 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:06 PM PDT 24 126751659 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4023315239 Mar 21 03:02:51 PM PDT 24 Mar 21 03:02:53 PM PDT 24 28928532 ps
T76 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4254114785 Mar 21 03:04:07 PM PDT 24 Mar 21 03:04:08 PM PDT 24 17708934 ps
T948 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.149313272 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:22 PM PDT 24 26622351 ps
T949 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1191612932 Mar 21 03:03:54 PM PDT 24 Mar 21 03:03:58 PM PDT 24 184116221 ps
T77 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1697391327 Mar 21 03:02:01 PM PDT 24 Mar 21 03:02:03 PM PDT 24 14665258 ps
T950 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2110245927 Mar 21 03:03:03 PM PDT 24 Mar 21 03:03:04 PM PDT 24 31214550 ps
T951 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.231945231 Mar 21 03:04:07 PM PDT 24 Mar 21 03:04:08 PM PDT 24 51713971 ps
T82 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.151682554 Mar 21 03:01:38 PM PDT 24 Mar 21 03:01:40 PM PDT 24 801926132 ps
T952 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.243564124 Mar 21 03:02:33 PM PDT 24 Mar 21 03:02:34 PM PDT 24 19269963 ps
T953 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.322020947 Mar 21 03:02:33 PM PDT 24 Mar 21 03:02:33 PM PDT 24 30314511 ps
T83 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.95204570 Mar 21 03:03:02 PM PDT 24 Mar 21 03:03:05 PM PDT 24 821218486 ps
T954 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3188949240 Mar 21 03:02:51 PM PDT 24 Mar 21 03:02:51 PM PDT 24 93137001 ps
T84 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2733929558 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:38 PM PDT 24 884271581 ps
T955 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.518490455 Mar 21 03:03:19 PM PDT 24 Mar 21 03:03:21 PM PDT 24 11447159 ps
T956 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2209073717 Mar 21 03:03:20 PM PDT 24 Mar 21 03:03:24 PM PDT 24 162392490 ps
T957 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1337516370 Mar 21 03:03:22 PM PDT 24 Mar 21 03:03:27 PM PDT 24 222789068 ps
T958 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.980130326 Mar 21 03:02:13 PM PDT 24 Mar 21 03:02:16 PM PDT 24 150527731 ps
T959 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2223902649 Mar 21 03:02:02 PM PDT 24 Mar 21 03:02:03 PM PDT 24 40638719 ps
T960 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3691481580 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:36 PM PDT 24 35635108 ps
T85 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.695576619 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:36 PM PDT 24 37995386 ps
T138 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3694210899 Mar 21 03:03:02 PM PDT 24 Mar 21 03:03:03 PM PDT 24 307707161 ps
T961 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1264380028 Mar 21 03:03:22 PM PDT 24 Mar 21 03:03:24 PM PDT 24 11899479 ps
T962 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3436581710 Mar 21 03:03:35 PM PDT 24 Mar 21 03:03:36 PM PDT 24 74623069 ps
T90 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2718510620 Mar 21 03:03:53 PM PDT 24 Mar 21 03:03:55 PM PDT 24 1939956361 ps
T89 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4210361293 Mar 21 03:03:20 PM PDT 24 Mar 21 03:03:24 PM PDT 24 352665033 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.68098819 Mar 21 03:02:51 PM PDT 24 Mar 21 03:02:53 PM PDT 24 14413306 ps
T964 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2752340314 Mar 21 03:03:19 PM PDT 24 Mar 21 03:03:20 PM PDT 24 125606547 ps
T965 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2631970163 Mar 21 03:03:36 PM PDT 24 Mar 21 03:03:36 PM PDT 24 14940682 ps
T966 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3948331934 Mar 21 03:03:03 PM PDT 24 Mar 21 03:03:04 PM PDT 24 16398008 ps
T967 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4146760229 Mar 21 03:03:31 PM PDT 24 Mar 21 03:03:31 PM PDT 24 132220812 ps
T968 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2497065095 Mar 21 03:03:30 PM PDT 24 Mar 21 03:03:32 PM PDT 24 21115903 ps
T969 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2445090094 Mar 21 03:02:31 PM PDT 24 Mar 21 03:02:34 PM PDT 24 122356879 ps
T970 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1956078952 Mar 21 03:03:20 PM PDT 24 Mar 21 03:03:24 PM PDT 24 120670087 ps
T91 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3083252384 Mar 21 03:03:03 PM PDT 24 Mar 21 03:03:05 PM PDT 24 265814247 ps
T971 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.196522615 Mar 21 03:02:51 PM PDT 24 Mar 21 03:02:52 PM PDT 24 31354963 ps
T972 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3739816523 Mar 21 03:03:54 PM PDT 24 Mar 21 03:03:55 PM PDT 24 95313849 ps
T973 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.883225875 Mar 21 03:02:52 PM PDT 24 Mar 21 03:02:54 PM PDT 24 78069789 ps
T974 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3459097801 Mar 21 03:03:44 PM PDT 24 Mar 21 03:03:45 PM PDT 24 93743435 ps
T975 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.51934322 Mar 21 03:03:22 PM PDT 24 Mar 21 03:03:24 PM PDT 24 17329831 ps
T128 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4154996396 Mar 21 03:01:47 PM PDT 24 Mar 21 03:01:49 PM PDT 24 193418567 ps
T976 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1479059338 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:45 PM PDT 24 54569529 ps
T977 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1048257755 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:44 PM PDT 24 54670054 ps
T978 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3781926653 Mar 21 03:03:52 PM PDT 24 Mar 21 03:03:53 PM PDT 24 20381765 ps
T979 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3102884453 Mar 21 03:03:33 PM PDT 24 Mar 21 03:03:36 PM PDT 24 1618472952 ps
T135 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3829241732 Mar 21 03:03:03 PM PDT 24 Mar 21 03:03:05 PM PDT 24 242993804 ps
T980 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3295029629 Mar 21 03:04:08 PM PDT 24 Mar 21 03:04:09 PM PDT 24 40774671 ps
T981 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3862001932 Mar 21 03:02:53 PM PDT 24 Mar 21 03:02:57 PM PDT 24 285580300 ps
T982 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3852176698 Mar 21 03:04:09 PM PDT 24 Mar 21 03:04:11 PM PDT 24 142072851 ps
T983 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4055939451 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:23 PM PDT 24 62592379 ps
T129 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.962460164 Mar 21 03:04:08 PM PDT 24 Mar 21 03:04:10 PM PDT 24 562250613 ps
T984 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.193170090 Mar 21 03:02:23 PM PDT 24 Mar 21 03:02:25 PM PDT 24 44132449 ps
T985 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2105506254 Mar 21 03:02:52 PM PDT 24 Mar 21 03:02:53 PM PDT 24 21066345 ps
T986 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3302936121 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:04 PM PDT 24 14254769 ps
T987 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2079588952 Mar 21 03:03:04 PM PDT 24 Mar 21 03:03:09 PM PDT 24 74262669 ps
T988 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2360993297 Mar 21 03:03:44 PM PDT 24 Mar 21 03:03:48 PM PDT 24 36829111 ps
T989 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1005254405 Mar 21 03:03:02 PM PDT 24 Mar 21 03:03:03 PM PDT 24 20079699 ps
T132 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3728487646 Mar 21 03:03:44 PM PDT 24 Mar 21 03:03:46 PM PDT 24 235273135 ps
T990 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.523232178 Mar 21 03:02:41 PM PDT 24 Mar 21 03:02:43 PM PDT 24 91692725 ps
T991 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1678018942 Mar 21 03:03:21 PM PDT 24 Mar 21 03:03:23 PM PDT 24 16330756 ps
T992 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3097793176 Mar 21 03:02:31 PM PDT 24 Mar 21 03:02:32 PM PDT 24 17839404 ps
T92 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2728733965 Mar 21 03:02:13 PM PDT 24 Mar 21 03:02:17 PM PDT 24 4139692148 ps
T993 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2641100139 Mar 21 03:03:25 PM PDT 24 Mar 21 03:03:29 PM PDT 24 323280551 ps
T131 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1106327401 Mar 21 03:03:26 PM PDT 24 Mar 21 03:03:28 PM PDT 24 402173763 ps
T994 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3376971117 Mar 21 03:02:43 PM PDT 24 Mar 21 03:02:44 PM PDT 24 14510344 ps
T995 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3076183356 Mar 21 03:02:41 PM PDT 24 Mar 21 03:02:43 PM PDT 24 413250094 ps
T94 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1735097483 Mar 21 03:02:10 PM PDT 24 Mar 21 03:02:11 PM PDT 24 26506048 ps
T996 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2538351169 Mar 21 03:03:38 PM PDT 24 Mar 21 03:03:41 PM PDT 24 119009661 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.625587235 Mar 21 03:02:42 PM PDT 24 Mar 21 03:02:43 PM PDT 24 93692964 ps
T998 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4152811901 Mar 21 03:04:08 PM PDT 24 Mar 21 03:04:09 PM PDT 24 93489679 ps
T137 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2793749837 Mar 21 03:03:20 PM PDT 24 Mar 21 03:03:23 PM PDT 24 217007470 ps
T999 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1246514909 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:26 PM PDT 24 612903319 ps
T1000 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3443441658 Mar 21 03:03:29 PM PDT 24 Mar 21 03:03:29 PM PDT 24 15003230 ps
T1001 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3038120471 Mar 21 03:03:43 PM PDT 24 Mar 21 03:03:44 PM PDT 24 96095308 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2749754896 Mar 21 03:01:47 PM PDT 24 Mar 21 03:01:50 PM PDT 24 31475848 ps
T136 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.979974250 Mar 21 03:03:22 PM PDT 24 Mar 21 03:03:25 PM PDT 24 208704181 ps
T1003 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1862338690 Mar 21 03:03:46 PM PDT 24 Mar 21 03:03:47 PM PDT 24 37214899 ps
T1004 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3076462027 Mar 21 03:02:14 PM PDT 24 Mar 21 03:02:15 PM PDT 24 69155513 ps
T1005 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2752182880 Mar 21 03:02:22 PM PDT 24 Mar 21 03:02:23 PM PDT 24 57527059 ps
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