Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145966468	1			T1	277844		T2	36864		T3	8700
instr_valid_dis	112910876	1			T1	277844		T2	36864		T3	8700
instr_en	24284453	1			T18	200370		T7	140960		T8	366168

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10426909	1			T18	62912		T7	64134		T8	152018
sram_ifetch_valid_disable	113629639	1			T1	277844		T2	36864		T3	8700
sram_ifetch_enable	21909920	1			T18	343102		T7	656970		T8	69364

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145966468	1			T1	277844		T2	36864		T3	8700
hw_debug_en_valid_off	111657629	1			T1	277844		T2	36864		T3	8700
hw_debug_en_on	23249398	1			T18	322248		T7	693522		T8	206492

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113629639	1			T1	277844		T2	36864		T3	8700
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99586004	1			T1	277844		T2	36864		T3	8700
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10970422	1			T18	71416		T7	46256		T8	144786
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3711122	1			T18	62912		T8	96490		T27	39100
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1388858	1			T18	62912		T27	39100		T147	29604
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1492086	1			T8	96490		T139	20000		T135	25938
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4348244	1			T7	64134		T8	27410		T31	28374
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2013174	1			T7	64134		T31	28374		T42	24390
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1830078	1			T8	27410		T62	9738		T40	10154
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9749290	1			T18	92358		T7	110810		T8	144786
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3599346	1			T18	28650		T7	94492		T31	39368
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4599624	1			T18	23126		T8	144786		T26	222

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9171354	1			T18	128954		T7	94704		T8	69364
lc_exec_en	9151864	1			T18	229890		T7	518578		T8	34296
valid_exec_dis	108304003	1			T1	277844		T2	36864		T3	8700
invalid_exec_dis	32336829	1			T18	406014		T7	721104		T8	221382