Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.81	97.10	100.00	100.00	98.58	99.70	98.52

Total tests in report: 1032

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
77.60	77.60	95.61	95.61	69.92	69.92	85.77	85.77	71.43	71.43	85.06	85.06	94.45	94.45	41.00	41.00	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.768171882
88.49	10.88	97.95	2.34	85.44	15.52	94.99	9.23	100.00	28.57	94.54	9.48	94.90	0.45	51.58	10.58	/workspace/coverage/default/47.sram_ctrl_stress_all.3933178761
92.76	4.28	98.05	0.10	89.42	3.98	95.64	0.64	100.00	0.00	95.40	0.86	96.25	1.35	74.58	23.01	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2616314821
93.99	1.23	98.44	0.39	91.76	2.34	96.78	1.14	100.00	0.00	97.13	1.72	96.85	0.60	76.99	2.41	/workspace/coverage/default/0.sram_ctrl_sec_cm.2469430619
95.10	1.11	98.44	0.00	91.76	0.00	97.85	1.07	100.00	0.00	97.13	0.00	96.85	0.00	83.67	6.68	/workspace/coverage/default/20.sram_ctrl_stress_all.3386221804
95.89	0.79	98.44	0.00	92.45	0.69	97.85	0.00	100.00	0.00	97.13	0.00	96.85	0.00	88.50	4.82	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2753153725
96.61	0.72	99.71	1.27	93.27	0.82	98.35	0.50	100.00	0.00	98.85	1.72	97.00	0.15	89.05	0.56	/workspace/coverage/default/2.sram_ctrl_alert_test.3283495828
97.11	0.50	99.71	0.00	93.82	0.55	98.71	0.36	100.00	0.00	98.85	0.00	97.00	0.00	91.65	2.60	/workspace/coverage/default/4.sram_ctrl_regwen.171788412
97.37	0.27	99.71	0.00	94.09	0.27	99.03	0.32	100.00	0.00	98.85	0.00	97.90	0.90	92.02	0.37	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3614387650
97.61	0.24	99.71	0.00	94.09	0.00	99.03	0.00	100.00	0.00	98.85	0.00	97.90	0.00	93.69	1.67	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.583187773
97.82	0.21	99.71	0.00	94.09	0.00	99.03	0.00	100.00	0.00	98.85	0.00	97.90	0.00	95.18	1.48	/workspace/coverage/default/32.sram_ctrl_regwen.965228062
98.03	0.21	99.71	0.00	94.37	0.27	99.21	0.18	100.00	0.00	98.85	0.00	98.35	0.45	95.73	0.56	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.650956454
98.21	0.18	99.71	0.00	94.37	0.00	99.28	0.07	100.00	0.00	98.85	0.00	99.55	1.20	95.73	0.00	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2308016011
98.35	0.13	99.71	0.00	94.37	0.00	99.28	0.00	100.00	0.00	98.85	0.00	99.55	0.00	96.66	0.93	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.950884048
98.46	0.12	99.80	0.10	94.37	0.00	100.00	0.72	100.00	0.00	98.85	0.00	99.55	0.00	96.66	0.00	/workspace/coverage/default/13.sram_ctrl_ram_cfg.358276379
98.54	0.08	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.55	0.00	97.22	0.56	/workspace/coverage/default/13.sram_ctrl_regwen.1487874951
98.62	0.08	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.55	0.00	97.77	0.56	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1382732242
98.67	0.05	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.55	0.00	98.14	0.37	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3309023507
98.70	0.03	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.55	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3150975543
98.73	0.03	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.55	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3588722991
98.75	0.02	99.80	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.85	0.00	99.70	0.15	98.52	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2249649101

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3461064244
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1361150332
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.752803587
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1799359587
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2024245181
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1420949035
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1679574108
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2006646980
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.253179135
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1311044694
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1766155976
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3078614868
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4018893874
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.183022802
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1617855404
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3626860992
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4020313181
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1427586942
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3514018087
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2605416025
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.752358575
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3187954160
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1839752331
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.671045344
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1192922119
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3306529968
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.873997279
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2450766512
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2604417802
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2349032585
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.635088355
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2556223872
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2931072147
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1051575784
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3951210125
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3384818536
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3106062422
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1143215684
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.277549320
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2311899112
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3367612248
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1682299850
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.751744309
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2389638034
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2031315958
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3213430592
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2955342918
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2428919818
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4276401824
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1600076204
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.311353177
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.359207798
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.705748907
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1091977076
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1287410778
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1161355132
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4253803882
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1702792398
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.248038721
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.456155949
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.311102592
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1339615182
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3925475155
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.489928790
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3039151377
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.990967600
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3560895281
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2122628221
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2461043850
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2551505921
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.360671731
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3392324252
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.829893557
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4091596703
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3311637633
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.561528660
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.954041474
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2484533310
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2345110629
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1398825148
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4119773874
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1017323715
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2009555909
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2113146243
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1990533096
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3839854983
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.237040320
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1240838006
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1886885335
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2418942008
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3515114311
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1259983402
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.249787703
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2248862227
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3297683662
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1222717914
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.500850123
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3505982003
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1658074181
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3610222932
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.725127742
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.915414510
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2529177113
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2280012898
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3388715091
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3745977140
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3537354858
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.945421333
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3123499544
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3930610537
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1631092582
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2227953738
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2267045702
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3436964508
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2465241282
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.896787542
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3485284736
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2155754918
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2627960513
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1525649102
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4227224237
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4290187619
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1619649021
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1101705286
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2780724155
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3206013249
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.636879101
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.413095921
/workspace/coverage/default/0.sram_ctrl_alert_test.3504365468
/workspace/coverage/default/0.sram_ctrl_bijection.3068994197
/workspace/coverage/default/0.sram_ctrl_executable.2089920508
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2447678008
/workspace/coverage/default/0.sram_ctrl_max_throughput.3027089108
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1310491841
/workspace/coverage/default/0.sram_ctrl_mem_walk.1094382126
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1416070289
/workspace/coverage/default/0.sram_ctrl_partial_access.1805101744
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1568319324
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3572688222
/workspace/coverage/default/0.sram_ctrl_regwen.1221133934
/workspace/coverage/default/0.sram_ctrl_smoke.4273831999
/workspace/coverage/default/0.sram_ctrl_stress_all.3157034406
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1003229968
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3884665858
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1402259274
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2688775135
/workspace/coverage/default/1.sram_ctrl_alert_test.3852062882
/workspace/coverage/default/1.sram_ctrl_bijection.3937346498
/workspace/coverage/default/1.sram_ctrl_executable.2936295956
/workspace/coverage/default/1.sram_ctrl_lc_escalation.4072020301
/workspace/coverage/default/1.sram_ctrl_max_throughput.1700630546
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.920366573
/workspace/coverage/default/1.sram_ctrl_mem_walk.1628621017
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2980886821
/workspace/coverage/default/1.sram_ctrl_partial_access.1181267183
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2239236113
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3991501081
/workspace/coverage/default/1.sram_ctrl_regwen.3066669584
/workspace/coverage/default/1.sram_ctrl_sec_cm.3559034144
/workspace/coverage/default/1.sram_ctrl_smoke.2221334607
/workspace/coverage/default/1.sram_ctrl_stress_all.2926049110
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2674124167
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2357754257
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3439803427
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.75142531
/workspace/coverage/default/10.sram_ctrl_alert_test.2799200550
/workspace/coverage/default/10.sram_ctrl_bijection.45698149
/workspace/coverage/default/10.sram_ctrl_executable.755759408
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3918362929
/workspace/coverage/default/10.sram_ctrl_max_throughput.2185507542
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3625467871
/workspace/coverage/default/10.sram_ctrl_mem_walk.1259702006
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2957956468
/workspace/coverage/default/10.sram_ctrl_partial_access.2044394853
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4183147371
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1186226007
/workspace/coverage/default/10.sram_ctrl_regwen.1683614794
/workspace/coverage/default/10.sram_ctrl_smoke.3425428656
/workspace/coverage/default/10.sram_ctrl_stress_all.831851796
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2704948131
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2662465300
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.493594203
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2619123918
/workspace/coverage/default/11.sram_ctrl_alert_test.3678195137
/workspace/coverage/default/11.sram_ctrl_bijection.2660600485
/workspace/coverage/default/11.sram_ctrl_executable.3898573251
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2420940279
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/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.605092740
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1922820972
/workspace/coverage/default/42.sram_ctrl_alert_test.629484608
/workspace/coverage/default/42.sram_ctrl_bijection.931833692
/workspace/coverage/default/42.sram_ctrl_executable.3139939065
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3154656793
/workspace/coverage/default/42.sram_ctrl_max_throughput.2972143175
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2512872968
/workspace/coverage/default/42.sram_ctrl_mem_walk.2306301780
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3833307027
/workspace/coverage/default/42.sram_ctrl_partial_access.881696531
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2105330958
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2809363694
/workspace/coverage/default/42.sram_ctrl_regwen.576769579
/workspace/coverage/default/42.sram_ctrl_smoke.4205852715
/workspace/coverage/default/42.sram_ctrl_stress_all.1675040096
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2507442643
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4010008196
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.110252274
/workspace/coverage/default/43.sram_ctrl_alert_test.2292884458
/workspace/coverage/default/43.sram_ctrl_bijection.1599470304
/workspace/coverage/default/43.sram_ctrl_executable.1318296215
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3565241453
/workspace/coverage/default/43.sram_ctrl_max_throughput.3134621363
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4284666120
/workspace/coverage/default/43.sram_ctrl_mem_walk.3690168024
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1260361297
/workspace/coverage/default/43.sram_ctrl_partial_access.969592524
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2688928609
/workspace/coverage/default/43.sram_ctrl_ram_cfg.205752134
/workspace/coverage/default/43.sram_ctrl_regwen.660369245
/workspace/coverage/default/43.sram_ctrl_smoke.164216207
/workspace/coverage/default/43.sram_ctrl_stress_all.3662260981
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.313263307
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3809488587
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4001926162
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2658352521
/workspace/coverage/default/44.sram_ctrl_alert_test.2882288344
/workspace/coverage/default/44.sram_ctrl_bijection.3469702833
/workspace/coverage/default/44.sram_ctrl_executable.3099077605
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1326443460
/workspace/coverage/default/44.sram_ctrl_max_throughput.1289519585
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1439266173
/workspace/coverage/default/44.sram_ctrl_mem_walk.3124987101
/workspace/coverage/default/44.sram_ctrl_multiple_keys.252398942
/workspace/coverage/default/44.sram_ctrl_partial_access.774103930
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2228395204
/workspace/coverage/default/44.sram_ctrl_ram_cfg.4217649285
/workspace/coverage/default/44.sram_ctrl_regwen.1775670871
/workspace/coverage/default/44.sram_ctrl_smoke.978857441
/workspace/coverage/default/44.sram_ctrl_stress_all.3018169433
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2366149760
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1847827609
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3283431990
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3246800932
/workspace/coverage/default/45.sram_ctrl_alert_test.2737983501
/workspace/coverage/default/45.sram_ctrl_bijection.3271230089
/workspace/coverage/default/45.sram_ctrl_executable.1159007930
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2148648485
/workspace/coverage/default/45.sram_ctrl_max_throughput.1474047708
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3342723417
/workspace/coverage/default/45.sram_ctrl_mem_walk.4278068685
/workspace/coverage/default/45.sram_ctrl_partial_access.1863656857
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2712614771
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3717514385
/workspace/coverage/default/45.sram_ctrl_regwen.3522099858
/workspace/coverage/default/45.sram_ctrl_smoke.582998177
/workspace/coverage/default/45.sram_ctrl_stress_all.1445568084
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3634917948
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1223015353
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2815901809
/workspace/coverage/default/46.sram_ctrl_alert_test.507757186
/workspace/coverage/default/46.sram_ctrl_bijection.351963513
/workspace/coverage/default/46.sram_ctrl_executable.1018966182
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3769507075
/workspace/coverage/default/46.sram_ctrl_max_throughput.3203591728
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3205169626
/workspace/coverage/default/46.sram_ctrl_mem_walk.461727348
/workspace/coverage/default/46.sram_ctrl_multiple_keys.395302059
/workspace/coverage/default/46.sram_ctrl_partial_access.525805835
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3690951244
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1062206578
/workspace/coverage/default/46.sram_ctrl_regwen.625292326
/workspace/coverage/default/46.sram_ctrl_smoke.1953626643
/workspace/coverage/default/46.sram_ctrl_stress_all.1441943188
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3989916274
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1495803492
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2909447813
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3795404646
/workspace/coverage/default/47.sram_ctrl_alert_test.2886535940
/workspace/coverage/default/47.sram_ctrl_bijection.1370492822
/workspace/coverage/default/47.sram_ctrl_executable.3163276768
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2231193558
/workspace/coverage/default/47.sram_ctrl_max_throughput.3488265480
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1684188668
/workspace/coverage/default/47.sram_ctrl_mem_walk.1222424121
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1979380284
/workspace/coverage/default/47.sram_ctrl_partial_access.810757384
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2221333877
/workspace/coverage/default/47.sram_ctrl_ram_cfg.711351614
/workspace/coverage/default/47.sram_ctrl_regwen.1308139773
/workspace/coverage/default/47.sram_ctrl_smoke.4149325553
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.476479081
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1067780094
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3664260821
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4144524507
/workspace/coverage/default/48.sram_ctrl_alert_test.3010015291
/workspace/coverage/default/48.sram_ctrl_bijection.3250242876
/workspace/coverage/default/48.sram_ctrl_executable.766150962
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3549524057
/workspace/coverage/default/48.sram_ctrl_max_throughput.2766207482
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3088072488
/workspace/coverage/default/48.sram_ctrl_mem_walk.1927310438
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2051693070
/workspace/coverage/default/48.sram_ctrl_partial_access.3027937629
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2140387760
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2705998781
/workspace/coverage/default/48.sram_ctrl_regwen.2406444721
/workspace/coverage/default/48.sram_ctrl_smoke.1222657716
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3845644960
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2861193936
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.4168095300
/workspace/coverage/default/49.sram_ctrl_alert_test.3727561647
/workspace/coverage/default/49.sram_ctrl_bijection.2332463195
/workspace/coverage/default/49.sram_ctrl_executable.2986084527
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2551373975
/workspace/coverage/default/49.sram_ctrl_max_throughput.2440954418
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1796143603
/workspace/coverage/default/49.sram_ctrl_mem_walk.3120823870
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3041119312
/workspace/coverage/default/49.sram_ctrl_partial_access.41748624
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1744135871
/workspace/coverage/default/49.sram_ctrl_ram_cfg.187178725
/workspace/coverage/default/49.sram_ctrl_regwen.4095180339
/workspace/coverage/default/49.sram_ctrl_smoke.1532516589
/workspace/coverage/default/49.sram_ctrl_stress_all.3890997333
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3289942621
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1272537702
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1176612286
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2235888127
/workspace/coverage/default/5.sram_ctrl_alert_test.3262336145
/workspace/coverage/default/5.sram_ctrl_bijection.3524745269
/workspace/coverage/default/5.sram_ctrl_executable.2751680867
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3358611622
/workspace/coverage/default/5.sram_ctrl_max_throughput.2454285820
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1315878924
/workspace/coverage/default/5.sram_ctrl_mem_walk.362011139
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1012028157
/workspace/coverage/default/5.sram_ctrl_partial_access.1198960950
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4237332024
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3179314795
/workspace/coverage/default/5.sram_ctrl_regwen.945324736
/workspace/coverage/default/5.sram_ctrl_smoke.484766576
/workspace/coverage/default/5.sram_ctrl_stress_all.3513746968
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4242010977
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2823989394
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3342580104
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2280457730
/workspace/coverage/default/6.sram_ctrl_alert_test.1502905752
/workspace/coverage/default/6.sram_ctrl_bijection.2540512098
/workspace/coverage/default/6.sram_ctrl_executable.3177151540
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3625040175
/workspace/coverage/default/6.sram_ctrl_max_throughput.1384588708
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2792430249
/workspace/coverage/default/6.sram_ctrl_mem_walk.3914099316
/workspace/coverage/default/6.sram_ctrl_multiple_keys.815612857
/workspace/coverage/default/6.sram_ctrl_partial_access.1932604357
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.942944159
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2621756557
/workspace/coverage/default/6.sram_ctrl_regwen.3204677600
/workspace/coverage/default/6.sram_ctrl_smoke.3159466262
/workspace/coverage/default/6.sram_ctrl_stress_all.4279978364
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.675663442
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1010894690
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1495810507
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3264033101
/workspace/coverage/default/7.sram_ctrl_alert_test.509750738
/workspace/coverage/default/7.sram_ctrl_bijection.4042557046
/workspace/coverage/default/7.sram_ctrl_executable.788757992
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2774731220
/workspace/coverage/default/7.sram_ctrl_max_throughput.1564188907
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3711879876
/workspace/coverage/default/7.sram_ctrl_mem_walk.53727965
/workspace/coverage/default/7.sram_ctrl_multiple_keys.443707442
/workspace/coverage/default/7.sram_ctrl_partial_access.4209379786
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.179068518
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1342776606
/workspace/coverage/default/7.sram_ctrl_regwen.1975378396
/workspace/coverage/default/7.sram_ctrl_smoke.911004747
/workspace/coverage/default/7.sram_ctrl_stress_all.2470059406
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1624124549
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4231717369
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2495915275
/workspace/coverage/default/8.sram_ctrl_alert_test.1495222835
/workspace/coverage/default/8.sram_ctrl_bijection.821631611
/workspace/coverage/default/8.sram_ctrl_executable.2864918254
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2672291710
/workspace/coverage/default/8.sram_ctrl_max_throughput.2396897803
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2766127951
/workspace/coverage/default/8.sram_ctrl_mem_walk.1686887665
/workspace/coverage/default/8.sram_ctrl_multiple_keys.24708385
/workspace/coverage/default/8.sram_ctrl_partial_access.3654075590
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3477354628
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3405368181
/workspace/coverage/default/8.sram_ctrl_regwen.1622762700
/workspace/coverage/default/8.sram_ctrl_smoke.3998884773
/workspace/coverage/default/8.sram_ctrl_stress_all.765609545
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973528918
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1202677515
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3409211253
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3357539186
/workspace/coverage/default/9.sram_ctrl_alert_test.4023988649
/workspace/coverage/default/9.sram_ctrl_bijection.111749912
/workspace/coverage/default/9.sram_ctrl_executable.1794033527
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1497624121
/workspace/coverage/default/9.sram_ctrl_max_throughput.2139986122
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.329536893
/workspace/coverage/default/9.sram_ctrl_mem_walk.3104008199
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2758099367
/workspace/coverage/default/9.sram_ctrl_partial_access.3240164061
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3048439458
/workspace/coverage/default/9.sram_ctrl_ram_cfg.96569249
/workspace/coverage/default/9.sram_ctrl_regwen.2590933211
/workspace/coverage/default/9.sram_ctrl_smoke.1009547349
/workspace/coverage/default/9.sram_ctrl_stress_all.1667691486
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.477161690
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.681983055
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2108912174

Total test records in report: 1032

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3614387650	Mar 24 01:17:55 PM PDT 24	Mar 24 01:26:24 PM PDT 24	10990742388 ps
T2	/workspace/coverage/default/24.sram_ctrl_bijection.3120835878	Mar 24 01:18:13 PM PDT 24	Mar 24 01:18:42 PM PDT 24	5296886688 ps
T3	/workspace/coverage/default/9.sram_ctrl_partial_access.3240164061	Mar 24 01:17:26 PM PDT 24	Mar 24 01:17:55 PM PDT 24	700553427 ps
T4	/workspace/coverage/default/28.sram_ctrl_multiple_keys.382111415	Mar 24 01:18:17 PM PDT 24	Mar 24 01:37:20 PM PDT 24	3042418738 ps
T10	/workspace/coverage/default/31.sram_ctrl_max_throughput.2309380212	Mar 24 01:18:34 PM PDT 24	Mar 24 01:20:33 PM PDT 24	139922623 ps
T11	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.768171882	Mar 24 01:17:24 PM PDT 24	Mar 24 01:22:54 PM PDT 24	27424952804 ps
T12	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3491135050	Mar 24 01:17:35 PM PDT 24	Mar 24 01:19:20 PM PDT 24	557502623 ps
T13	/workspace/coverage/default/2.sram_ctrl_alert_test.3283495828	Mar 24 01:17:05 PM PDT 24	Mar 24 01:17:06 PM PDT 24	15283880 ps
T5	/workspace/coverage/default/44.sram_ctrl_mem_walk.3124987101	Mar 24 01:19:38 PM PDT 24	Mar 24 01:19:44 PM PDT 24	2152871881 ps
T14	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3707399393	Mar 24 01:18:29 PM PDT 24	Mar 24 01:22:14 PM PDT 24	3991392029 ps
T6	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.765350830	Mar 24 01:18:32 PM PDT 24	Mar 24 01:18:38 PM PDT 24	727663050 ps
T16	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1010894690	Mar 24 01:17:21 PM PDT 24	Mar 24 01:19:49 PM PDT 24	11634956074 ps
T17	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4194610644	Mar 24 01:18:04 PM PDT 24	Mar 24 01:20:56 PM PDT 24	13597498891 ps
T32	/workspace/coverage/default/46.sram_ctrl_ram_cfg.1062206578	Mar 24 01:19:45 PM PDT 24	Mar 24 01:19:46 PM PDT 24	46869638 ps
T18	/workspace/coverage/default/1.sram_ctrl_executable.2936295956	Mar 24 01:16:41 PM PDT 24	Mar 24 01:46:14 PM PDT 24	5043545948 ps
T73	/workspace/coverage/default/40.sram_ctrl_multiple_keys.1719467969	Mar 24 01:19:13 PM PDT 24	Mar 24 01:40:46 PM PDT 24	14103002927 ps
T33	/workspace/coverage/default/8.sram_ctrl_ram_cfg.3405368181	Mar 24 01:17:27 PM PDT 24	Mar 24 01:17:28 PM PDT 24	76119478 ps
T7	/workspace/coverage/default/20.sram_ctrl_stress_all.3386221804	Mar 24 01:17:59 PM PDT 24	Mar 24 02:31:39 PM PDT 24	201661485815 ps
T8	/workspace/coverage/default/47.sram_ctrl_stress_all.3933178761	Mar 24 01:19:51 PM PDT 24	Mar 24 01:43:52 PM PDT 24	66556023848 ps
T15	/workspace/coverage/default/41.sram_ctrl_multiple_keys.2409157770	Mar 24 01:19:20 PM PDT 24	Mar 24 01:36:42 PM PDT 24	50763737466 ps
T58	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.661550788	Mar 24 01:18:23 PM PDT 24	Mar 24 01:18:26 PM PDT 24	61648432 ps
T31	/workspace/coverage/default/48.sram_ctrl_regwen.2406444721	Mar 24 01:19:58 PM PDT 24	Mar 24 01:33:16 PM PDT 24	25939654894 ps
T59	/workspace/coverage/default/36.sram_ctrl_bijection.3676869031	Mar 24 01:18:51 PM PDT 24	Mar 24 01:19:20 PM PDT 24	989052250 ps
T19	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.658106266	Mar 24 01:19:03 PM PDT 24	Mar 24 01:34:04 PM PDT 24	3499805031 ps
T60	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2324794316	Mar 24 01:18:20 PM PDT 24	Mar 24 01:18:23 PM PDT 24	371484709 ps
T61	/workspace/coverage/default/33.sram_ctrl_partial_access.691168382	Mar 24 01:18:50 PM PDT 24	Mar 24 01:21:03 PM PDT 24	2495768176 ps
T62	/workspace/coverage/default/42.sram_ctrl_executable.3139939065	Mar 24 01:19:23 PM PDT 24	Mar 24 01:31:49 PM PDT 24	14984010244 ps
T9	/workspace/coverage/default/27.sram_ctrl_lc_escalation.3529783070	Mar 24 01:18:13 PM PDT 24	Mar 24 01:18:19 PM PDT 24	380049727 ps
T110	/workspace/coverage/default/35.sram_ctrl_executable.3103142013	Mar 24 01:18:54 PM PDT 24	Mar 24 01:27:11 PM PDT 24	7863162737 ps
T29	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.650956454	Mar 24 01:17:36 PM PDT 24	Mar 24 01:19:28 PM PDT 24	1876164913 ps
T50	/workspace/coverage/default/38.sram_ctrl_lc_escalation.3040740257	Mar 24 01:19:05 PM PDT 24	Mar 24 01:19:09 PM PDT 24	341617737 ps
T51	/workspace/coverage/default/33.sram_ctrl_max_throughput.1491667017	Mar 24 01:18:44 PM PDT 24	Mar 24 01:19:04 PM PDT 24	347245448 ps
T52	/workspace/coverage/default/10.sram_ctrl_partial_access.2044394853	Mar 24 01:17:25 PM PDT 24	Mar 24 01:17:39 PM PDT 24	1021582919 ps
T53	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3801157177	Mar 24 01:16:53 PM PDT 24	Mar 24 01:20:28 PM PDT 24	2584547987 ps
T54	/workspace/coverage/default/4.sram_ctrl_max_throughput.2552605929	Mar 24 01:16:52 PM PDT 24	Mar 24 01:17:38 PM PDT 24	102297844 ps
T55	/workspace/coverage/default/9.sram_ctrl_mem_walk.3104008199	Mar 24 01:17:25 PM PDT 24	Mar 24 01:17:34 PM PDT 24	530368996 ps
T56	/workspace/coverage/default/27.sram_ctrl_max_throughput.2770118561	Mar 24 01:18:17 PM PDT 24	Mar 24 01:19:07 PM PDT 24	501933000 ps
T57	/workspace/coverage/default/3.sram_ctrl_multiple_keys.1830101322	Mar 24 01:16:53 PM PDT 24	Mar 24 01:17:10 PM PDT 24	287005484 ps
T26	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2817388928	Mar 24 01:17:04 PM PDT 24	Mar 24 01:17:16 PM PDT 24	347439891 ps
T42	/workspace/coverage/default/46.sram_ctrl_regwen.625292326	Mar 24 01:19:46 PM PDT 24	Mar 24 01:33:38 PM PDT 24	55137032648 ps
T23	/workspace/coverage/default/2.sram_ctrl_sec_cm.3300049572	Mar 24 01:16:53 PM PDT 24	Mar 24 01:16:56 PM PDT 24	897708222 ps
T20	/workspace/coverage/default/18.sram_ctrl_alert_test.788533447	Mar 24 01:17:43 PM PDT 24	Mar 24 01:17:44 PM PDT 24	33731335 ps
T34	/workspace/coverage/default/34.sram_ctrl_ram_cfg.2928843763	Mar 24 01:18:48 PM PDT 24	Mar 24 01:18:49 PM PDT 24	57948524 ps
T21	/workspace/coverage/default/42.sram_ctrl_alert_test.629484608	Mar 24 01:19:24 PM PDT 24	Mar 24 01:19:24 PM PDT 24	22211384 ps
T28	/workspace/coverage/default/41.sram_ctrl_lc_escalation.1837690607	Mar 24 01:19:18 PM PDT 24	Mar 24 01:19:23 PM PDT 24	2740405092 ps
T37	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3795404646	Mar 24 01:19:52 PM PDT 24	Mar 24 01:37:52 PM PDT 24	4361084214 ps
T38	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4237332024	Mar 24 01:17:22 PM PDT 24	Mar 24 01:22:42 PM PDT 24	15819229017 ps
T39	/workspace/coverage/default/42.sram_ctrl_partial_access.881696531	Mar 24 01:19:23 PM PDT 24	Mar 24 01:19:54 PM PDT 24	7004866421 ps
T40	/workspace/coverage/default/1.sram_ctrl_stress_all.2926049110	Mar 24 01:16:58 PM PDT 24	Mar 24 01:24:13 PM PDT 24	22825445364 ps
T41	/workspace/coverage/default/15.sram_ctrl_regwen.234182860	Mar 24 01:17:30 PM PDT 24	Mar 24 01:31:32 PM PDT 24	8786295140 ps
T98	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.681983055	Mar 24 01:17:26 PM PDT 24	Mar 24 01:22:06 PM PDT 24	11899205421 ps
T156	/workspace/coverage/default/39.sram_ctrl_smoke.1445190393	Mar 24 01:19:10 PM PDT 24	Mar 24 01:19:16 PM PDT 24	2127906530 ps
T27	/workspace/coverage/default/13.sram_ctrl_regwen.1487874951	Mar 24 01:17:30 PM PDT 24	Mar 24 01:30:59 PM PDT 24	134974052190 ps
T151	/workspace/coverage/default/18.sram_ctrl_executable.2037009623	Mar 24 01:17:40 PM PDT 24	Mar 24 01:35:41 PM PDT 24	45834842744 ps
T22	/workspace/coverage/default/14.sram_ctrl_alert_test.3346611254	Mar 24 01:17:32 PM PDT 24	Mar 24 01:17:33 PM PDT 24	37632303 ps
T162	/workspace/coverage/default/3.sram_ctrl_max_throughput.252723941	Mar 24 01:17:00 PM PDT 24	Mar 24 01:17:38 PM PDT 24	437481871 ps
T163	/workspace/coverage/default/42.sram_ctrl_mem_walk.2306301780	Mar 24 01:19:29 PM PDT 24	Mar 24 01:19:34 PM PDT 24	85660673 ps
T164	/workspace/coverage/default/5.sram_ctrl_max_throughput.2454285820	Mar 24 01:17:21 PM PDT 24	Mar 24 01:17:32 PM PDT 24	242696254 ps
T99	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2105330958	Mar 24 01:19:25 PM PDT 24	Mar 24 01:24:32 PM PDT 24	4355742014 ps
T133	/workspace/coverage/default/11.sram_ctrl_regwen.591818451	Mar 24 01:17:28 PM PDT 24	Mar 24 01:35:36 PM PDT 24	2519524655 ps
T145	/workspace/coverage/default/5.sram_ctrl_partial_access.1198960950	Mar 24 01:17:12 PM PDT 24	Mar 24 01:18:07 PM PDT 24	2071948639 ps
T80	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3246800932	Mar 24 01:19:41 PM PDT 24	Mar 24 01:38:18 PM PDT 24	3272576448 ps
T165	/workspace/coverage/default/40.sram_ctrl_bijection.1778200546	Mar 24 01:19:14 PM PDT 24	Mar 24 01:19:39 PM PDT 24	5542216854 ps
T134	/workspace/coverage/default/44.sram_ctrl_executable.3099077605	Mar 24 01:19:39 PM PDT 24	Mar 24 01:19:51 PM PDT 24	2198165030 ps
T152	/workspace/coverage/default/28.sram_ctrl_ram_cfg.3565007035	Mar 24 01:18:23 PM PDT 24	Mar 24 01:18:24 PM PDT 24	31572989 ps
T129	/workspace/coverage/default/45.sram_ctrl_stress_all.1445568084	Mar 24 01:19:42 PM PDT 24	Mar 24 01:43:05 PM PDT 24	20948344728 ps
T100	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2332179926	Mar 24 01:19:09 PM PDT 24	Mar 24 01:24:26 PM PDT 24	25650315931 ps
T130	/workspace/coverage/default/4.sram_ctrl_regwen.171788412	Mar 24 01:17:09 PM PDT 24	Mar 24 01:33:12 PM PDT 24	27445725860 ps
T131	/workspace/coverage/default/3.sram_ctrl_executable.3413279134	Mar 24 01:16:54 PM PDT 24	Mar 24 01:27:59 PM PDT 24	37974491338 ps
T157	/workspace/coverage/default/0.sram_ctrl_multiple_keys.1416070289	Mar 24 01:16:58 PM PDT 24	Mar 24 01:38:18 PM PDT 24	16557279756 ps
T159	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4273714346	Mar 24 01:17:54 PM PDT 24	Mar 24 01:18:48 PM PDT 24	415587372 ps
T166	/workspace/coverage/default/21.sram_ctrl_alert_test.492735794	Mar 24 01:17:58 PM PDT 24	Mar 24 01:17:59 PM PDT 24	41135340 ps
T139	/workspace/coverage/default/2.sram_ctrl_stress_all.2793149183	Mar 24 01:16:53 PM PDT 24	Mar 24 01:50:36 PM PDT 24	81240742080 ps
T146	/workspace/coverage/default/32.sram_ctrl_partial_access.913063124	Mar 24 01:18:35 PM PDT 24	Mar 24 01:18:38 PM PDT 24	213460813 ps
T101	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1013791517	Mar 24 01:18:10 PM PDT 24	Mar 24 01:23:20 PM PDT 24	3215555184 ps
T167	/workspace/coverage/default/44.sram_ctrl_alert_test.2882288344	Mar 24 01:19:37 PM PDT 24	Mar 24 01:19:38 PM PDT 24	39188669 ps
T149	/workspace/coverage/default/26.sram_ctrl_regwen.726166545	Mar 24 01:18:15 PM PDT 24	Mar 24 01:44:30 PM PDT 24	18708324623 ps
T168	/workspace/coverage/default/29.sram_ctrl_multiple_keys.3652879448	Mar 24 01:18:24 PM PDT 24	Mar 24 01:18:35 PM PDT 24	738459103 ps
T160	/workspace/coverage/default/23.sram_ctrl_multiple_keys.1505967855	Mar 24 01:18:05 PM PDT 24	Mar 24 01:33:08 PM PDT 24	10155324847 ps
T169	/workspace/coverage/default/0.sram_ctrl_mem_walk.1094382126	Mar 24 01:16:44 PM PDT 24	Mar 24 01:16:53 PM PDT 24	451019048 ps
T81	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2951282467	Mar 24 01:17:30 PM PDT 24	Mar 24 01:35:18 PM PDT 24	4588653696 ps
T161	/workspace/coverage/default/33.sram_ctrl_alert_test.1837194864	Mar 24 01:18:49 PM PDT 24	Mar 24 01:18:50 PM PDT 24	34873615 ps
T170	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2698532855	Mar 24 01:18:49 PM PDT 24	Mar 24 01:24:37 PM PDT 24	3928232729 ps
T135	/workspace/coverage/default/32.sram_ctrl_regwen.965228062	Mar 24 01:18:41 PM PDT 24	Mar 24 01:34:47 PM PDT 24	54059145595 ps
T171	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1402259274	Mar 24 01:16:43 PM PDT 24	Mar 24 01:17:18 PM PDT 24	110136434 ps
T82	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.513074981	Mar 24 01:17:40 PM PDT 24	Mar 24 01:17:44 PM PDT 24	102231994 ps
T147	/workspace/coverage/default/5.sram_ctrl_regwen.945324736	Mar 24 01:17:17 PM PDT 24	Mar 24 01:33:19 PM PDT 24	12919187566 ps
T172	/workspace/coverage/default/17.sram_ctrl_alert_test.1801780235	Mar 24 01:17:43 PM PDT 24	Mar 24 01:17:44 PM PDT 24	19248752 ps
T83	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.149106488	Mar 24 01:19:05 PM PDT 24	Mar 24 01:19:08 PM PDT 24	798507655 ps
T153	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3345000466	Mar 24 01:17:27 PM PDT 24	Mar 24 01:17:57 PM PDT 24	102177436 ps
T30	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3389591166	Mar 24 01:18:27 PM PDT 24	Mar 24 01:18:36 PM PDT 24	297742250 ps
T173	/workspace/coverage/default/17.sram_ctrl_partial_access.1618422996	Mar 24 01:17:36 PM PDT 24	Mar 24 01:18:49 PM PDT 24	193341178 ps
T174	/workspace/coverage/default/30.sram_ctrl_multiple_keys.544496192	Mar 24 01:18:29 PM PDT 24	Mar 24 01:20:39 PM PDT 24	18292070255 ps
T175	/workspace/coverage/default/27.sram_ctrl_ram_cfg.3980882118	Mar 24 01:18:14 PM PDT 24	Mar 24 01:18:15 PM PDT 24	93681383 ps
T43	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3289942621	Mar 24 01:20:07 PM PDT 24	Mar 24 01:20:57 PM PDT 24	1025218215 ps
T140	/workspace/coverage/default/18.sram_ctrl_multiple_keys.146425645	Mar 24 01:17:42 PM PDT 24	Mar 24 01:50:42 PM PDT 24	90313193919 ps
T176	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3530077869	Mar 24 01:18:18 PM PDT 24	Mar 24 01:18:50 PM PDT 24	97836036 ps
T177	/workspace/coverage/default/47.sram_ctrl_partial_access.810757384	Mar 24 01:19:47 PM PDT 24	Mar 24 01:19:49 PM PDT 24	56041873 ps
T141	/workspace/coverage/default/34.sram_ctrl_multiple_keys.2422918755	Mar 24 01:18:49 PM PDT 24	Mar 24 01:33:02 PM PDT 24	25150271899 ps
T178	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.274088112	Mar 24 01:17:26 PM PDT 24	Mar 24 01:17:29 PM PDT 24	48561755 ps
T179	/workspace/coverage/default/44.sram_ctrl_multiple_keys.252398942	Mar 24 01:19:33 PM PDT 24	Mar 24 01:32:14 PM PDT 24	1819724730 ps
T180	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.489209643	Mar 24 01:17:38 PM PDT 24	Mar 24 01:19:41 PM PDT 24	838096931 ps
T150	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1123377960	Mar 24 01:18:30 PM PDT 24	Mar 24 01:19:06 PM PDT 24	106635062 ps
T181	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3220480468	Mar 24 01:18:41 PM PDT 24	Mar 24 01:21:30 PM PDT 24	6599876877 ps
T182	/workspace/coverage/default/9.sram_ctrl_smoke.1009547349	Mar 24 01:17:26 PM PDT 24	Mar 24 01:17:29 PM PDT 24	155603948 ps
T183	/workspace/coverage/default/36.sram_ctrl_mem_walk.441552779	Mar 24 01:19:06 PM PDT 24	Mar 24 01:19:11 PM PDT 24	141522630 ps
T148	/workspace/coverage/default/9.sram_ctrl_stress_all.1667691486	Mar 24 01:17:27 PM PDT 24	Mar 24 02:11:34 PM PDT 24	37989267838 ps
T184	/workspace/coverage/default/29.sram_ctrl_ram_cfg.1372706019	Mar 24 01:18:27 PM PDT 24	Mar 24 01:18:28 PM PDT 24	105657614 ps
T185	/workspace/coverage/default/4.sram_ctrl_smoke.3187765619	Mar 24 01:17:00 PM PDT 24	Mar 24 01:17:29 PM PDT 24	415160594 ps
T155	/workspace/coverage/default/39.sram_ctrl_lc_escalation.825728080	Mar 24 01:19:07 PM PDT 24	Mar 24 01:19:13 PM PDT 24	1891541788 ps
T186	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.68635057	Mar 24 01:18:05 PM PDT 24	Mar 24 01:22:39 PM PDT 24	2845496492 ps
T154	/workspace/coverage/default/42.sram_ctrl_stress_all.1675040096	Mar 24 01:19:26 PM PDT 24	Mar 24 01:53:55 PM PDT 24	22425315004 ps
T187	/workspace/coverage/default/2.sram_ctrl_max_throughput.1817289472	Mar 24 01:16:46 PM PDT 24	Mar 24 01:17:18 PM PDT 24	93156501 ps
T188	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3191113450	Mar 24 01:16:59 PM PDT 24	Mar 24 01:21:59 PM PDT 24	14423845560 ps
T189	/workspace/coverage/default/38.sram_ctrl_executable.1702498850	Mar 24 01:19:08 PM PDT 24	Mar 24 01:39:43 PM PDT 24	16568793463 ps
T190	/workspace/coverage/default/49.sram_ctrl_ram_cfg.187178725	Mar 24 01:20:01 PM PDT 24	Mar 24 01:20:02 PM PDT 24	78342332 ps
T191	/workspace/coverage/default/46.sram_ctrl_max_throughput.3203591728	Mar 24 01:19:48 PM PDT 24	Mar 24 01:21:11 PM PDT 24	130832585 ps
T192	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.647884696	Mar 24 01:19:03 PM PDT 24	Mar 24 01:22:21 PM PDT 24	8157811360 ps
T193	/workspace/coverage/default/8.sram_ctrl_alert_test.1495222835	Mar 24 01:17:25 PM PDT 24	Mar 24 01:17:26 PM PDT 24	64161108 ps
T194	/workspace/coverage/default/15.sram_ctrl_bijection.869765913	Mar 24 01:17:31 PM PDT 24	Mar 24 01:17:48 PM PDT 24	556247807 ps
T195	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3409211253	Mar 24 01:17:23 PM PDT 24	Mar 24 01:17:53 PM PDT 24	385997787 ps
T196	/workspace/coverage/default/38.sram_ctrl_partial_access.4170303343	Mar 24 01:19:01 PM PDT 24	Mar 24 01:21:44 PM PDT 24	871368470 ps
T197	/workspace/coverage/default/20.sram_ctrl_mem_walk.803923291	Mar 24 01:17:56 PM PDT 24	Mar 24 01:18:01 PM PDT 24	1275778171 ps
T142	/workspace/coverage/default/32.sram_ctrl_stress_all.2843016413	Mar 24 01:18:41 PM PDT 24	Mar 24 02:03:13 PM PDT 24	166014442042 ps
T198	/workspace/coverage/default/24.sram_ctrl_alert_test.575441656	Mar 24 01:18:14 PM PDT 24	Mar 24 01:18:15 PM PDT 24	19903205 ps
T199	/workspace/coverage/default/9.sram_ctrl_alert_test.4023988649	Mar 24 01:17:25 PM PDT 24	Mar 24 01:17:26 PM PDT 24	13908688 ps
T200	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.905519281	Mar 24 01:17:18 PM PDT 24	Mar 24 01:25:41 PM PDT 24	6827583495 ps
T201	/workspace/coverage/default/35.sram_ctrl_lc_escalation.1411780301	Mar 24 01:18:53 PM PDT 24	Mar 24 01:19:00 PM PDT 24	1611147272 ps
T44	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973528918	Mar 24 01:17:26 PM PDT 24	Mar 24 01:17:47 PM PDT 24	1235675256 ps
T202	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3357539186	Mar 24 01:17:25 PM PDT 24	Mar 24 01:18:08 PM PDT 24	488951214 ps
T203	/workspace/coverage/default/28.sram_ctrl_mem_walk.2018585637	Mar 24 01:18:22 PM PDT 24	Mar 24 01:18:27 PM PDT 24	1430770471 ps
T204	/workspace/coverage/default/34.sram_ctrl_bijection.1383088212	Mar 24 01:18:46 PM PDT 24	Mar 24 01:19:23 PM PDT 24	1829749320 ps
T132	/workspace/coverage/default/36.sram_ctrl_stress_all.3581796985	Mar 24 01:19:02 PM PDT 24	Mar 24 02:16:54 PM PDT 24	77727261305 ps
T205	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1640597691	Mar 24 01:18:25 PM PDT 24	Mar 24 01:18:27 PM PDT 24	171291235 ps
T158	/workspace/coverage/default/35.sram_ctrl_stress_all.3410461290	Mar 24 01:18:52 PM PDT 24	Mar 24 01:48:42 PM PDT 24	10992016896 ps
T206	/workspace/coverage/default/19.sram_ctrl_partial_access.2931077132	Mar 24 01:17:47 PM PDT 24	Mar 24 01:19:53 PM PDT 24	2372338097 ps
T207	/workspace/coverage/default/3.sram_ctrl_smoke.314605971	Mar 24 01:16:57 PM PDT 24	Mar 24 01:17:14 PM PDT 24	750099799 ps
T208	/workspace/coverage/default/0.sram_ctrl_max_throughput.3027089108	Mar 24 01:16:42 PM PDT 24	Mar 24 01:18:28 PM PDT 24	495563426 ps
T209	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.493584238	Mar 24 01:17:34 PM PDT 24	Mar 24 01:20:54 PM PDT 24	8587647162 ps
T210	/workspace/coverage/default/14.sram_ctrl_ram_cfg.2650377260	Mar 24 01:17:31 PM PDT 24	Mar 24 01:17:32 PM PDT 24	85302875 ps
T211	/workspace/coverage/default/18.sram_ctrl_max_throughput.961126195	Mar 24 01:17:41 PM PDT 24	Mar 24 01:18:16 PM PDT 24	176303458 ps
T212	/workspace/coverage/default/14.sram_ctrl_executable.2481402541	Mar 24 01:17:25 PM PDT 24	Mar 24 01:31:48 PM PDT 24	25049438478 ps
T213	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3240295912	Mar 24 01:17:32 PM PDT 24	Mar 24 01:22:02 PM PDT 24	16100939526 ps
T214	/workspace/coverage/default/6.sram_ctrl_multiple_keys.815612857	Mar 24 01:17:25 PM PDT 24	Mar 24 01:25:13 PM PDT 24	11495618042 ps
T215	/workspace/coverage/default/41.sram_ctrl_max_throughput.546366867	Mar 24 01:19:23 PM PDT 24	Mar 24 01:19:53 PM PDT 24	364322430 ps
T216	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3283431990	Mar 24 01:19:44 PM PDT 24	Mar 24 01:22:16 PM PDT 24	621253574 ps
T45	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.52607273	Mar 24 01:18:12 PM PDT 24	Mar 24 01:18:46 PM PDT 24	760075450 ps
T217	/workspace/coverage/default/37.sram_ctrl_regwen.3766365804	Mar 24 01:19:05 PM PDT 24	Mar 24 01:19:13 PM PDT 24	451871488 ps
T218	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1220428222	Mar 24 01:18:11 PM PDT 24	Mar 24 01:40:03 PM PDT 24	6261326610 ps
T219	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2468404779	Mar 24 01:17:57 PM PDT 24	Mar 24 01:21:45 PM PDT 24	10861360628 ps
T220	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3939490053	Mar 24 01:17:36 PM PDT 24	Mar 24 01:17:39 PM PDT 24	297374780 ps
T221	/workspace/coverage/default/40.sram_ctrl_alert_test.2200324832	Mar 24 01:19:14 PM PDT 24	Mar 24 01:19:15 PM PDT 24	43630664 ps
T222	/workspace/coverage/default/27.sram_ctrl_mem_walk.1112648743	Mar 24 01:18:18 PM PDT 24	Mar 24 01:18:27 PM PDT 24	139848256 ps
T223	/workspace/coverage/default/28.sram_ctrl_regwen.3063321581	Mar 24 01:18:18 PM PDT 24	Mar 24 01:33:56 PM PDT 24	3228286151 ps
T224	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.918873605	Mar 24 01:18:26 PM PDT 24	Mar 24 01:18:29 PM PDT 24	353250573 ps
T225	/workspace/coverage/default/6.sram_ctrl_partial_access.1932604357	Mar 24 01:17:24 PM PDT 24	Mar 24 01:17:36 PM PDT 24	219257915 ps
T226	/workspace/coverage/default/16.sram_ctrl_bijection.1381187546	Mar 24 01:17:33 PM PDT 24	Mar 24 01:18:53 PM PDT 24	3617882233 ps
T227	/workspace/coverage/default/21.sram_ctrl_bijection.1857946171	Mar 24 01:17:59 PM PDT 24	Mar 24 01:18:49 PM PDT 24	3543156823 ps
T228	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2991175899	Mar 24 01:18:42 PM PDT 24	Mar 24 01:21:17 PM PDT 24	577483936 ps
T229	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.801822367	Mar 24 01:18:07 PM PDT 24	Mar 24 01:18:17 PM PDT 24	94148514 ps
T230	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1272537702	Mar 24 01:20:01 PM PDT 24	Mar 24 01:23:53 PM PDT 24	2495223042 ps
T231	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2961103270	Mar 24 01:18:32 PM PDT 24	Mar 24 01:20:28 PM PDT 24	2407648213 ps
T136	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2047388621	Mar 24 01:18:50 PM PDT 24	Mar 24 01:18:53 PM PDT 24	366188070 ps
T232	/workspace/coverage/default/22.sram_ctrl_executable.88262895	Mar 24 01:18:07 PM PDT 24	Mar 24 01:23:53 PM PDT 24	1452960497 ps
T233	/workspace/coverage/default/44.sram_ctrl_smoke.978857441	Mar 24 01:19:33 PM PDT 24	Mar 24 01:19:43 PM PDT 24	171298163 ps
T234	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1684188668	Mar 24 01:19:51 PM PDT 24	Mar 24 01:19:54 PM PDT 24	179206833 ps
T235	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4068243663	Mar 24 01:17:32 PM PDT 24	Mar 24 01:17:38 PM PDT 24	120529705 ps
T236	/workspace/coverage/default/7.sram_ctrl_max_throughput.1564188907	Mar 24 01:17:21 PM PDT 24	Mar 24 01:17:23 PM PDT 24	43563494 ps
T237	/workspace/coverage/default/40.sram_ctrl_partial_access.2082858461	Mar 24 01:19:14 PM PDT 24	Mar 24 01:21:28 PM PDT 24	416457855 ps
T238	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3220619620	Mar 24 01:17:44 PM PDT 24	Mar 24 01:17:49 PM PDT 24	2937001660 ps
T24	/workspace/coverage/default/0.sram_ctrl_sec_cm.2469430619	Mar 24 01:16:42 PM PDT 24	Mar 24 01:16:45 PM PDT 24	389864981 ps
T239	/workspace/coverage/default/38.sram_ctrl_bijection.539471512	Mar 24 01:19:02 PM PDT 24	Mar 24 01:19:51 PM PDT 24	11807554091 ps
T240	/workspace/coverage/default/27.sram_ctrl_stress_all.261669967	Mar 24 01:18:21 PM PDT 24	Mar 24 01:56:08 PM PDT 24	75862618868 ps
T241	/workspace/coverage/default/19.sram_ctrl_alert_test.2409195242	Mar 24 01:17:53 PM PDT 24	Mar 24 01:17:54 PM PDT 24	10516643 ps
T242	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1981544329	Mar 24 01:17:39 PM PDT 24	Mar 24 01:17:44 PM PDT 24	160693929 ps
T243	/workspace/coverage/default/20.sram_ctrl_multiple_keys.4118442487	Mar 24 01:18:01 PM PDT 24	Mar 24 01:24:15 PM PDT 24	5712873723 ps
T244	/workspace/coverage/default/38.sram_ctrl_mem_walk.3041501844	Mar 24 01:19:08 PM PDT 24	Mar 24 01:19:16 PM PDT 24	138486182 ps
T245	/workspace/coverage/default/47.sram_ctrl_bijection.1370492822	Mar 24 01:19:46 PM PDT 24	Mar 24 01:20:22 PM PDT 24	6157371924 ps
T143	/workspace/coverage/default/22.sram_ctrl_multiple_keys.419454700	Mar 24 01:18:05 PM PDT 24	Mar 24 01:55:50 PM PDT 24	25423470454 ps
T246	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1849287618	Mar 24 01:18:14 PM PDT 24	Mar 24 01:44:51 PM PDT 24	5585225267 ps
T247	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.4003684911	Mar 24 01:18:07 PM PDT 24	Mar 24 01:18:12 PM PDT 24	303050329 ps
T248	/workspace/coverage/default/24.sram_ctrl_regwen.28953903	Mar 24 01:18:17 PM PDT 24	Mar 24 01:38:53 PM PDT 24	52176217861 ps
T249	/workspace/coverage/default/1.sram_ctrl_alert_test.3852062882	Mar 24 01:16:46 PM PDT 24	Mar 24 01:16:47 PM PDT 24	12751231 ps
T46	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2616314821	Mar 24 01:19:29 PM PDT 24	Mar 24 01:33:34 PM PDT 24	4197003585 ps
T250	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3205169626	Mar 24 01:19:46 PM PDT 24	Mar 24 01:19:49 PM PDT 24	46737049 ps
T251	/workspace/coverage/default/48.sram_ctrl_max_throughput.2766207482	Mar 24 01:19:54 PM PDT 24	Mar 24 01:19:56 PM PDT 24	41156756 ps
T252	/workspace/coverage/default/21.sram_ctrl_max_throughput.1048192060	Mar 24 01:18:08 PM PDT 24	Mar 24 01:19:41 PM PDT 24	525365647 ps
T253	/workspace/coverage/default/8.sram_ctrl_bijection.821631611	Mar 24 01:17:20 PM PDT 24	Mar 24 01:18:21 PM PDT 24	2501997766 ps
T254	/workspace/coverage/default/23.sram_ctrl_lc_escalation.1535728215	Mar 24 01:18:06 PM PDT 24	Mar 24 01:18:14 PM PDT 24	854841741 ps
T255	/workspace/coverage/default/15.sram_ctrl_mem_walk.2903481055	Mar 24 01:17:34 PM PDT 24	Mar 24 01:17:44 PM PDT 24	596563104 ps
T256	/workspace/coverage/default/31.sram_ctrl_partial_access.3868254134	Mar 24 01:18:33 PM PDT 24	Mar 24 01:18:41 PM PDT 24	217952204 ps
T257	/workspace/coverage/default/20.sram_ctrl_bijection.3579399457	Mar 24 01:17:55 PM PDT 24	Mar 24 01:18:55 PM PDT 24	2887628890 ps
T258	/workspace/coverage/default/17.sram_ctrl_ram_cfg.2969213235	Mar 24 01:17:35 PM PDT 24	Mar 24 01:17:36 PM PDT 24	88054744 ps
T259	/workspace/coverage/default/25.sram_ctrl_regwen.2998362829	Mar 24 01:18:14 PM PDT 24	Mar 24 01:33:59 PM PDT 24	58800614183 ps
T260	/workspace/coverage/default/33.sram_ctrl_smoke.3434307575	Mar 24 01:18:40 PM PDT 24	Mar 24 01:18:50 PM PDT 24	465244014 ps
T261	/workspace/coverage/default/40.sram_ctrl_max_throughput.837724554	Mar 24 01:19:15 PM PDT 24	Mar 24 01:20:27 PM PDT 24	121263328 ps
T262	/workspace/coverage/default/13.sram_ctrl_ram_cfg.358276379	Mar 24 01:17:35 PM PDT 24	Mar 24 01:17:36 PM PDT 24	45617125 ps
T263	/workspace/coverage/default/23.sram_ctrl_executable.1091888644	Mar 24 01:18:08 PM PDT 24	Mar 24 01:22:58 PM PDT 24	1640683888 ps
T264	/workspace/coverage/default/44.sram_ctrl_regwen.1775670871	Mar 24 01:19:44 PM PDT 24	Mar 24 01:34:02 PM PDT 24	4404834716 ps
T265	/workspace/coverage/default/19.sram_ctrl_max_throughput.3043525566	Mar 24 01:17:51 PM PDT 24	Mar 24 01:17:52 PM PDT 24	128392501 ps
T266	/workspace/coverage/default/26.sram_ctrl_max_throughput.1305312038	Mar 24 01:18:14 PM PDT 24	Mar 24 01:19:37 PM PDT 24	414202553 ps
T267	/workspace/coverage/default/36.sram_ctrl_lc_escalation.187989881	Mar 24 01:19:04 PM PDT 24	Mar 24 01:19:06 PM PDT 24	614680114 ps
T268	/workspace/coverage/default/13.sram_ctrl_multiple_keys.3913749687	Mar 24 01:17:33 PM PDT 24	Mar 24 01:33:28 PM PDT 24	8264547152 ps
T269	/workspace/coverage/default/25.sram_ctrl_lc_escalation.3049986826	Mar 24 01:18:09 PM PDT 24	Mar 24 01:18:16 PM PDT 24	685952267 ps
T270	/workspace/coverage/default/23.sram_ctrl_alert_test.1892848822	Mar 24 01:18:08 PM PDT 24	Mar 24 01:18:09 PM PDT 24	21198741 ps
T271	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4010008196	Mar 24 01:19:23 PM PDT 24	Mar 24 01:19:25 PM PDT 24	79387109 ps
T272	/workspace/coverage/default/34.sram_ctrl_executable.1817663886	Mar 24 01:18:46 PM PDT 24	Mar 24 01:33:10 PM PDT 24	27496801098 ps
T273	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2869010945	Mar 24 01:17:33 PM PDT 24	Mar 24 01:17:36 PM PDT 24	48402372 ps
T274	/workspace/coverage/default/32.sram_ctrl_multiple_keys.2398995394	Mar 24 01:18:36 PM PDT 24	Mar 24 01:34:07 PM PDT 24	5766513507 ps
T275	/workspace/coverage/default/49.sram_ctrl_smoke.1532516589	Mar 24 01:19:56 PM PDT 24	Mar 24 01:20:14 PM PDT 24	963104228 ps
T276	/workspace/coverage/default/44.sram_ctrl_lc_escalation.1326443460	Mar 24 01:19:36 PM PDT 24	Mar 24 01:19:39 PM PDT 24	429788958 ps
T277	/workspace/coverage/default/23.sram_ctrl_smoke.2802898079	Mar 24 01:18:05 PM PDT 24	Mar 24 01:18:13 PM PDT 24	270845511 ps
T278	/workspace/coverage/default/32.sram_ctrl_mem_walk.1319401358	Mar 24 01:18:40 PM PDT 24	Mar 24 01:18:45 PM PDT 24	494988640 ps
T279	/workspace/coverage/default/22.sram_ctrl_stress_all.1249457705	Mar 24 01:18:06 PM PDT 24	Mar 24 02:36:09 PM PDT 24	69236394790 ps
T280	/workspace/coverage/default/48.sram_ctrl_alert_test.3010015291	Mar 24 01:19:54 PM PDT 24	Mar 24 01:19:55 PM PDT 24	84216557 ps
T281	/workspace/coverage/default/39.sram_ctrl_regwen.2006764866	Mar 24 01:19:17 PM PDT 24	Mar 24 01:40:24 PM PDT 24	47130000084 ps
T282	/workspace/coverage/default/25.sram_ctrl_alert_test.919005768	Mar 24 01:18:16 PM PDT 24	Mar 24 01:18:17 PM PDT 24	18804879 ps
T25	/workspace/coverage/default/1.sram_ctrl_sec_cm.3559034144	Mar 24 01:16:45 PM PDT 24	Mar 24 01:16:47 PM PDT 24	190652446 ps
T283	/workspace/coverage/default/4.sram_ctrl_multiple_keys.1224532103	Mar 24 01:16:59 PM PDT 24	Mar 24 01:34:07 PM PDT 24	34039999792 ps
T284	/workspace/coverage/default/4.sram_ctrl_partial_access.3232909103	Mar 24 01:16:55 PM PDT 24	Mar 24 01:17:08 PM PDT 24	1091418195 ps
T285	/workspace/coverage/default/26.sram_ctrl_bijection.569879212	Mar 24 01:18:17 PM PDT 24	Mar 24 01:19:11 PM PDT 24	1741544626 ps
T286	/workspace/coverage/default/35.sram_ctrl_partial_access.1823133722	Mar 24 01:18:58 PM PDT 24	Mar 24 01:19:07 PM PDT 24	477462602 ps
T47	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2471685802	Mar 24 01:18:11 PM PDT 24	Mar 24 01:18:32 PM PDT 24	340414385 ps
T287	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3535000618	Mar 24 01:18:04 PM PDT 24	Mar 24 01:21:04 PM PDT 24	7283625629 ps
T288	/workspace/coverage/default/11.sram_ctrl_smoke.3182043820	Mar 24 01:17:30 PM PDT 24	Mar 24 01:17:35 PM PDT 24	305957086 ps
T289	/workspace/coverage/default/18.sram_ctrl_regwen.1017074307	Mar 24 01:17:44 PM PDT 24	Mar 24 01:22:43 PM PDT 24	3483375348 ps
T290	/workspace/coverage/default/19.sram_ctrl_bijection.2812996928	Mar 24 01:17:51 PM PDT 24	Mar 24 01:18:43 PM PDT 24	854238920 ps
T291	/workspace/coverage/default/2.sram_ctrl_smoke.1505991747	Mar 24 01:16:46 PM PDT 24	Mar 24 01:16:49 PM PDT 24	69030585 ps
T48	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3551727318	Mar 24 01:18:47 PM PDT 24	Mar 24 01:19:19 PM PDT 24	2351070360 ps
T292	/workspace/coverage/default/31.sram_ctrl_regwen.708377476	Mar 24 01:18:32 PM PDT 24	Mar 24 01:33:45 PM PDT 24	84029603883 ps
T293	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2280457730	Mar 24 01:17:16 PM PDT 24	Mar 24 01:20:32 PM PDT 24	1019721580 ps
T49	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1382732242	Mar 24 01:18:50 PM PDT 24	Mar 24 01:24:04 PM PDT 24	1270218805 ps
T294	/workspace/coverage/default/26.sram_ctrl_smoke.2446556988	Mar 24 01:18:17 PM PDT 24	Mar 24 01:18:31 PM PDT 24	4124339015 ps
T144	/workspace/coverage/default/40.sram_ctrl_executable.708341481	Mar 24 01:19:12 PM PDT 24	Mar 24 01:27:48 PM PDT 24	10691109904 ps
T295	/workspace/coverage/default/32.sram_ctrl_lc_escalation.1012397652	Mar 24 01:18:38 PM PDT 24	Mar 24 01:18:44 PM PDT 24	526386574 ps
T296	/workspace/coverage/default/11.sram_ctrl_partial_access.3164627696	Mar 24 01:17:27 PM PDT 24	Mar 24 01:17:35 PM PDT 24	820397979 ps
T297	/workspace/coverage/default/27.sram_ctrl_partial_access.733636460	Mar 24 01:18:13 PM PDT 24	Mar 24 01:18:26 PM PDT 24	884330921 ps
T298	/workspace/coverage/default/37.sram_ctrl_max_throughput.2368463746	Mar 24 01:19:00 PM PDT 24	Mar 24 01:21:32 PM PDT 24	546405249 ps
T299	/workspace/coverage/default/4.sram_ctrl_ram_cfg.1529800218	Mar 24 01:17:16 PM PDT 24	Mar 24 01:17:17 PM PDT 24	34086192 ps
T300	/workspace/coverage/default/35.sram_ctrl_alert_test.1584175014	Mar 24 01:18:58 PM PDT 24	Mar 24 01:18:59 PM PDT 24	35505055 ps
T111	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.361619609	Mar 24 01:17:49 PM PDT 24	Mar 24 01:18:22 PM PDT 24	2228758412 ps
T301	/workspace/coverage/default/39.sram_ctrl_stress_all.3171542916	Mar 24 01:19:15 PM PDT 24	Mar 24 01:40:43 PM PDT 24	17777613073 ps
T302	/workspace/coverage/default/39.sram_ctrl_bijection.2057474672	Mar 24 01:19:10 PM PDT 24	Mar 24 01:20:25 PM PDT 24	9630931356 ps
T303	/workspace/coverage/default/1.sram_ctrl_multiple_keys.2980886821	Mar 24 01:16:42 PM PDT 24	Mar 24 01:22:30 PM PDT 24	3494169638 ps
T304	/workspace/coverage/default/39.sram_ctrl_mem_walk.2595876286	Mar 24 01:19:14 PM PDT 24	Mar 24 01:19:19 PM PDT 24	238006187 ps
T137	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2581820434	Mar 24 01:17:28 PM PDT 24	Mar 24 01:17:34 PM PDT 24	643880030 ps
T305	/workspace/coverage/default/22.sram_ctrl_bijection.741403439	Mar 24 01:18:05 PM PDT 24	Mar 24 01:18:30 PM PDT 24	476101481 ps
T306	/workspace/coverage/default/48.sram_ctrl_smoke.1222657716	Mar 24 01:19:55 PM PDT 24	Mar 24 01:21:05 PM PDT 24	545269522 ps
T307	/workspace/coverage/default/28.sram_ctrl_max_throughput.2169934557	Mar 24 01:18:18 PM PDT 24	Mar 24 01:18:27 PM PDT 24	231350319 ps
T308	/workspace/coverage/default/35.sram_ctrl_mem_walk.187104823	Mar 24 01:18:50 PM PDT 24	Mar 24 01:18:58 PM PDT 24	267656184 ps