Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43940514	1			T1	126310		T2	18432		T3	787
triple_byte_access	2534064	1			T1	2502		T3	744		T4	3362
halfword_access	3804858	1			T1	3747		T3	1040		T4	5076
byte_access	5076811	1			T1	5081		T3	1442		T4	6816
zero_access	1279102	1			T1	1282		T3	337		T4	1606

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28265343

1

T1

69435

T2

9216

T3

2125

auto[1]

28370006

1

T1

69487

T2

9216

T3

2225

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21923640	1			T1	63114		T2	9216		T3	387
auto[0]	triple_byte_access	1264524	1			T1	1295		T3	376		T4	1674
auto[0]	halfword_access	1898183	1			T1	1894		T3	514		T4	2511
auto[0]	byte_access	2535060	1			T1	2473		T3	688		T4	3367
auto[0]	zero_access	643936	1			T1	659		T3	160		T4	803
auto[1]	word_access	22016874	1			T1	63196		T2	9216		T3	400
auto[1]	triple_byte_access	1269540	1			T1	1207		T3	368		T4	1688
auto[1]	halfword_access	1906675	1			T1	1853		T3	526		T4	2565
auto[1]	byte_access	2541751	1			T1	2608		T3	754		T4	3449
auto[1]	zero_access	635166	1			T1	623		T3	177		T4	803