Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14107721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58996276

1

T1

3071

T2

164320

T3

3071

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36429733	1			T1	1024		T2	90113		T3	1024
values[0x0]	16924873	1			T1	1044		T2	43816		T3	1020
values[0x1]	19749391	1			T1	1003		T2	46504		T3	1027

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7026681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66077316

1

T1

3071

T2

172390

T3

3071

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306681	1			T1	10		T2	694		T8	30
valid_sources[0x01]	352428	1			T1	17		T2	683		T8	47
valid_sources[0x02]	368169	1			T1	6		T2	734		T8	38
valid_sources[0x03]	281119	1			T1	27		T2	730		T8	35
valid_sources[0x04]	267348	1			T1	12		T2	682		T8	33
valid_sources[0x05]	259452	1			T1	29		T2	667		T8	38
valid_sources[0x06]	298677	1			T1	5		T2	684		T8	38
valid_sources[0x07]	325595	1			T1	17		T2	650		T8	35
valid_sources[0x08]	306774	1			T1	4		T2	710		T8	26
valid_sources[0x09]	351525	1			T1	9		T2	757		T8	38
valid_sources[0x0a]	320452	1			T1	12		T2	759		T8	52
valid_sources[0x0b]	344737	1			T1	11		T2	747		T8	39
valid_sources[0x0c]	315507	1			T1	26		T2	684		T8	23
valid_sources[0x0d]	350876	1			T1	29		T2	711		T8	53
valid_sources[0x0e]	251732	1			T1	12		T2	754		T8	39
valid_sources[0x0f]	382425	1			T1	13		T2	582		T8	34
valid_sources[0x10]	263733	1			T1	9		T2	712		T8	41
valid_sources[0x11]	311714	1			T1	12		T2	697		T8	22
valid_sources[0x12]	228697	1			T1	15		T2	707		T8	43
valid_sources[0x13]	229710	1			T1	6		T2	656		T8	27
valid_sources[0x14]	352075	1			T1	26		T2	715		T8	32
valid_sources[0x15]	282527	1			T1	11		T2	660		T8	37
valid_sources[0x16]	331378	1			T1	15		T2	685		T8	34
valid_sources[0x17]	261985	1			T1	2		T2	674		T8	30
valid_sources[0x18]	324553	1			T1	4		T2	851		T8	43
valid_sources[0x19]	300141	1			T1	14		T2	753		T8	47
valid_sources[0x1a]	275801	1			T1	24		T2	771		T8	33
valid_sources[0x1b]	286666	1			T1	19		T2	753		T8	31
valid_sources[0x1c]	250881	1			T1	8		T2	673		T8	28
valid_sources[0x1d]	276826	1			T1	18		T2	566		T8	25
valid_sources[0x1e]	257754	1			T1	14		T2	714		T8	38
valid_sources[0x1f]	257314	1			T1	21		T2	743		T8	31
valid_sources[0x20]	286055	1			T1	19		T2	665		T8	36
valid_sources[0x21]	246498	1			T1	9		T2	656		T8	36
valid_sources[0x22]	281549	1			T1	18		T2	705		T8	39
valid_sources[0x23]	332361	1			T1	4		T2	794		T8	31
valid_sources[0x24]	293406	1			T1	12		T2	713		T8	33
valid_sources[0x25]	322622	1			T1	12		T2	697		T8	26
valid_sources[0x26]	236793	1			T1	3		T2	743		T8	43
valid_sources[0x27]	258081	1			T1	14		T2	644		T8	39
valid_sources[0x28]	347779	1			T1	7		T2	787		T8	41
valid_sources[0x29]	286865	1			T1	14		T2	628		T8	40
valid_sources[0x2a]	271564	1			T1	9		T2	639		T8	42
valid_sources[0x2b]	262440	1			T1	10		T2	731		T8	29
valid_sources[0x2c]	241362	1			T1	6		T2	731		T8	45
valid_sources[0x2d]	329973	1			T1	6		T2	635		T8	50
valid_sources[0x2e]	298220	1			T1	13		T2	813		T8	34
valid_sources[0x2f]	259616	1			T1	5		T2	753		T8	34
valid_sources[0x30]	256044	1			T1	3		T2	732		T8	33
valid_sources[0x31]	365377	1			T1	9		T2	735		T8	47
valid_sources[0x32]	284414	1			T1	21		T2	774		T8	26
valid_sources[0x33]	336504	1			T1	11		T2	657		T8	49
valid_sources[0x34]	262699	1			T1	11		T2	666		T8	33
valid_sources[0x35]	340350	1			T1	8		T2	747		T8	31
valid_sources[0x36]	243437	1			T1	8		T2	783		T8	31
valid_sources[0x37]	269048	1			T1	8		T2	798		T8	36
valid_sources[0x38]	331924	1			T1	7		T2	741		T8	35
valid_sources[0x39]	260386	1			T1	21		T2	724		T8	31
valid_sources[0x3a]	302342	1			T1	12		T2	687		T8	25
valid_sources[0x3b]	248232	1			T1	25		T2	698		T8	37
valid_sources[0x3c]	231247	1			T1	11		T2	737		T8	30
valid_sources[0x3d]	324205	1			T1	9		T2	678		T8	40
valid_sources[0x3e]	320066	1			T1	11		T2	695		T8	31
valid_sources[0x3f]	305967	1			T1	5		T2	659		T8	21
valid_sources[0x40]	272942	1			T1	5		T2	718		T8	25
valid_sources[0x41]	326427	1			T2	637		T8	48		T5	184
valid_sources[0x42]	266929	1			T1	13		T2	683		T8	29
valid_sources[0x43]	273036	1			T1	34		T2	662		T8	25
valid_sources[0x44]	317252	1			T1	13		T2	676		T8	30
valid_sources[0x45]	303669	1			T1	6		T2	738		T8	43
valid_sources[0x46]	261421	1			T1	9		T2	707		T8	43
valid_sources[0x47]	301454	1			T1	8		T2	680		T8	29
valid_sources[0x48]	251175	1			T1	15		T2	726		T8	45
valid_sources[0x49]	394894	1			T1	8		T2	636		T8	37
valid_sources[0x4a]	264960	1			T1	7		T2	743		T8	22
valid_sources[0x4b]	266530	1			T1	6		T2	649		T8	39
valid_sources[0x4c]	288126	1			T1	16		T2	727		T8	27
valid_sources[0x4d]	272497	1			T1	13		T2	726		T8	28
valid_sources[0x4e]	300638	1			T1	19		T2	696		T8	44
valid_sources[0x4f]	288078	1			T1	12		T2	695		T8	31
valid_sources[0x50]	293879	1			T1	10		T2	764		T8	41
valid_sources[0x51]	271845	1			T1	5		T2	802		T8	38
valid_sources[0x52]	304177	1			T1	13		T2	599		T8	43
valid_sources[0x53]	323558	1			T2	749		T8	29		T5	152
valid_sources[0x54]	265846	1			T1	5		T2	754		T8	24
valid_sources[0x55]	333088	1			T1	11		T2	747		T8	32
valid_sources[0x56]	317304	1			T1	8		T2	610		T8	38
valid_sources[0x57]	277454	1			T1	10		T2	559		T8	36
valid_sources[0x58]	254048	1			T1	10		T2	691		T8	27
valid_sources[0x59]	282304	1			T1	8		T2	750		T8	28
valid_sources[0x5a]	236509	1			T1	16		T2	711		T8	29
valid_sources[0x5b]	322339	1			T1	1		T2	706		T8	17
valid_sources[0x5c]	258059	1			T1	13		T2	731		T8	32
valid_sources[0x5d]	320368	1			T1	6		T2	593		T8	33
valid_sources[0x5e]	309770	1			T1	7		T2	727		T8	43
valid_sources[0x5f]	257411	1			T1	10		T2	673		T8	21
valid_sources[0x60]	279906	1			T1	14		T2	665		T8	40
valid_sources[0x61]	322374	1			T1	4		T2	673		T8	27
valid_sources[0x62]	308747	1			T1	17		T2	691		T8	38
valid_sources[0x63]	280837	1			T1	19		T2	716		T8	31
valid_sources[0x64]	267719	1			T1	15		T2	756		T8	31
valid_sources[0x65]	234097	1			T1	5		T2	698		T8	29
valid_sources[0x66]	303611	1			T1	14		T2	669		T8	35
valid_sources[0x67]	235693	1			T1	16		T2	721		T8	19
valid_sources[0x68]	259001	1			T1	3		T2	801		T8	44
valid_sources[0x69]	285135	1			T1	5		T2	634		T8	35
valid_sources[0x6a]	243344	1			T1	13		T2	688		T8	25
valid_sources[0x6b]	295622	1			T1	14		T2	701		T8	27
valid_sources[0x6c]	315816	1			T1	9		T2	758		T8	29
valid_sources[0x6d]	293681	1			T1	9		T2	684		T8	31
valid_sources[0x6e]	311178	1			T1	28		T2	817		T8	44
valid_sources[0x6f]	242171	1			T1	16		T2	750		T8	29
valid_sources[0x70]	331079	1			T1	7		T2	754		T8	33
valid_sources[0x71]	241921	1			T1	10		T2	647		T8	40
valid_sources[0x72]	297764	1			T1	20		T2	582		T8	41
valid_sources[0x73]	298835	1			T1	11		T2	710		T8	37
valid_sources[0x74]	291794	1			T1	16		T2	711		T8	42
valid_sources[0x75]	282999	1			T1	12		T2	732		T8	33
valid_sources[0x76]	292504	1			T1	10		T2	739		T8	33
valid_sources[0x77]	310046	1			T1	15		T2	671		T8	41
valid_sources[0x78]	280618	1			T1	14		T2	602		T8	34
valid_sources[0x79]	251504	1			T1	11		T2	729		T8	31
valid_sources[0x7a]	243949	1			T1	2		T2	766		T8	41
valid_sources[0x7b]	254115	1			T1	9		T2	831		T8	34
valid_sources[0x7c]	256253	1			T1	10		T2	688		T8	40
valid_sources[0x7d]	245333	1			T1	8		T2	681		T8	44
valid_sources[0x7e]	276881	1			T1	36		T2	694		T8	39
valid_sources[0x7f]	301242	1			T1	21		T2	664		T8	32
valid_sources[0x80]	286050	1			T1	12		T2	646		T8	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29378785

1

T1

1024

T2

82056

T3

1024

values[0x0]

all_enables

biggest_size

14807754

1

T1

1044

T2

41357

T3

1020

values[0x1]

all_enables

biggest_size

14809737

1

T1

1003

T2

40907

T3

1027

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150748

1

T2

1

T8

1

T4

1864

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53430	1			T4	548		T5	763		T7	16
values[0x0]	63832	1			T2	4		T4	668		T5	1068
values[0x1]	68249	1			T2	3		T8	2		T4	735

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159425

1

T2

2

T8

1

T4

1899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	622	1			T4	12		T42	2		T24	1
valid_sources[0x01]	588	1			T4	1		T5	13		T17	1
valid_sources[0x02]	653	1			T4	2		T5	10		T7	4
valid_sources[0x03]	756	1			T4	7		T5	4		T17	1
valid_sources[0x04]	659	1			T4	10		T5	2		T17	1
valid_sources[0x05]	538	1			T4	11		T5	13		T10	2
valid_sources[0x06]	532	1			T4	4		T5	4		T19	1
valid_sources[0x07]	536	1			T8	2		T4	4		T5	2
valid_sources[0x08]	622	1			T4	10		T5	13		T17	2
valid_sources[0x09]	629	1			T4	6		T5	15		T33	20
valid_sources[0x0a]	830	1			T4	10		T5	13		T37	6
valid_sources[0x0b]	707	1			T4	16		T5	11		T19	1
valid_sources[0x0c]	626	1			T4	7		T5	6		T17	1
valid_sources[0x0d]	828	1			T4	20		T5	11		T7	5
valid_sources[0x0e]	683	1			T4	11		T5	6		T37	49
valid_sources[0x0f]	536	1			T4	8		T5	4		T17	2
valid_sources[0x10]	518	1			T4	10		T5	12		T35	4
valid_sources[0x11]	664	1			T4	16		T5	4		T9	42
valid_sources[0x12]	483	1			T4	5		T5	5		T17	1
valid_sources[0x13]	659	1			T4	11		T5	15		T17	1
valid_sources[0x14]	851	1			T4	5		T5	8		T17	1
valid_sources[0x15]	994	1			T4	3		T5	10		T37	15
valid_sources[0x16]	974	1			T4	14		T5	7		T37	1
valid_sources[0x17]	715	1			T4	9		T5	4		T17	4
valid_sources[0x18]	732	1			T4	6		T5	9		T10	1
valid_sources[0x19]	1038	1			T4	3		T5	23		T7	5
valid_sources[0x1a]	572	1			T4	5		T5	1		T37	82
valid_sources[0x1b]	635	1			T4	6		T5	11		T37	13
valid_sources[0x1c]	534	1			T5	11		T17	1		T37	1
valid_sources[0x1d]	718	1			T4	5		T5	16		T19	1
valid_sources[0x1e]	592	1			T4	2		T5	4		T31	2
valid_sources[0x1f]	801	1			T4	15		T5	6		T13	2
valid_sources[0x20]	607	1			T4	8		T5	17		T35	1
valid_sources[0x21]	837	1			T4	7		T5	23		T19	3
valid_sources[0x22]	869	1			T4	3		T5	17		T37	32
valid_sources[0x23]	758	1			T4	14		T5	8		T19	3
valid_sources[0x24]	621	1			T4	4		T18	2		T37	10
valid_sources[0x25]	630	1			T4	6		T5	10		T35	2
valid_sources[0x26]	514	1			T4	6		T5	21		T35	1
valid_sources[0x27]	1388	1			T4	5		T5	3		T37	13
valid_sources[0x28]	683	1			T4	9		T5	7		T17	1
valid_sources[0x29]	586	1			T4	4		T17	1		T31	1
valid_sources[0x2a]	709	1			T4	9		T5	2		T7	4
valid_sources[0x2b]	676	1			T4	11		T5	11		T37	47
valid_sources[0x2c]	514	1			T4	5		T5	28		T37	4
valid_sources[0x2d]	571	1			T4	10		T5	14		T35	1
valid_sources[0x2e]	719	1			T4	3		T5	10		T37	22
valid_sources[0x2f]	624	1			T4	4		T5	24		T33	17
valid_sources[0x30]	827	1			T4	8		T5	11		T33	33
valid_sources[0x31]	930	1			T4	7		T5	6		T37	3
valid_sources[0x32]	1022	1			T4	4		T5	30		T16	1
valid_sources[0x33]	710	1			T4	9		T5	25		T35	4
valid_sources[0x34]	729	1			T4	8		T5	8		T17	1
valid_sources[0x35]	578	1			T4	9		T5	16		T35	1
valid_sources[0x36]	1035	1			T4	15		T5	23		T37	27
valid_sources[0x37]	768	1			T4	3		T5	13		T19	2
valid_sources[0x38]	932	1			T4	7		T5	9		T17	2
valid_sources[0x39]	779	1			T4	4		T5	13		T37	25
valid_sources[0x3a]	766	1			T4	20		T5	3		T17	1
valid_sources[0x3b]	732	1			T4	4		T5	21		T35	1
valid_sources[0x3c]	729	1			T4	5		T5	31		T19	2
valid_sources[0x3d]	728	1			T4	6		T5	12		T21	1
valid_sources[0x3e]	1048	1			T4	8		T5	1		T7	4
valid_sources[0x3f]	994	1			T2	7		T4	11		T5	58
valid_sources[0x40]	588	1			T4	5		T5	14		T19	1
valid_sources[0x41]	742	1			T4	5		T5	11		T17	1
valid_sources[0x42]	619	1			T4	8		T5	7		T17	1
valid_sources[0x43]	524	1			T4	3		T5	14		T137	1
valid_sources[0x44]	852	1			T4	8		T5	9		T17	1
valid_sources[0x45]	761	1			T4	5		T5	14		T37	46
valid_sources[0x46]	679	1			T4	2		T5	4		T74	1
valid_sources[0x47]	623	1			T4	5		T5	18		T19	1
valid_sources[0x48]	649	1			T4	5		T5	22		T17	1
valid_sources[0x49]	715	1			T5	15		T17	2		T10	1
valid_sources[0x4a]	539	1			T4	5		T5	12		T19	1
valid_sources[0x4b]	638	1			T4	6		T5	4		T37	6
valid_sources[0x4c]	637	1			T4	10		T5	32		T17	1
valid_sources[0x4d]	730	1			T4	10		T13	1		T37	24
valid_sources[0x4e]	892	1			T4	2		T5	2		T17	1
valid_sources[0x4f]	715	1			T4	10		T5	4		T37	2
valid_sources[0x50]	949	1			T4	6		T5	16		T17	1
valid_sources[0x51]	556	1			T4	8		T21	1		T33	19
valid_sources[0x52]	617	1			T4	1		T5	2		T35	4
valid_sources[0x53]	566	1			T4	11		T5	30		T37	4
valid_sources[0x54]	623	1			T4	3		T5	14		T58	2
valid_sources[0x55]	938	1			T4	7		T5	9		T17	1
valid_sources[0x56]	688	1			T4	8		T5	21		T37	13
valid_sources[0x57]	1115	1			T4	6		T5	6		T17	1
valid_sources[0x58]	867	1			T4	4		T35	1		T33	24
valid_sources[0x59]	927	1			T4	5		T5	22		T35	2
valid_sources[0x5a]	606	1			T4	26		T5	7		T17	2
valid_sources[0x5b]	813	1			T4	18		T5	37		T37	11
valid_sources[0x5c]	725	1			T4	8		T5	5		T17	3
valid_sources[0x5d]	730	1			T5	2		T31	1		T37	5
valid_sources[0x5e]	860	1			T5	18		T32	1		T33	27
valid_sources[0x5f]	692	1			T4	13		T5	14		T17	1
valid_sources[0x60]	1192	1			T4	9		T5	3		T21	1
valid_sources[0x61]	649	1			T4	1		T5	13		T37	2
valid_sources[0x62]	570	1			T4	12		T5	8		T17	2
valid_sources[0x63]	1217	1			T5	6		T17	2		T21	1
valid_sources[0x64]	579	1			T4	2		T5	11		T19	1
valid_sources[0x65]	687	1			T4	6		T5	27		T31	1
valid_sources[0x66]	598	1			T4	4		T5	5		T19	1
valid_sources[0x67]	876	1			T4	4		T5	30		T16	1
valid_sources[0x68]	578	1			T4	12		T5	6		T32	1
valid_sources[0x69]	593	1			T4	9		T5	9		T17	1
valid_sources[0x6a]	754	1			T4	2		T5	4		T37	93
valid_sources[0x6b]	654	1			T4	10		T5	16		T17	1
valid_sources[0x6c]	854	1			T4	5		T5	14		T37	3
valid_sources[0x6d]	738	1			T5	21		T17	1		T19	1
valid_sources[0x6e]	801	1			T4	4		T5	26		T35	1
valid_sources[0x6f]	876	1			T4	10		T5	19		T17	3
valid_sources[0x70]	941	1			T4	11		T5	14		T35	1
valid_sources[0x71]	672	1			T4	11		T5	11		T7	4
valid_sources[0x72]	829	1			T4	9		T5	15		T13	1
valid_sources[0x73]	794	1			T4	12		T5	7		T21	1
valid_sources[0x74]	847	1			T4	9		T5	6		T17	1
valid_sources[0x75]	742	1			T4	18		T5	4		T37	1
valid_sources[0x76]	946	1			T4	1		T5	33		T37	14
valid_sources[0x77]	814	1			T4	1		T5	9		T37	1
valid_sources[0x78]	649	1			T4	5		T5	1		T16	1
valid_sources[0x79]	565	1			T4	18		T5	2		T35	2
valid_sources[0x7a]	677	1			T4	10		T17	1		T37	22
valid_sources[0x7b]	640	1			T4	9		T5	23		T17	3
valid_sources[0x7c]	706	1			T4	5		T5	14		T19	1
valid_sources[0x7d]	735	1			T4	4		T5	7		T7	1
valid_sources[0x7e]	767	1			T5	28		T17	1		T35	3
valid_sources[0x7f]	500	1			T4	2		T5	8		T139	2
valid_sources[0x80]	690	1			T4	9		T5	20		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40983

1

T4

513

T5

717

T7

11

values[0x0]

all_enables

biggest_size

55790

1

T2

1

T4

657

T5

1059

values[0x1]

all_enables

biggest_size

53975

1

T8

1

T4

694

T5

1089