Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13839890

1

T2

16113

T4

3558

T5

4169

full_word

54132268

1

T1

3071

T2

164320

T3

3071

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67971858	1			T1	3071		T2	180433		T3	3071
auto[TlIntgErrCmd]	104	1			T108	5		T109	2		T110	2
auto[TlIntgErrData]	88	1			T108	1		T109	5		T110	3
auto[TlIntgErrBoth]	108	1			T108	4		T109	3		T110	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31201486

1

T1

1024

T2

90113

T3

1024

auto[1]

36770672

1

T1

2047

T2

90320

T3

2047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6615599	1			T2	8057		T4	1041		T5	953
auto[TlIntgErrNone]	partial	auto[1]	7224017	1			T2	8056		T4	2517		T5	3216
auto[TlIntgErrNone]	full_word	auto[0]	24585756	1			T1	1024		T2	82056		T3	1024
auto[TlIntgErrNone]	full_word	auto[1]	29546486	1			T1	2047		T2	82264		T3	2047
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T108	1		T109	1		T110	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T108	4		T109	1		T110	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T133	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T127	1		T133	2		T129	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T108	1		T110	2		T128	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T109	5		T110	1		T128	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T126	1		T130	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T126	1		T130	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T108	2		T109	1		T110	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T108	1		T109	2		T110	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T108	1		T135	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T135	3		T131	1		-	-