Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 66.67 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success 0.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 6 0 0.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
false 0 1 1
true 0 1 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 91 1 T17 1 T19 1 T35 4
others[1] 110 1 T137 1 T32 2 T138 1
others[2] 89 1 T17 1 T35 1 T139 1
others[3] 158 1 T19 3 T35 1 T137 1
false 918 1 T17 10 T19 13 T35 5
true 969 1 T17 11 T19 5 T35 12


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 119 1 T4 1 T19 1 T35 1
others[1] 740 1 T5 1 T17 5 T19 5
others[2] 5666 1 T1 1 T2 1 T3 1
others[3] 207 1 T17 2 T35 2 T49 1
false 33 1 T140 1 T141 3 T142 2
true 35 1 T50 1 T143 1 T141 1

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