Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	824901	1			T13	15974		T14	3		T15	2596
auto[1]	10822879	1			T2	75832		T8	4364		T4	3878
auto[2]	707392	1			T9	1		T13	14619		T14	1
auto[3]	10714053	1			T2	75955		T8	4483		T4	3690

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14741642	1			T2	125970		T8	8847		T4	6150
auto[1]	2234163	1			T2	12249		T4	691		T5	45
auto[2]	2221662	1			T2	12383		T4	639		T5	51
auto[3]	3871758	1			T2	1185		T4	88		T5	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8889918

1

T8

8838

T4

7561

T5

672

auto[1]

14179307

1

T2

151787

T8

9

T4

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	331210	1			T13	13078		T14	1		T15	2158
auto[0]	auto[0]	auto[1]	33911	1			T13	1380		T14	2		T15	208
auto[0]	auto[0]	auto[2]	33908	1			T13	1360		T15	207		T144	1
auto[0]	auto[0]	auto[3]	9735	1			T13	132		T15	21		T144	1
auto[0]	auto[1]	auto[0]	3325798	1			T8	4359		T4	3146		T5	291
auto[0]	auto[1]	auto[1]	350689	1			T4	368		T5	26		T7	1
auto[0]	auto[1]	auto[2]	337251	1			T4	315		T5	28		T17	39
auto[0]	auto[1]	auto[3]	72430	1			T4	44		T17	21		T18	9
auto[0]	auto[2]	auto[0]	292294	1			T9	1		T13	12095		T14	1
auto[0]	auto[2]	auto[1]	30132	1			T13	1249		T15	138		T49	105
auto[0]	auto[2]	auto[2]	26504	1			T13	1139		T15	220		T46	1
auto[0]	auto[2]	auto[3]	7278	1			T13	126		T15	18		T144	1
auto[0]	auto[3]	auto[0]	3285280	1			T8	4479		T4	2998		T5	282
auto[0]	auto[3]	auto[1]	332317	1			T4	323		T5	19		T17	43
auto[0]	auto[3]	auto[2]	346445	1			T4	323		T5	23		T7	2
auto[0]	auto[3]	auto[3]	74736	1			T4	44		T5	3		T7	1
auto[1]	auto[0]	auto[0]	14073	1			T13	19		T15	2		T22	999
auto[1]	auto[0]	auto[1]	61937	1			T13	3		T22	4291		T144	3055
auto[1]	auto[0]	auto[2]	61683	1			T13	2		T22	4320		T144	3101
auto[1]	auto[0]	auto[3]	278444	1			T22	19287		T144	13651		T146	9208
auto[1]	auto[1]	auto[0]	3739914	1			T2	62940		T8	5		T4	5
auto[1]	auto[1]	auto[1]	701063	1			T2	6102		T16	10236		T9	1
auto[1]	auto[1]	auto[2]	673763	1			T2	6224		T16	10768		T19	1
auto[1]	auto[1]	auto[3]	1621971	1			T2	566		T16	993		T13	1
auto[1]	auto[2]	auto[0]	12782	1			T13	10		T15	2		T22	870
auto[1]	auto[2]	auto[1]	55672	1			T22	3997		T144	2811		T51	1
auto[1]	auto[2]	auto[2]	51641	1			T22	2746		T144	2518		T51	1
auto[1]	auto[2]	auto[3]	231089	1			T22	12894		T144	11658		T147	1
auto[1]	auto[3]	auto[0]	3740291	1			T2	63030		T8	4		T4	1
auto[1]	auto[3]	auto[1]	668442	1			T2	6147		T16	10946		T21	4
auto[1]	auto[3]	auto[2]	690467	1			T2	6159		T4	1		T16	9859
auto[1]	auto[3]	auto[3]	1576075	1			T2	619		T16	966		T21	1