Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	304135093	151188	0	0
ctrl_regwen_rd_A	304135093	5315	0	0
exec_rd_A	304135093	5102	0	0
exec_regwen_rd_A	304135093	5432	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304135093	151188	0	0
T4	36835	1462	0	0
T5	95759	3252	0	0
T6	65188	0	0	0
T7	33590	0	0	0
T11	2823	0	0	0
T12	13388	0	0	0
T16	375969	0	0	0
T17	149048	0	0	0
T18	4653	0	0	0
T20	2295	0	0	0
T33	0	6199	0	0
T37	0	2591	0	0
T52	0	1652	0	0
T53	0	1043	0	0
T54	0	1582	0	0
T55	0	11311	0	0
T56	0	3270	0	0
T57	0	1471	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304135093	5315	0	0
T36	248472	0	0	0
T50	363292	0	0	0
T51	141811	0	0	0
T52	71776	402	0	0
T54	0	354	0	0
T111	0	381	0	0
T112	0	712	0	0
T113	0	524	0	0
T114	0	220	0	0
T115	0	367	0	0
T116	0	177	0	0
T117	0	217	0	0
T118	0	212	0	0
T119	449881	0	0	0
T120	1864	0	0	0
T121	3880	0	0	0
T122	7754	0	0	0
T123	6312	0	0	0
T124	6419	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304135093	5102	0	0
T36	248472	0	0	0
T50	363292	0	0	0
T51	141811	0	0	0
T52	71776	281	0	0
T54	0	359	0	0
T111	0	280	0	0
T112	0	688	0	0
T113	0	603	0	0
T114	0	228	0	0
T115	0	343	0	0
T116	0	143	0	0
T117	0	166	0	0
T118	0	174	0	0
T119	449881	0	0	0
T120	1864	0	0	0
T121	3880	0	0	0
T122	7754	0	0	0
T123	6312	0	0	0
T124	6419	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304135093	5432	0	0
T36	248472	0	0	0
T50	363292	0	0	0
T51	141811	0	0	0
T52	71776	380	0	0
T54	0	425	0	0
T111	0	280	0	0
T112	0	746	0	0
T113	0	652	0	0
T114	0	190	0	0
T115	0	298	0	0
T116	0	200	0	0
T117	0	240	0	0
T118	0	246	0	0
T119	449881	0	0	0
T120	1864	0	0	0
T121	3880	0	0	0
T122	7754	0	0	0
T123	6312	0	0	0
T124	6419	0	0	0