| T794 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1699780598 |
|
|
Mar 26 02:57:30 PM PDT 24 |
Mar 26 03:19:29 PM PDT 24 |
88841501440 ps |
| T795 |
/workspace/coverage/default/32.sram_ctrl_executable.2443209652 |
|
|
Mar 26 02:58:27 PM PDT 24 |
Mar 26 03:16:30 PM PDT 24 |
68906033003 ps |
| T796 |
/workspace/coverage/default/45.sram_ctrl_partial_access.659296918 |
|
|
Mar 26 02:59:17 PM PDT 24 |
Mar 26 02:59:34 PM PDT 24 |
297285195 ps |
| T797 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.303668595 |
|
|
Mar 26 02:57:31 PM PDT 24 |
Mar 26 02:57:32 PM PDT 24 |
32371386 ps |
| T798 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3592758765 |
|
|
Mar 26 02:57:41 PM PDT 24 |
Mar 26 03:00:34 PM PDT 24 |
1894795876 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_smoke.669957345 |
|
|
Mar 26 02:58:28 PM PDT 24 |
Mar 26 02:59:02 PM PDT 24 |
448739994 ps |
| T800 |
/workspace/coverage/default/0.sram_ctrl_alert_test.417066290 |
|
|
Mar 26 02:57:22 PM PDT 24 |
Mar 26 02:57:24 PM PDT 24 |
28719486 ps |
| T801 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3727101933 |
|
|
Mar 26 02:59:34 PM PDT 24 |
Mar 26 03:03:28 PM PDT 24 |
10410393831 ps |
| T802 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.540426657 |
|
|
Mar 26 02:57:51 PM PDT 24 |
Mar 26 03:06:29 PM PDT 24 |
1991791668 ps |
| T803 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4241550147 |
|
|
Mar 26 02:58:20 PM PDT 24 |
Mar 26 02:58:22 PM PDT 24 |
162415740 ps |
| T804 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3419161246 |
|
|
Mar 26 02:57:28 PM PDT 24 |
Mar 26 02:57:30 PM PDT 24 |
185905412 ps |
| T805 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.354084881 |
|
|
Mar 26 02:57:13 PM PDT 24 |
Mar 26 02:57:15 PM PDT 24 |
52301200 ps |
| T806 |
/workspace/coverage/default/41.sram_ctrl_bijection.2647460167 |
|
|
Mar 26 02:59:08 PM PDT 24 |
Mar 26 02:59:44 PM PDT 24 |
9699331594 ps |
| T807 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.420021400 |
|
|
Mar 26 02:58:55 PM PDT 24 |
Mar 26 02:58:56 PM PDT 24 |
83474451 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.443039769 |
|
|
Mar 26 02:58:54 PM PDT 24 |
Mar 26 02:58:56 PM PDT 24 |
156908590 ps |
| T809 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2335515970 |
|
|
Mar 26 02:58:16 PM PDT 24 |
Mar 26 03:03:17 PM PDT 24 |
52801026875 ps |
| T810 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1083971669 |
|
|
Mar 26 02:57:48 PM PDT 24 |
Mar 26 03:04:47 PM PDT 24 |
8374172618 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.43075143 |
|
|
Mar 26 02:57:35 PM PDT 24 |
Mar 26 02:57:38 PM PDT 24 |
234427564 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3220524030 |
|
|
Mar 26 02:57:41 PM PDT 24 |
Mar 26 03:19:49 PM PDT 24 |
4066457672 ps |
| T813 |
/workspace/coverage/default/24.sram_ctrl_regwen.1051061290 |
|
|
Mar 26 02:58:21 PM PDT 24 |
Mar 26 03:13:10 PM PDT 24 |
73060884671 ps |
| T814 |
/workspace/coverage/default/7.sram_ctrl_bijection.3675530012 |
|
|
Mar 26 02:57:36 PM PDT 24 |
Mar 26 02:57:58 PM PDT 24 |
1369025740 ps |
| T815 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1214541151 |
|
|
Mar 26 02:58:35 PM PDT 24 |
Mar 26 03:00:41 PM PDT 24 |
751745934 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3317134659 |
|
|
Mar 26 02:57:29 PM PDT 24 |
Mar 26 03:02:45 PM PDT 24 |
3664319259 ps |
| T817 |
/workspace/coverage/default/33.sram_ctrl_stress_all.841966970 |
|
|
Mar 26 02:58:35 PM PDT 24 |
Mar 26 03:00:02 PM PDT 24 |
25043084675 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4193495560 |
|
|
Mar 26 02:58:26 PM PDT 24 |
Mar 26 02:58:57 PM PDT 24 |
643838452 ps |
| T819 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2466197281 |
|
|
Mar 26 02:59:05 PM PDT 24 |
Mar 26 03:03:38 PM PDT 24 |
2949761918 ps |
| T820 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2027424892 |
|
|
Mar 26 02:57:44 PM PDT 24 |
Mar 26 03:13:36 PM PDT 24 |
18919971373 ps |
| T821 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3826244983 |
|
|
Mar 26 02:57:25 PM PDT 24 |
Mar 26 02:57:29 PM PDT 24 |
287934608 ps |
| T822 |
/workspace/coverage/default/18.sram_ctrl_regwen.2442501942 |
|
|
Mar 26 02:58:06 PM PDT 24 |
Mar 26 03:10:03 PM PDT 24 |
11530576163 ps |
| T823 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2671941478 |
|
|
Mar 26 02:57:29 PM PDT 24 |
Mar 26 02:57:37 PM PDT 24 |
343396212 ps |
| T824 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3866112526 |
|
|
Mar 26 02:58:01 PM PDT 24 |
Mar 26 03:38:09 PM PDT 24 |
113489682488 ps |
| T825 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.226068967 |
|
|
Mar 26 02:58:20 PM PDT 24 |
Mar 26 03:30:40 PM PDT 24 |
18566684754 ps |
| T826 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3476291978 |
|
|
Mar 26 02:58:23 PM PDT 24 |
Mar 26 03:01:55 PM PDT 24 |
2280019997 ps |
| T827 |
/workspace/coverage/default/17.sram_ctrl_smoke.3309511 |
|
|
Mar 26 02:58:06 PM PDT 24 |
Mar 26 02:58:19 PM PDT 24 |
800765626 ps |
| T828 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3522837694 |
|
|
Mar 26 02:58:28 PM PDT 24 |
Mar 26 02:58:36 PM PDT 24 |
547837199 ps |
| T829 |
/workspace/coverage/default/37.sram_ctrl_executable.248159967 |
|
|
Mar 26 02:58:52 PM PDT 24 |
Mar 26 03:12:15 PM PDT 24 |
7602518902 ps |
| T830 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2495615016 |
|
|
Mar 26 02:59:19 PM PDT 24 |
Mar 26 02:59:24 PM PDT 24 |
233657388 ps |
| T831 |
/workspace/coverage/default/36.sram_ctrl_smoke.1671366258 |
|
|
Mar 26 02:58:44 PM PDT 24 |
Mar 26 03:01:36 PM PDT 24 |
635525563 ps |
| T832 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1178193379 |
|
|
Mar 26 02:59:29 PM PDT 24 |
Mar 26 03:27:10 PM PDT 24 |
39780497632 ps |
| T833 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.4270768246 |
|
|
Mar 26 02:58:02 PM PDT 24 |
Mar 26 02:58:08 PM PDT 24 |
1368673958 ps |
| T834 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3851684148 |
|
|
Mar 26 02:58:25 PM PDT 24 |
Mar 26 03:02:47 PM PDT 24 |
43686220963 ps |
| T835 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2948499555 |
|
|
Mar 26 02:58:07 PM PDT 24 |
Mar 26 02:58:08 PM PDT 24 |
19999895 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1239383128 |
|
|
Mar 26 02:59:12 PM PDT 24 |
Mar 26 02:59:31 PM PDT 24 |
494562880 ps |
| T837 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1026005270 |
|
|
Mar 26 02:58:54 PM PDT 24 |
Mar 26 02:59:02 PM PDT 24 |
485546740 ps |
| T838 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1589637040 |
|
|
Mar 26 02:57:26 PM PDT 24 |
Mar 26 02:57:30 PM PDT 24 |
951177707 ps |
| T839 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2317133066 |
|
|
Mar 26 02:59:08 PM PDT 24 |
Mar 26 02:59:15 PM PDT 24 |
136132882 ps |
| T840 |
/workspace/coverage/default/28.sram_ctrl_regwen.3409828201 |
|
|
Mar 26 02:58:24 PM PDT 24 |
Mar 26 03:15:12 PM PDT 24 |
3908207460 ps |
| T841 |
/workspace/coverage/default/40.sram_ctrl_smoke.2481078546 |
|
|
Mar 26 02:59:03 PM PDT 24 |
Mar 26 02:59:11 PM PDT 24 |
668369346 ps |
| T842 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3657335698 |
|
|
Mar 26 02:58:53 PM PDT 24 |
Mar 26 03:07:10 PM PDT 24 |
11621053056 ps |
| T843 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3993988788 |
|
|
Mar 26 02:58:18 PM PDT 24 |
Mar 26 02:58:23 PM PDT 24 |
1483951086 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_executable.1731098128 |
|
|
Mar 26 02:58:27 PM PDT 24 |
Mar 26 03:06:14 PM PDT 24 |
3068440036 ps |
| T845 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3616291891 |
|
|
Mar 26 02:57:29 PM PDT 24 |
Mar 26 02:57:34 PM PDT 24 |
665524112 ps |
| T846 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.360751166 |
|
|
Mar 26 02:59:08 PM PDT 24 |
Mar 26 03:12:46 PM PDT 24 |
4251862919 ps |
| T847 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3548108332 |
|
|
Mar 26 02:58:28 PM PDT 24 |
Mar 26 02:58:33 PM PDT 24 |
674292133 ps |
| T848 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.487079033 |
|
|
Mar 26 02:58:38 PM PDT 24 |
Mar 26 02:58:39 PM PDT 24 |
44511999 ps |
| T849 |
/workspace/coverage/default/23.sram_ctrl_partial_access.631544872 |
|
|
Mar 26 02:58:07 PM PDT 24 |
Mar 26 02:58:24 PM PDT 24 |
911616608 ps |
| T850 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1533267314 |
|
|
Mar 26 02:58:23 PM PDT 24 |
Mar 26 02:58:39 PM PDT 24 |
506218613 ps |
| T851 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.827625225 |
|
|
Mar 26 02:59:19 PM PDT 24 |
Mar 26 03:11:15 PM PDT 24 |
8413485915 ps |
| T852 |
/workspace/coverage/default/22.sram_ctrl_bijection.3610866904 |
|
|
Mar 26 02:58:03 PM PDT 24 |
Mar 26 02:58:49 PM PDT 24 |
5608340663 ps |
| T853 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2454438469 |
|
|
Mar 26 02:58:29 PM PDT 24 |
Mar 26 03:11:07 PM PDT 24 |
9083930236 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1067999678 |
|
|
Mar 26 02:59:11 PM PDT 24 |
Mar 26 02:59:19 PM PDT 24 |
1737162592 ps |
| T855 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.251675002 |
|
|
Mar 26 02:57:30 PM PDT 24 |
Mar 26 02:57:32 PM PDT 24 |
119736312 ps |
| T856 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3805118935 |
|
|
Mar 26 02:58:01 PM PDT 24 |
Mar 26 02:58:24 PM PDT 24 |
430963994 ps |
| T857 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1219724470 |
|
|
Mar 26 02:58:01 PM PDT 24 |
Mar 26 02:58:03 PM PDT 24 |
375643319 ps |
| T858 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.4175015332 |
|
|
Mar 26 02:57:43 PM PDT 24 |
Mar 26 02:57:48 PM PDT 24 |
238764109 ps |
| T859 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3168284961 |
|
|
Mar 26 02:57:26 PM PDT 24 |
Mar 26 02:57:32 PM PDT 24 |
154382668 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_stress_all.581162515 |
|
|
Mar 26 02:59:03 PM PDT 24 |
Mar 26 04:06:20 PM PDT 24 |
34186121878 ps |
| T861 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3670936410 |
|
|
Mar 26 02:59:34 PM PDT 24 |
Mar 26 02:59:37 PM PDT 24 |
174844975 ps |
| T862 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4096697568 |
|
|
Mar 26 02:59:27 PM PDT 24 |
Mar 26 03:03:31 PM PDT 24 |
2540004760 ps |
| T863 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.905168966 |
|
|
Mar 26 02:58:27 PM PDT 24 |
Mar 26 03:16:50 PM PDT 24 |
4527749851 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2332228116 |
|
|
Mar 26 02:58:23 PM PDT 24 |
Mar 26 03:18:57 PM PDT 24 |
11679290418 ps |
| T865 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2455077610 |
|
|
Mar 26 02:59:10 PM PDT 24 |
Mar 26 02:59:10 PM PDT 24 |
24157717 ps |
| T866 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1171384569 |
|
|
Mar 26 02:58:37 PM PDT 24 |
Mar 26 03:10:14 PM PDT 24 |
1368368859 ps |
| T867 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.364279939 |
|
|
Mar 26 02:57:19 PM PDT 24 |
Mar 26 02:57:22 PM PDT 24 |
39482568 ps |
| T868 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2717896698 |
|
|
Mar 26 02:58:36 PM PDT 24 |
Mar 26 03:05:52 PM PDT 24 |
77118058791 ps |
| T869 |
/workspace/coverage/default/45.sram_ctrl_bijection.1991163255 |
|
|
Mar 26 02:59:18 PM PDT 24 |
Mar 26 03:00:19 PM PDT 24 |
1955642548 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4275364609 |
|
|
Mar 26 02:59:37 PM PDT 24 |
Mar 26 02:59:49 PM PDT 24 |
3130401515 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1639471100 |
|
|
Mar 26 02:57:22 PM PDT 24 |
Mar 26 03:01:11 PM PDT 24 |
2578043128 ps |
| T872 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.114098746 |
|
|
Mar 26 02:58:15 PM PDT 24 |
Mar 26 03:19:39 PM PDT 24 |
13334740051 ps |
| T873 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3945970137 |
|
|
Mar 26 02:58:27 PM PDT 24 |
Mar 26 02:58:28 PM PDT 24 |
13399971 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3303318445 |
|
|
Mar 26 02:58:09 PM PDT 24 |
Mar 26 03:03:32 PM PDT 24 |
56652990003 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1276025274 |
|
|
Mar 26 02:58:26 PM PDT 24 |
Mar 26 03:12:37 PM PDT 24 |
2448719833 ps |
| T876 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3432028226 |
|
|
Mar 26 02:58:22 PM PDT 24 |
Mar 26 02:58:29 PM PDT 24 |
269115943 ps |
| T877 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1276381067 |
|
|
Mar 26 02:58:12 PM PDT 24 |
Mar 26 02:58:37 PM PDT 24 |
645905035 ps |
| T878 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.788179927 |
|
|
Mar 26 02:57:31 PM PDT 24 |
Mar 26 02:58:24 PM PDT 24 |
131191166 ps |
| T879 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.693215351 |
|
|
Mar 26 02:59:20 PM PDT 24 |
Mar 26 03:05:16 PM PDT 24 |
146250160429 ps |
| T880 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.450895466 |
|
|
Mar 26 02:58:16 PM PDT 24 |
Mar 26 03:01:31 PM PDT 24 |
6651151874 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_regwen.3805574946 |
|
|
Mar 26 02:57:26 PM PDT 24 |
Mar 26 03:08:03 PM PDT 24 |
34190438997 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2616736550 |
|
|
Mar 26 02:57:58 PM PDT 24 |
Mar 26 03:00:06 PM PDT 24 |
514319609 ps |
| T883 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2704062212 |
|
|
Mar 26 02:58:17 PM PDT 24 |
Mar 26 04:16:51 PM PDT 24 |
77785567366 ps |
| T884 |
/workspace/coverage/default/32.sram_ctrl_regwen.3013257231 |
|
|
Mar 26 02:58:31 PM PDT 24 |
Mar 26 03:12:46 PM PDT 24 |
6682287093 ps |
| T885 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.746317300 |
|
|
Mar 26 02:57:51 PM PDT 24 |
Mar 26 02:57:53 PM PDT 24 |
213483849 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3237102165 |
|
|
Mar 26 02:58:26 PM PDT 24 |
Mar 26 02:58:31 PM PDT 24 |
656050568 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_executable.3954049364 |
|
|
Mar 26 02:57:33 PM PDT 24 |
Mar 26 03:14:11 PM PDT 24 |
4021532532 ps |
| T888 |
/workspace/coverage/default/29.sram_ctrl_smoke.474585882 |
|
|
Mar 26 02:58:19 PM PDT 24 |
Mar 26 03:00:18 PM PDT 24 |
562446874 ps |
| T889 |
/workspace/coverage/default/23.sram_ctrl_executable.2280957335 |
|
|
Mar 26 02:58:17 PM PDT 24 |
Mar 26 03:02:37 PM PDT 24 |
945258284 ps |
| T890 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2472860991 |
|
|
Mar 26 02:58:23 PM PDT 24 |
Mar 26 02:59:15 PM PDT 24 |
220624810 ps |
| T891 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1447294118 |
|
|
Mar 26 02:59:26 PM PDT 24 |
Mar 26 02:59:44 PM PDT 24 |
3898707776 ps |
| T892 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2428842831 |
|
|
Mar 26 02:58:54 PM PDT 24 |
Mar 26 03:02:40 PM PDT 24 |
30984668852 ps |
| T893 |
/workspace/coverage/default/48.sram_ctrl_bijection.4186081523 |
|
|
Mar 26 02:59:33 PM PDT 24 |
Mar 26 03:00:29 PM PDT 24 |
3693941126 ps |
| T894 |
/workspace/coverage/default/25.sram_ctrl_alert_test.953036277 |
|
|
Mar 26 02:58:20 PM PDT 24 |
Mar 26 02:58:21 PM PDT 24 |
15199937 ps |
| T895 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.32330906 |
|
|
Mar 26 02:57:37 PM PDT 24 |
Mar 26 03:22:07 PM PDT 24 |
38733438606 ps |
| T896 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1360884584 |
|
|
Mar 26 02:57:40 PM PDT 24 |
Mar 26 03:02:10 PM PDT 24 |
51549374724 ps |
| T897 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3228457836 |
|
|
Mar 26 02:58:03 PM PDT 24 |
Mar 26 02:58:51 PM PDT 24 |
147657176 ps |
| T898 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.805517270 |
|
|
Mar 26 02:59:34 PM PDT 24 |
Mar 26 03:02:11 PM PDT 24 |
302511175 ps |
| T899 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3949369504 |
|
|
Mar 26 02:58:24 PM PDT 24 |
Mar 26 03:00:37 PM PDT 24 |
158678594 ps |
| T900 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2506256369 |
|
|
Mar 26 02:58:43 PM PDT 24 |
Mar 26 03:01:16 PM PDT 24 |
302209259 ps |
| T901 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3752686595 |
|
|
Mar 26 02:58:01 PM PDT 24 |
Mar 26 02:58:04 PM PDT 24 |
380233876 ps |
| T902 |
/workspace/coverage/default/13.sram_ctrl_regwen.952790694 |
|
|
Mar 26 02:57:27 PM PDT 24 |
Mar 26 03:14:51 PM PDT 24 |
20350960205 ps |
| T903 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3834034557 |
|
|
Mar 26 02:57:29 PM PDT 24 |
Mar 26 02:58:20 PM PDT 24 |
662497985 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2197104151 |
|
|
Mar 26 02:57:34 PM PDT 24 |
Mar 26 03:10:38 PM PDT 24 |
13853045138 ps |
| T905 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.27198914 |
|
|
Mar 26 02:59:41 PM PDT 24 |
Mar 26 03:02:11 PM PDT 24 |
1638044040 ps |
| T906 |
/workspace/coverage/default/0.sram_ctrl_regwen.3496924964 |
|
|
Mar 26 02:57:33 PM PDT 24 |
Mar 26 03:21:53 PM PDT 24 |
63520006555 ps |
| T907 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3902315262 |
|
|
Mar 26 02:58:31 PM PDT 24 |
Mar 26 02:58:32 PM PDT 24 |
30016190 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2389288511 |
|
|
Mar 26 02:58:29 PM PDT 24 |
Mar 26 02:58:53 PM PDT 24 |
2125144717 ps |
| T909 |
/workspace/coverage/default/33.sram_ctrl_partial_access.28447780 |
|
|
Mar 26 02:58:31 PM PDT 24 |
Mar 26 02:58:43 PM PDT 24 |
1245411368 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.59125210 |
|
|
Mar 26 02:57:43 PM PDT 24 |
Mar 26 03:05:46 PM PDT 24 |
11705564842 ps |
| T911 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1431836008 |
|
|
Mar 26 02:59:27 PM PDT 24 |
Mar 26 03:27:03 PM PDT 24 |
8753502737 ps |
| T912 |
/workspace/coverage/default/35.sram_ctrl_executable.3106695361 |
|
|
Mar 26 02:58:38 PM PDT 24 |
Mar 26 03:10:42 PM PDT 24 |
6671837021 ps |
| T913 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2319762424 |
|
|
Mar 26 02:59:02 PM PDT 24 |
Mar 26 02:59:03 PM PDT 24 |
92240532 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3531989029 |
|
|
Mar 26 02:59:46 PM PDT 24 |
Mar 26 02:59:51 PM PDT 24 |
1327447249 ps |
| T915 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3204166266 |
|
|
Mar 26 02:58:34 PM PDT 24 |
Mar 26 03:02:16 PM PDT 24 |
12018104795 ps |
| T916 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.703364294 |
|
|
Mar 26 02:57:31 PM PDT 24 |
Mar 26 03:00:11 PM PDT 24 |
8285966115 ps |
| T917 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4283188903 |
|
|
Mar 26 02:59:02 PM PDT 24 |
Mar 26 03:00:14 PM PDT 24 |
131169935 ps |
| T918 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2137451341 |
|
|
Mar 26 02:57:45 PM PDT 24 |
Mar 26 03:15:59 PM PDT 24 |
4205908566 ps |
| T919 |
/workspace/coverage/default/34.sram_ctrl_alert_test.34832144 |
|
|
Mar 26 02:58:36 PM PDT 24 |
Mar 26 02:58:37 PM PDT 24 |
18229565 ps |
| T920 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3379159149 |
|
|
Mar 26 02:58:45 PM PDT 24 |
Mar 26 03:03:54 PM PDT 24 |
3211878487 ps |
| T921 |
/workspace/coverage/default/48.sram_ctrl_stress_all.1045441398 |
|
|
Mar 26 02:59:42 PM PDT 24 |
Mar 26 03:52:25 PM PDT 24 |
37553934354 ps |
| T922 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.201339199 |
|
|
Mar 26 02:57:09 PM PDT 24 |
Mar 26 03:03:28 PM PDT 24 |
8703031393 ps |
| T923 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2073950300 |
|
|
Mar 26 02:57:39 PM PDT 24 |
Mar 26 02:57:41 PM PDT 24 |
85752394 ps |
| T924 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1932503097 |
|
|
Mar 26 02:58:43 PM PDT 24 |
Mar 26 02:59:36 PM PDT 24 |
782496776 ps |
| T925 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3759995042 |
|
|
Mar 26 02:59:27 PM PDT 24 |
Mar 26 02:59:33 PM PDT 24 |
179154179 ps |
| T926 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.242988339 |
|
|
Mar 26 02:57:30 PM PDT 24 |
Mar 26 02:58:35 PM PDT 24 |
122695568 ps |
| T927 |
/workspace/coverage/default/11.sram_ctrl_regwen.2832995822 |
|
|
Mar 26 02:57:24 PM PDT 24 |
Mar 26 03:01:36 PM PDT 24 |
674461702 ps |
| T928 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3240986164 |
|
|
Mar 26 02:59:42 PM PDT 24 |
Mar 26 02:59:53 PM PDT 24 |
1458703197 ps |
| T929 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2807209635 |
|
|
Mar 26 02:58:10 PM PDT 24 |
Mar 26 02:58:20 PM PDT 24 |
84931773 ps |
| T930 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.185476428 |
|
|
Mar 26 02:59:12 PM PDT 24 |
Mar 26 02:59:15 PM PDT 24 |
888670047 ps |
| T931 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1299411248 |
|
|
Mar 26 02:58:27 PM PDT 24 |
Mar 26 03:00:00 PM PDT 24 |
564987799 ps |
| T932 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3831482430 |
|
|
Mar 26 02:58:04 PM PDT 24 |
Mar 26 03:00:43 PM PDT 24 |
4611476719 ps |
| T933 |
/workspace/coverage/default/10.sram_ctrl_bijection.2388377870 |
|
|
Mar 26 02:57:57 PM PDT 24 |
Mar 26 02:58:12 PM PDT 24 |
242648386 ps |
| T934 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3570115250 |
|
|
Mar 26 02:57:28 PM PDT 24 |
Mar 26 02:57:29 PM PDT 24 |
31553808 ps |
| T935 |
/workspace/coverage/default/0.sram_ctrl_smoke.875344446 |
|
|
Mar 26 02:57:25 PM PDT 24 |
Mar 26 02:57:34 PM PDT 24 |
917013779 ps |
| T106 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.636509606 |
|
|
Mar 26 02:40:07 PM PDT 24 |
Mar 26 02:40:10 PM PDT 24 |
20235045 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2274349030 |
|
|
Mar 26 02:39:58 PM PDT 24 |
Mar 26 02:40:01 PM PDT 24 |
75552818 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3842619030 |
|
|
Mar 26 02:40:06 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
124053339 ps |
| T61 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2110355165 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
219919254 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.990912280 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:18 PM PDT 24 |
23163131 ps |
| T109 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2107730492 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
569924427 ps |
| T110 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.497016482 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
358154916 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4247809309 |
|
|
Mar 26 02:40:14 PM PDT 24 |
Mar 26 02:40:15 PM PDT 24 |
44952829 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.69936457 |
|
|
Mar 26 02:40:35 PM PDT 24 |
Mar 26 02:40:36 PM PDT 24 |
27006959 ps |
| T937 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3853079980 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
912110663 ps |
| T938 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.202389860 |
|
|
Mar 26 02:40:25 PM PDT 24 |
Mar 26 02:40:28 PM PDT 24 |
414519733 ps |
| T939 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3582141904 |
|
|
Mar 26 02:40:04 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
364568378 ps |
| T940 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3880880385 |
|
|
Mar 26 02:40:25 PM PDT 24 |
Mar 26 02:40:28 PM PDT 24 |
221718501 ps |
| T128 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1560112743 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
82635760 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3321596972 |
|
|
Mar 26 02:39:53 PM PDT 24 |
Mar 26 02:39:54 PM PDT 24 |
15642035 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2873676723 |
|
|
Mar 26 02:40:05 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
94059971 ps |
| T135 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4128031440 |
|
|
Mar 26 02:40:04 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
94336371 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2883680751 |
|
|
Mar 26 02:39:52 PM PDT 24 |
Mar 26 02:39:54 PM PDT 24 |
24956130 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.202731621 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
79015322 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2173366601 |
|
|
Mar 26 02:39:54 PM PDT 24 |
Mar 26 02:39:55 PM PDT 24 |
158740161 ps |
| T942 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1776921410 |
|
|
Mar 26 02:40:37 PM PDT 24 |
Mar 26 02:40:40 PM PDT 24 |
132539936 ps |
| T64 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2472346793 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
76248564 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3603875716 |
|
|
Mar 26 02:40:03 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
100028952 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3868677845 |
|
|
Mar 26 02:39:52 PM PDT 24 |
Mar 26 02:39:56 PM PDT 24 |
395079987 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3406524761 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:03 PM PDT 24 |
19991088 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2233794326 |
|
|
Mar 26 02:40:32 PM PDT 24 |
Mar 26 02:40:33 PM PDT 24 |
40022234 ps |
| T67 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1426167789 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
396936417 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.852219120 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:56 PM PDT 24 |
30589549 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1256658696 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:03 PM PDT 24 |
44173648 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1404826338 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:23 PM PDT 24 |
1544731944 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3966987934 |
|
|
Mar 26 02:40:04 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
36111391 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1933869695 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
452604514 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1727230356 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:56 PM PDT 24 |
45128339 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2030889273 |
|
|
Mar 26 02:40:21 PM PDT 24 |
Mar 26 02:40:23 PM PDT 24 |
51126076 ps |
| T127 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.35845002 |
|
|
Mar 26 02:40:35 PM PDT 24 |
Mar 26 02:40:39 PM PDT 24 |
458155792 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3914666507 |
|
|
Mar 26 02:40:20 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
31381827 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3517086375 |
|
|
Mar 26 02:39:58 PM PDT 24 |
Mar 26 02:40:00 PM PDT 24 |
634772072 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.836202785 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:18 PM PDT 24 |
135300286 ps |
| T69 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3475529001 |
|
|
Mar 26 02:40:05 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
229085597 ps |
| T70 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2281870258 |
|
|
Mar 26 02:40:16 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
1627598894 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3732921922 |
|
|
Mar 26 02:40:12 PM PDT 24 |
Mar 26 02:40:15 PM PDT 24 |
363015561 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1336967853 |
|
|
Mar 26 02:40:13 PM PDT 24 |
Mar 26 02:40:15 PM PDT 24 |
39000395 ps |
| T89 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3083173443 |
|
|
Mar 26 02:40:35 PM PDT 24 |
Mar 26 02:40:37 PM PDT 24 |
434808049 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.649364483 |
|
|
Mar 26 02:39:59 PM PDT 24 |
Mar 26 02:40:01 PM PDT 24 |
144189039 ps |
| T130 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1722398095 |
|
|
Mar 26 02:40:05 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
309793054 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1350062775 |
|
|
Mar 26 02:40:33 PM PDT 24 |
Mar 26 02:40:34 PM PDT 24 |
54199018 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2194498301 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:18 PM PDT 24 |
105585420 ps |
| T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.361964258 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:18 PM PDT 24 |
52543457 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.438371428 |
|
|
Mar 26 02:39:59 PM PDT 24 |
Mar 26 02:39:59 PM PDT 24 |
23936263 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.679042325 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
472955637 ps |
| T958 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2924137000 |
|
|
Mar 26 02:40:36 PM PDT 24 |
Mar 26 02:40:39 PM PDT 24 |
62572327 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1895286993 |
|
|
Mar 26 02:40:34 PM PDT 24 |
Mar 26 02:40:38 PM PDT 24 |
42353515 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2738306536 |
|
|
Mar 26 02:40:34 PM PDT 24 |
Mar 26 02:40:35 PM PDT 24 |
15570295 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1454577777 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
30679625 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2941514588 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:57 PM PDT 24 |
104873867 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3198860456 |
|
|
Mar 26 02:39:54 PM PDT 24 |
Mar 26 02:39:57 PM PDT 24 |
464869366 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1832672930 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:21 PM PDT 24 |
578152993 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3103803619 |
|
|
Mar 26 02:40:03 PM PDT 24 |
Mar 26 02:40:06 PM PDT 24 |
146892403 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2661865068 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:17 PM PDT 24 |
78436739 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2669692386 |
|
|
Mar 26 02:40:03 PM PDT 24 |
Mar 26 02:40:03 PM PDT 24 |
37713551 ps |
| T90 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.273852785 |
|
|
Mar 26 02:40:24 PM PDT 24 |
Mar 26 02:40:27 PM PDT 24 |
752663226 ps |
| T132 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2678404105 |
|
|
Mar 26 02:39:58 PM PDT 24 |
Mar 26 02:40:00 PM PDT 24 |
475907129 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3399147108 |
|
|
Mar 26 02:40:03 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
673344817 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2572948368 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:02 PM PDT 24 |
22547215 ps |
| T136 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3174743180 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
192982316 ps |
| T967 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2887439542 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
124654075 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4037049824 |
|
|
Mar 26 02:40:17 PM PDT 24 |
Mar 26 02:40:20 PM PDT 24 |
307255189 ps |
| T91 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4011624628 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:18 PM PDT 24 |
203076712 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2509278285 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:24 PM PDT 24 |
244621488 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3775896464 |
|
|
Mar 26 02:40:06 PM PDT 24 |
Mar 26 02:40:08 PM PDT 24 |
18204851 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2143769272 |
|
|
Mar 26 02:40:32 PM PDT 24 |
Mar 26 02:40:36 PM PDT 24 |
484056329 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.809238571 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
49653927 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2841883496 |
|
|
Mar 26 02:40:21 PM PDT 24 |
Mar 26 02:40:22 PM PDT 24 |
41414978 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2887310715 |
|
|
Mar 26 02:40:18 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
21273613 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3974450319 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:56 PM PDT 24 |
10366882 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.411543871 |
|
|
Mar 26 02:40:07 PM PDT 24 |
Mar 26 02:40:09 PM PDT 24 |
13701631 ps |
| T977 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1709733717 |
|
|
Mar 26 02:40:06 PM PDT 24 |
Mar 26 02:40:08 PM PDT 24 |
12783653 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3695192215 |
|
|
Mar 26 02:40:24 PM PDT 24 |
Mar 26 02:40:25 PM PDT 24 |
42182582 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.111599765 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:03 PM PDT 24 |
55356656 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3556545718 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:22 PM PDT 24 |
3040232504 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3639507692 |
|
|
Mar 26 02:39:58 PM PDT 24 |
Mar 26 02:39:59 PM PDT 24 |
40425229 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.123657774 |
|
|
Mar 26 02:40:08 PM PDT 24 |
Mar 26 02:40:12 PM PDT 24 |
420229702 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1697444054 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:56 PM PDT 24 |
15920359 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2293325607 |
|
|
Mar 26 02:39:56 PM PDT 24 |
Mar 26 02:39:57 PM PDT 24 |
21749021 ps |
| T982 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3808801845 |
|
|
Mar 26 02:40:07 PM PDT 24 |
Mar 26 02:40:10 PM PDT 24 |
32127653 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2946177856 |
|
|
Mar 26 02:40:04 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
40856626 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3888018285 |
|
|
Mar 26 02:39:56 PM PDT 24 |
Mar 26 02:39:58 PM PDT 24 |
59327128 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1039730886 |
|
|
Mar 26 02:39:55 PM PDT 24 |
Mar 26 02:39:57 PM PDT 24 |
363583320 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4029330283 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:07 PM PDT 24 |
474885765 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2667539745 |
|
|
Mar 26 02:40:32 PM PDT 24 |
Mar 26 02:40:35 PM PDT 24 |
406901703 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2001269507 |
|
|
Mar 26 02:40:19 PM PDT 24 |
Mar 26 02:40:22 PM PDT 24 |
329464735 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2286275286 |
|
|
Mar 26 02:39:51 PM PDT 24 |
Mar 26 02:39:55 PM PDT 24 |
69412402 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3431317567 |
|
|
Mar 26 02:40:37 PM PDT 24 |
Mar 26 02:40:38 PM PDT 24 |
42063139 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3660501365 |
|
|
Mar 26 02:40:25 PM PDT 24 |
Mar 26 02:40:26 PM PDT 24 |
36352839 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2748126345 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:03 PM PDT 24 |
65772971 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3742532961 |
|
|
Mar 26 02:40:02 PM PDT 24 |
Mar 26 02:40:04 PM PDT 24 |
343237885 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.671446602 |
|
|
Mar 26 02:40:32 PM PDT 24 |
Mar 26 02:40:34 PM PDT 24 |
610179712 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2558010467 |
|
|
Mar 26 02:40:16 PM PDT 24 |
Mar 26 02:40:17 PM PDT 24 |
36617755 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.168775806 |
|
|
Mar 26 02:40:22 PM PDT 24 |
Mar 26 02:40:25 PM PDT 24 |
112006424 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2230920797 |
|
|
Mar 26 02:40:03 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
212887100 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.158111667 |
|
|
Mar 26 02:40:35 PM PDT 24 |
Mar 26 02:40:36 PM PDT 24 |
47364614 ps |
| T95 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1078062794 |
|
|
Mar 26 02:40:15 PM PDT 24 |
Mar 26 02:40:19 PM PDT 24 |
609789508 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3119106983 |
|
|
Mar 26 02:40:32 PM PDT 24 |
Mar 26 02:40:34 PM PDT 24 |
178943405 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1630935235 |
|
|
Mar 26 02:40:35 PM PDT 24 |
Mar 26 02:40:37 PM PDT 24 |
414150341 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.10900731 |
|
|
Mar 26 02:39:57 PM PDT 24 |
Mar 26 02:39:58 PM PDT 24 |
91700881 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3528063825 |
|
|
Mar 26 02:40:04 PM PDT 24 |
Mar 26 02:40:05 PM PDT 24 |
87959995 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1935031322 |
|
|
Mar 26 02:39:56 PM PDT 24 |
Mar 26 02:39:59 PM PDT 24 |
2066059001 ps |
| T131 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1990243469 |
|
|
Mar 26 02:40:25 PM PDT 24 |
Mar 26 02:40:27 PM PDT 24 |
194833610 ps |