Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147984252	1			T1	6328		T2	569874		T3	670094
instr_valid_dis	113223525	1			T1	6328		T2	569874		T3	456020
instr_en	25242238	1			T3	155570		T4	1534		T43	95198

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13002451	1			T3	42388		T7	72082		T4	1534
sram_ifetch_valid_disable	113063661	1			T1	6328		T2	569874		T3	404432
sram_ifetch_enable	21918140	1			T3	223274		T7	192192		T43	257836

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147984252	1			T1	6328		T2	569874		T3	670094
hw_debug_en_valid_off	115095841	1			T1	6328		T2	569874		T3	493338
hw_debug_en_on	22352369	1			T3	109716		T7	154128		T4	16806

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113063661	1			T1	6328		T2	569874		T3	404432
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100235110	1			T1	6328		T2	569874		T3	404432
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9783913	1			T43	23452		T23	62840		T130	68900
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5333080	1			T7	54318		T4	1534		T43	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1869094	1			T130	21942		T24	18496		T133	38024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1954164	1			T4	1534		T43	20000		T130	11666
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5543721	1			T24	220128		T58	15592		T129	152350
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1969777	1			T24	20000		T58	15592		T129	11110
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3011314	1			T24	200128		T129	38622		T27	11964
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8607349	1			T3	47490		T7	67276		T4	16806
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3023944	1			T3	47490		T43	78026		T24	75112
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4188817	1			T23	62840		T24	304408		T136	1546

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9777881	1			T3	155570		T43	51746		T130	20992
lc_exec_en	8201299	1			T3	62226		T7	86852		T43	128250
valid_exec_dis	108330653	1			T1	6328		T2	569874		T3	388530
invalid_exec_dis	34920591	1			T3	265662		T7	264274		T4	1534