Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1019
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.30 83.30 97.56 97.56 78.79 78.79 95.85 95.85 100.00 100.00 90.52 90.52 94.75 94.75 25.60 25.60 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3722696296
90.50 7.20 98.93 1.37 84.45 5.66 96.57 0.72 100.00 0.00 92.53 2.01 96.10 1.35 64.94 39.33 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4028258219
94.76 4.26 99.32 0.39 90.62 6.17 97.71 1.14 100.00 0.00 96.84 4.31 96.25 0.15 82.56 17.63 /workspace/coverage/default/4.sram_ctrl_stress_all.3900896007
95.81 1.05 99.51 0.20 91.52 0.90 97.93 0.21 100.00 0.00 97.70 0.86 96.25 0.00 87.76 5.19 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4159052260
96.71 0.90 99.51 0.00 91.77 0.26 98.21 0.29 100.00 0.00 97.70 0.00 96.25 0.00 93.51 5.75 /workspace/coverage/default/39.sram_ctrl_stress_all.1922299528
97.46 0.75 99.71 0.20 93.70 1.93 98.93 0.72 100.00 0.00 98.56 0.86 96.85 0.60 94.43 0.93 /workspace/coverage/default/1.sram_ctrl_sec_cm.20468649
97.81 0.36 99.71 0.00 93.70 0.00 98.93 0.00 100.00 0.00 98.85 0.29 97.75 0.90 95.73 1.30 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.287883168
98.01 0.20 99.71 0.00 93.70 0.00 99.00 0.07 100.00 0.00 98.85 0.00 99.10 1.35 95.73 0.00 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3006876397
98.16 0.15 99.71 0.00 93.70 0.00 99.21 0.21 100.00 0.00 98.85 0.00 99.55 0.45 96.10 0.37 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3695583734
98.28 0.12 99.71 0.00 93.96 0.26 99.21 0.00 100.00 0.00 98.85 0.00 99.55 0.00 96.66 0.56 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1024473399
98.39 0.12 99.80 0.10 93.96 0.00 99.93 0.72 100.00 0.00 98.85 0.00 99.55 0.00 96.66 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3039490378
98.50 0.11 99.80 0.00 93.96 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.40 0.74 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2871322736
98.56 0.07 99.80 0.00 94.34 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.55 0.00 97.40 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.945997554
98.62 0.05 99.80 0.00 94.34 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.77 0.37 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2477577949
98.66 0.04 99.80 0.00 94.47 0.13 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.96 0.19 /workspace/coverage/default/1.sram_ctrl_lc_escalation.2607229638
98.69 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3379608877
98.72 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/default/1.sram_ctrl_executable.2598425806
98.74 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/default/10.sram_ctrl_regwen.442190075
98.76 0.02 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2577812817


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3852264070
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1214519684
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3580727968
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1000027236
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4112833024
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.875869123
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1267175157
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2717320011
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2373506491
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.842780286
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3037991037
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3778686208
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1924388077
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3992400297
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1410007860
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1211352953
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1786537963
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1078654308
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.611760972
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.542739730
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.302345224
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4288495686
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3683435099
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1428431420
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1548578988
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2101818228
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3603844346
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1155171261
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3489628936
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.614316483
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.431906355
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2769203785
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1833766673
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2568066955
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2390439160
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2046091021
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.848235415
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1828632844
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4038927851
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.480268874
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.750128968
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1003000622
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3513231909
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3363615416
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.183745628
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1296136255
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.26997793
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3941676400
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1680985534
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.973587167
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3784067560
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2925733136
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2694011502
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3438366981
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2489150083
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4029345180
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1927695911
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2394893665
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3723777590
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.488366018
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2239225705
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2526536569
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.775262919
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3292323868
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2228494052
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3528800146
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.296380378
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3310366056
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2197719980
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2178541765
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2734278278
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1815994119
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3144531083
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.281920072
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2166937780
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3905727023
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.83054420
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1152871418
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1002878232
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4291390143
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.432385088
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4151086041
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1019936322
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2844535338
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.29309333
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1583665833
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3053182129
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1393165395
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3843380755
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1727837953
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.245819645
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2811526593
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3825400796
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1491522088
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.635114708
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.454146381
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1526176649
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2940780682
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.587327542
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3689173389
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2301246331
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1381575435
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.121644730
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1991556751
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3664712497
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2590774136
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.568030358
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.650744205
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3832809580
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1787328739
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4065572437
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4231140177
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.228404255
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4235489803
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.224837107
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4046226390
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1941001029
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2971623165
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1559081635
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.126643963
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4020031504
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1983623118
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3947890127
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.339660012
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2304622688
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1403852769
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1933710519
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1762370850
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.144586059
/workspace/coverage/default/0.sram_ctrl_alert_test.2720964333
/workspace/coverage/default/0.sram_ctrl_bijection.1212651796
/workspace/coverage/default/0.sram_ctrl_executable.2985109230
/workspace/coverage/default/0.sram_ctrl_lc_escalation.527012503
/workspace/coverage/default/0.sram_ctrl_max_throughput.3738806467
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1125151292
/workspace/coverage/default/0.sram_ctrl_mem_walk.1465666334
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2495897567
/workspace/coverage/default/0.sram_ctrl_partial_access.3871043474
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2588768012
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2708725011
/workspace/coverage/default/0.sram_ctrl_regwen.2379265675
/workspace/coverage/default/0.sram_ctrl_sec_cm.2681981899
/workspace/coverage/default/0.sram_ctrl_smoke.1407598490
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.958287029
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3561073802
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1361380630
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4186418874
/workspace/coverage/default/1.sram_ctrl_bijection.2340639898
/workspace/coverage/default/1.sram_ctrl_max_throughput.3916861748
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2841667676
/workspace/coverage/default/1.sram_ctrl_mem_walk.881115190
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2953020655
/workspace/coverage/default/1.sram_ctrl_partial_access.862557830
/workspace/coverage/default/1.sram_ctrl_smoke.2338247863
/workspace/coverage/default/1.sram_ctrl_stress_all.3440980435
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3680672766
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1008564811
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1141162386
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3508218554
/workspace/coverage/default/10.sram_ctrl_alert_test.1185131592
/workspace/coverage/default/10.sram_ctrl_bijection.1428155016
/workspace/coverage/default/10.sram_ctrl_executable.274902838
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1890241597
/workspace/coverage/default/10.sram_ctrl_max_throughput.2147833850
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.400004898
/workspace/coverage/default/10.sram_ctrl_mem_walk.2448304707
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3572232552
/workspace/coverage/default/10.sram_ctrl_partial_access.3208407432
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2881041615
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2893924181
/workspace/coverage/default/10.sram_ctrl_smoke.4202920847
/workspace/coverage/default/10.sram_ctrl_stress_all.3706696666
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2147184457
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2743548788
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3462000486
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3705455219
/workspace/coverage/default/11.sram_ctrl_alert_test.119358544
/workspace/coverage/default/11.sram_ctrl_bijection.190206587
/workspace/coverage/default/11.sram_ctrl_executable.4116457079
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1538177732
/workspace/coverage/default/11.sram_ctrl_max_throughput.3656646050
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.161332251
/workspace/coverage/default/11.sram_ctrl_mem_walk.614029439
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2946831063
/workspace/coverage/default/11.sram_ctrl_partial_access.3871013245
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2303183141
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3127113331
/workspace/coverage/default/11.sram_ctrl_regwen.3217532862
/workspace/coverage/default/11.sram_ctrl_smoke.1922149573
/workspace/coverage/default/11.sram_ctrl_stress_all.1308086476
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2263202902
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4031298213
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3426223700
/workspace/coverage/default/12.sram_ctrl_alert_test.2175201471
/workspace/coverage/default/12.sram_ctrl_bijection.4024768193
/workspace/coverage/default/12.sram_ctrl_executable.2688231600
/workspace/coverage/default/12.sram_ctrl_lc_escalation.892710974
/workspace/coverage/default/12.sram_ctrl_max_throughput.4186207863
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.350148065
/workspace/coverage/default/12.sram_ctrl_mem_walk.275132264
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2982885186
/workspace/coverage/default/12.sram_ctrl_partial_access.2937348702
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3057405460
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1923716387
/workspace/coverage/default/12.sram_ctrl_regwen.1324186381
/workspace/coverage/default/12.sram_ctrl_smoke.346947589
/workspace/coverage/default/12.sram_ctrl_stress_all.3332758934
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/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.95602703
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.261564621
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3677115031
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2514184751
/workspace/coverage/default/44.sram_ctrl_alert_test.2815914880
/workspace/coverage/default/44.sram_ctrl_bijection.910975716
/workspace/coverage/default/44.sram_ctrl_executable.1792774794
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3654195671
/workspace/coverage/default/44.sram_ctrl_max_throughput.1533015538
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1873023946
/workspace/coverage/default/44.sram_ctrl_mem_walk.1065256874
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3802273772
/workspace/coverage/default/44.sram_ctrl_partial_access.756261137
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1170894942
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3272689275
/workspace/coverage/default/44.sram_ctrl_regwen.1219626501
/workspace/coverage/default/44.sram_ctrl_smoke.3267541478
/workspace/coverage/default/44.sram_ctrl_stress_all.761162645
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.823744820
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2025156559
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2174983165
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.85094966
/workspace/coverage/default/45.sram_ctrl_alert_test.2148300214
/workspace/coverage/default/45.sram_ctrl_bijection.3049710334
/workspace/coverage/default/45.sram_ctrl_executable.643008433
/workspace/coverage/default/45.sram_ctrl_lc_escalation.647383151
/workspace/coverage/default/45.sram_ctrl_max_throughput.761938568
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1549190442
/workspace/coverage/default/45.sram_ctrl_mem_walk.4087408127
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2120182374
/workspace/coverage/default/45.sram_ctrl_partial_access.3023022696
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.734862917
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1739144037
/workspace/coverage/default/45.sram_ctrl_regwen.1057044935
/workspace/coverage/default/45.sram_ctrl_smoke.620720941
/workspace/coverage/default/45.sram_ctrl_stress_all.1741719241
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2791730161
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2556721926
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2458062065
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2631649250
/workspace/coverage/default/46.sram_ctrl_alert_test.1794294241
/workspace/coverage/default/46.sram_ctrl_bijection.660034099
/workspace/coverage/default/46.sram_ctrl_executable.2083525997
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1780326584
/workspace/coverage/default/46.sram_ctrl_max_throughput.2340414985
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2069492493
/workspace/coverage/default/46.sram_ctrl_mem_walk.969344525
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2555365395
/workspace/coverage/default/46.sram_ctrl_partial_access.3718556932
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2940382250
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3782004058
/workspace/coverage/default/46.sram_ctrl_regwen.3871855097
/workspace/coverage/default/46.sram_ctrl_smoke.3264256868
/workspace/coverage/default/46.sram_ctrl_stress_all.964339119
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2260369949
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1030135559
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3333802932
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2946337382
/workspace/coverage/default/47.sram_ctrl_alert_test.3870368636
/workspace/coverage/default/47.sram_ctrl_bijection.1097909551
/workspace/coverage/default/47.sram_ctrl_executable.1053361416
/workspace/coverage/default/47.sram_ctrl_lc_escalation.498978654
/workspace/coverage/default/47.sram_ctrl_max_throughput.1195694018
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1085894769
/workspace/coverage/default/47.sram_ctrl_mem_walk.1685124547
/workspace/coverage/default/47.sram_ctrl_multiple_keys.673678293
/workspace/coverage/default/47.sram_ctrl_partial_access.986457778
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2982840813
/workspace/coverage/default/47.sram_ctrl_ram_cfg.529093701
/workspace/coverage/default/47.sram_ctrl_regwen.1677331756
/workspace/coverage/default/47.sram_ctrl_smoke.3250478416
/workspace/coverage/default/47.sram_ctrl_stress_all.2486938225
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.80564104
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2065667657
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1936623788
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2475239417
/workspace/coverage/default/48.sram_ctrl_alert_test.2315192790
/workspace/coverage/default/48.sram_ctrl_bijection.1118561803
/workspace/coverage/default/48.sram_ctrl_executable.2500118315
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2031420445
/workspace/coverage/default/48.sram_ctrl_max_throughput.1034165768
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3393445893
/workspace/coverage/default/48.sram_ctrl_mem_walk.3327269071
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2020650271
/workspace/coverage/default/48.sram_ctrl_partial_access.3595577753
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3586475144
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2136264525
/workspace/coverage/default/48.sram_ctrl_regwen.3127408968
/workspace/coverage/default/48.sram_ctrl_smoke.913814094
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4078269704
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.255283825
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.942165446
/workspace/coverage/default/49.sram_ctrl_alert_test.439761207
/workspace/coverage/default/49.sram_ctrl_bijection.2861874487
/workspace/coverage/default/49.sram_ctrl_executable.739571060
/workspace/coverage/default/49.sram_ctrl_max_throughput.2955719107
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3137505037
/workspace/coverage/default/49.sram_ctrl_mem_walk.682838005
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3870495179
/workspace/coverage/default/49.sram_ctrl_partial_access.1330025920
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1782098480
/workspace/coverage/default/49.sram_ctrl_ram_cfg.453346355
/workspace/coverage/default/49.sram_ctrl_regwen.3829575952
/workspace/coverage/default/49.sram_ctrl_smoke.3282971237
/workspace/coverage/default/49.sram_ctrl_stress_all.1108109834
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2402416183
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3348086186
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1485987899
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1265026880
/workspace/coverage/default/5.sram_ctrl_alert_test.4196319947
/workspace/coverage/default/5.sram_ctrl_bijection.1328381947
/workspace/coverage/default/5.sram_ctrl_executable.2092131012
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1326998543
/workspace/coverage/default/5.sram_ctrl_max_throughput.400254118
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.19776021
/workspace/coverage/default/5.sram_ctrl_mem_walk.1625428148
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1606266079
/workspace/coverage/default/5.sram_ctrl_partial_access.897592211
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.68236866
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3711482862
/workspace/coverage/default/5.sram_ctrl_regwen.3260647057
/workspace/coverage/default/5.sram_ctrl_smoke.1666011412
/workspace/coverage/default/5.sram_ctrl_stress_all.1598878387
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1938938110
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.589955989
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.4004278795
/workspace/coverage/default/6.sram_ctrl_alert_test.999186561
/workspace/coverage/default/6.sram_ctrl_bijection.547757317
/workspace/coverage/default/6.sram_ctrl_executable.690724635
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1021828548
/workspace/coverage/default/6.sram_ctrl_max_throughput.2127789065
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1328498265
/workspace/coverage/default/6.sram_ctrl_mem_walk.2532172920
/workspace/coverage/default/6.sram_ctrl_multiple_keys.304192879
/workspace/coverage/default/6.sram_ctrl_partial_access.3728968465
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4117559360
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2009813341
/workspace/coverage/default/6.sram_ctrl_regwen.2413463721
/workspace/coverage/default/6.sram_ctrl_smoke.1110527295
/workspace/coverage/default/6.sram_ctrl_stress_all.1920500439
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.644285002
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.135996325
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.628124857
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1539502766
/workspace/coverage/default/7.sram_ctrl_alert_test.516236504
/workspace/coverage/default/7.sram_ctrl_bijection.3227258896
/workspace/coverage/default/7.sram_ctrl_executable.441006569
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2321362981
/workspace/coverage/default/7.sram_ctrl_max_throughput.214905703
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3785989244
/workspace/coverage/default/7.sram_ctrl_mem_walk.1347998578
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2837503876
/workspace/coverage/default/7.sram_ctrl_partial_access.3424869891
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3354180154
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1559044979
/workspace/coverage/default/7.sram_ctrl_regwen.177470620
/workspace/coverage/default/7.sram_ctrl_smoke.3854905839
/workspace/coverage/default/7.sram_ctrl_stress_all.2636979180
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3137637464
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3725556380
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1633827469
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3869083185
/workspace/coverage/default/8.sram_ctrl_alert_test.3155832797
/workspace/coverage/default/8.sram_ctrl_bijection.59387847
/workspace/coverage/default/8.sram_ctrl_executable.623217759
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2386345225
/workspace/coverage/default/8.sram_ctrl_max_throughput.2577320850
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2600101611
/workspace/coverage/default/8.sram_ctrl_mem_walk.2772481603
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4207606257
/workspace/coverage/default/8.sram_ctrl_partial_access.3176160673
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.809050537
/workspace/coverage/default/8.sram_ctrl_ram_cfg.645170933
/workspace/coverage/default/8.sram_ctrl_regwen.4055935366
/workspace/coverage/default/8.sram_ctrl_smoke.2972902759
/workspace/coverage/default/8.sram_ctrl_stress_all.1008227076
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.18057132
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.919780788
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4094997154
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1617340970
/workspace/coverage/default/9.sram_ctrl_alert_test.2782823747
/workspace/coverage/default/9.sram_ctrl_bijection.1320917512
/workspace/coverage/default/9.sram_ctrl_executable.2261356630
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2349439668
/workspace/coverage/default/9.sram_ctrl_max_throughput.3773049760
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.195840863
/workspace/coverage/default/9.sram_ctrl_mem_walk.3807623492
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3880263743
/workspace/coverage/default/9.sram_ctrl_partial_access.3110610159
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2230440747
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1515096637
/workspace/coverage/default/9.sram_ctrl_regwen.973134894
/workspace/coverage/default/9.sram_ctrl_smoke.1516789384
/workspace/coverage/default/9.sram_ctrl_stress_all.103075201
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1937055992
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.801437353
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3538050292




Total test records in report: 1019
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3722696296 Mar 28 03:13:59 PM PDT 24 Mar 28 03:14:07 PM PDT 24 2239274762 ps
T2 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2759239274 Mar 28 03:11:06 PM PDT 24 Mar 28 03:20:11 PM PDT 24 93844966351 ps
T3 /workspace/coverage/default/38.sram_ctrl_stress_all.3292614633 Mar 28 03:12:18 PM PDT 24 Mar 28 03:36:01 PM PDT 24 23332711852 ps
T6 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2065667657 Mar 28 03:13:49 PM PDT 24 Mar 28 03:17:32 PM PDT 24 2250502416 ps
T7 /workspace/coverage/default/10.sram_ctrl_regwen.442190075 Mar 28 03:08:29 PM PDT 24 Mar 28 03:26:11 PM PDT 24 21110059629 ps
T8 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.477954066 Mar 28 03:11:37 PM PDT 24 Mar 28 03:11:52 PM PDT 24 152728404 ps
T9 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2569549820 Mar 28 03:13:01 PM PDT 24 Mar 28 03:13:04 PM PDT 24 269577166 ps
T10 /workspace/coverage/default/24.sram_ctrl_alert_test.859443067 Mar 28 03:10:07 PM PDT 24 Mar 28 03:10:08 PM PDT 24 33895937 ps
T11 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.144586059 Mar 28 03:07:07 PM PDT 24 Mar 28 03:17:59 PM PDT 24 1892974515 ps
T12 /workspace/coverage/default/17.sram_ctrl_bijection.1372760308 Mar 28 03:09:24 PM PDT 24 Mar 28 03:10:35 PM PDT 24 3576533098 ps
T14 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.942165446 Mar 28 03:14:03 PM PDT 24 Mar 28 03:48:00 PM PDT 24 4918743488 ps
T15 /workspace/coverage/default/6.sram_ctrl_partial_access.3728968465 Mar 28 03:08:04 PM PDT 24 Mar 28 03:08:19 PM PDT 24 2979458743 ps
T4 /workspace/coverage/default/4.sram_ctrl_stress_all.3900896007 Mar 28 03:08:06 PM PDT 24 Mar 28 03:23:06 PM PDT 24 92160712536 ps
T69 /workspace/coverage/default/38.sram_ctrl_multiple_keys.2590706310 Mar 28 03:12:17 PM PDT 24 Mar 28 03:16:38 PM PDT 24 3171223603 ps
T70 /workspace/coverage/default/32.sram_ctrl_multiple_keys.6182869 Mar 28 03:11:20 PM PDT 24 Mar 28 03:32:44 PM PDT 24 20698771364 ps
T13 /workspace/coverage/default/23.sram_ctrl_smoke.1980469726 Mar 28 03:09:52 PM PDT 24 Mar 28 03:09:54 PM PDT 24 259658549 ps
T17 /workspace/coverage/default/22.sram_ctrl_alert_test.1949158424 Mar 28 03:09:53 PM PDT 24 Mar 28 03:09:54 PM PDT 24 11392763 ps
T137 /workspace/coverage/default/20.sram_ctrl_bijection.1094749208 Mar 28 03:09:37 PM PDT 24 Mar 28 03:10:39 PM PDT 24 994825889 ps
T28 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4028258219 Mar 28 03:08:07 PM PDT 24 Mar 28 03:12:01 PM PDT 24 675299162 ps
T51 /workspace/coverage/default/48.sram_ctrl_mem_walk.3327269071 Mar 28 03:13:43 PM PDT 24 Mar 28 03:13:53 PM PDT 24 1565852602 ps
T16 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3467383173 Mar 28 03:12:53 PM PDT 24 Mar 28 03:34:46 PM PDT 24 18342099793 ps
T52 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1024473399 Mar 28 03:10:27 PM PDT 24 Mar 28 03:20:15 PM PDT 24 3157140076 ps
T53 /workspace/coverage/default/0.sram_ctrl_mem_walk.1465666334 Mar 28 03:07:07 PM PDT 24 Mar 28 03:07:14 PM PDT 24 232686701 ps
T54 /workspace/coverage/default/16.sram_ctrl_partial_access.4153351369 Mar 28 03:09:04 PM PDT 24 Mar 28 03:11:29 PM PDT 24 729348036 ps
T55 /workspace/coverage/default/24.sram_ctrl_partial_access.581599626 Mar 28 03:10:08 PM PDT 24 Mar 28 03:10:34 PM PDT 24 774772241 ps
T30 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3086855000 Mar 28 03:11:05 PM PDT 24 Mar 28 03:11:06 PM PDT 24 45079473 ps
T43 /workspace/coverage/default/49.sram_ctrl_executable.739571060 Mar 28 03:13:58 PM PDT 24 Mar 28 03:46:33 PM PDT 24 63746421239 ps
T23 /workspace/coverage/default/27.sram_ctrl_stress_all.434102623 Mar 28 03:10:46 PM PDT 24 Mar 28 03:19:21 PM PDT 24 20761986012 ps
T75 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.287883168 Mar 28 03:11:21 PM PDT 24 Mar 28 03:11:27 PM PDT 24 661817482 ps
T139 /workspace/coverage/default/49.sram_ctrl_smoke.3282971237 Mar 28 03:13:48 PM PDT 24 Mar 28 03:15:14 PM PDT 24 1011119369 ps
T94 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.792632726 Mar 28 03:09:22 PM PDT 24 Mar 28 03:13:25 PM PDT 24 62355021979 ps
T76 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3502297507 Mar 28 03:09:34 PM PDT 24 Mar 28 03:14:40 PM PDT 24 3386275761 ps
T140 /workspace/coverage/default/33.sram_ctrl_partial_access.979385058 Mar 28 03:11:20 PM PDT 24 Mar 28 03:12:10 PM PDT 24 965279569 ps
T95 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.801437353 Mar 28 03:08:24 PM PDT 24 Mar 28 03:12:00 PM PDT 24 19756123093 ps
T18 /workspace/coverage/default/21.sram_ctrl_alert_test.2670285315 Mar 28 03:09:56 PM PDT 24 Mar 28 03:09:56 PM PDT 24 12921779 ps
T141 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2472906815 Mar 28 03:10:09 PM PDT 24 Mar 28 03:10:57 PM PDT 24 173219255 ps
T77 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1549190442 Mar 28 03:13:23 PM PDT 24 Mar 28 03:13:25 PM PDT 24 158295628 ps
T138 /workspace/coverage/default/40.sram_ctrl_max_throughput.82561008 Mar 28 03:12:22 PM PDT 24 Mar 28 03:13:51 PM PDT 24 1885286761 ps
T130 /workspace/coverage/default/43.sram_ctrl_executable.2220571818 Mar 28 03:12:54 PM PDT 24 Mar 28 03:26:25 PM PDT 24 21505386785 ps
T142 /workspace/coverage/default/20.sram_ctrl_smoke.2347017341 Mar 28 03:09:33 PM PDT 24 Mar 28 03:11:02 PM PDT 24 108524022 ps
T143 /workspace/coverage/default/35.sram_ctrl_mem_walk.2765792484 Mar 28 03:12:00 PM PDT 24 Mar 28 03:12:08 PM PDT 24 543427943 ps
T5 /workspace/coverage/default/33.sram_ctrl_stress_all.1464723448 Mar 28 03:11:38 PM PDT 24 Mar 28 03:12:44 PM PDT 24 2111979040 ps
T19 /workspace/coverage/default/3.sram_ctrl_alert_test.431902604 Mar 28 03:07:47 PM PDT 24 Mar 28 03:07:47 PM PDT 24 12523625 ps
T29 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3695583734 Mar 28 03:09:19 PM PDT 24 Mar 28 03:09:35 PM PDT 24 364372779 ps
T56 /workspace/coverage/default/34.sram_ctrl_stress_all.3558482058 Mar 28 03:11:38 PM PDT 24 Mar 28 03:22:32 PM PDT 24 10891531617 ps
T111 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3880263743 Mar 28 03:08:20 PM PDT 24 Mar 28 03:10:25 PM PDT 24 25103011009 ps
T96 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2577812817 Mar 28 03:07:07 PM PDT 24 Mar 28 03:13:59 PM PDT 24 91783688099 ps
T112 /workspace/coverage/default/28.sram_ctrl_max_throughput.1852112710 Mar 28 03:10:49 PM PDT 24 Mar 28 03:12:03 PM PDT 24 148961367 ps
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T173 /workspace/coverage/default/1.sram_ctrl_alert_test.945997554 Mar 28 03:07:46 PM PDT 24 Mar 28 03:07:47 PM PDT 24 21985218 ps
T174 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1854223294 Mar 28 03:09:53 PM PDT 24 Mar 28 03:15:13 PM PDT 24 15432677268 ps
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T135 /workspace/coverage/default/9.sram_ctrl_regwen.973134894 Mar 28 03:08:16 PM PDT 24 Mar 28 03:22:06 PM PDT 24 2015148529 ps
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T181 /workspace/coverage/default/49.sram_ctrl_partial_access.1330025920 Mar 28 03:13:59 PM PDT 24 Mar 28 03:14:41 PM PDT 24 426379159 ps
T182 /workspace/coverage/default/30.sram_ctrl_stress_all.3753521353 Mar 28 03:11:05 PM PDT 24 Mar 28 03:48:15 PM PDT 24 448580235631 ps
T183 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2048640426 Mar 28 03:11:41 PM PDT 24 Mar 28 03:29:45 PM PDT 24 8131622791 ps
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T185 /workspace/coverage/default/14.sram_ctrl_alert_test.3286847656 Mar 28 03:09:04 PM PDT 24 Mar 28 03:09:05 PM PDT 24 34853804 ps
T186 /workspace/coverage/default/26.sram_ctrl_regwen.487195743 Mar 28 03:10:28 PM PDT 24 Mar 28 03:30:17 PM PDT 24 13390588948 ps
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T188 /workspace/coverage/default/44.sram_ctrl_stress_all.761162645 Mar 28 03:13:22 PM PDT 24 Mar 28 03:54:37 PM PDT 24 43515377506 ps
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T192 /workspace/coverage/default/14.sram_ctrl_max_throughput.267346261 Mar 28 03:09:02 PM PDT 24 Mar 28 03:09:04 PM PDT 24 307570792 ps
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T198 /workspace/coverage/default/45.sram_ctrl_alert_test.2148300214 Mar 28 03:13:19 PM PDT 24 Mar 28 03:13:19 PM PDT 24 43855974 ps
T199 /workspace/coverage/default/16.sram_ctrl_bijection.3742183452 Mar 28 03:09:03 PM PDT 24 Mar 28 03:10:27 PM PDT 24 5937247650 ps
T200 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.4264598657 Mar 28 03:09:52 PM PDT 24 Mar 28 03:14:32 PM PDT 24 11523766279 ps
T201 /workspace/coverage/default/23.sram_ctrl_alert_test.1859734373 Mar 28 03:10:05 PM PDT 24 Mar 28 03:10:06 PM PDT 24 51553416 ps
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T205 /workspace/coverage/default/42.sram_ctrl_alert_test.2031949160 Mar 28 03:12:54 PM PDT 24 Mar 28 03:12:55 PM PDT 24 35088166 ps
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T208 /workspace/coverage/default/23.sram_ctrl_lc_escalation.3867466194 Mar 28 03:10:08 PM PDT 24 Mar 28 03:10:14 PM PDT 24 3954275266 ps
T209 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3354180154 Mar 28 03:08:16 PM PDT 24 Mar 28 03:15:00 PM PDT 24 5764092028 ps
T210 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1170911854 Mar 28 03:11:19 PM PDT 24 Mar 28 03:13:40 PM PDT 24 611020497 ps
T44 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2328468299 Mar 28 03:11:33 PM PDT 24 Mar 28 03:13:46 PM PDT 24 9494938609 ps
T211 /workspace/coverage/default/4.sram_ctrl_smoke.3414784996 Mar 28 03:07:48 PM PDT 24 Mar 28 03:08:43 PM PDT 24 1721158830 ps
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T212 /workspace/coverage/default/31.sram_ctrl_partial_access.1395365025 Mar 28 03:11:04 PM PDT 24 Mar 28 03:11:11 PM PDT 24 166795604 ps
T213 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2136264525 Mar 28 03:13:47 PM PDT 24 Mar 28 03:13:48 PM PDT 24 26582864 ps
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T219 /workspace/coverage/default/9.sram_ctrl_executable.2261356630 Mar 28 03:08:16 PM PDT 24 Mar 28 03:14:39 PM PDT 24 5935623744 ps
T220 /workspace/coverage/default/26.sram_ctrl_multiple_keys.1473526965 Mar 28 03:10:29 PM PDT 24 Mar 28 03:24:58 PM PDT 24 10372086512 ps
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T222 /workspace/coverage/default/15.sram_ctrl_bijection.142694193 Mar 28 03:09:04 PM PDT 24 Mar 28 03:10:08 PM PDT 24 7129569346 ps
T223 /workspace/coverage/default/7.sram_ctrl_alert_test.516236504 Mar 28 03:08:07 PM PDT 24 Mar 28 03:08:08 PM PDT 24 38151324 ps
T224 /workspace/coverage/default/25.sram_ctrl_bijection.538825101 Mar 28 03:10:24 PM PDT 24 Mar 28 03:11:21 PM PDT 24 3672031964 ps
T225 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1871636207 Mar 28 03:09:33 PM PDT 24 Mar 28 03:14:21 PM PDT 24 6185133579 ps
T226 /workspace/coverage/default/31.sram_ctrl_max_throughput.4091694561 Mar 28 03:11:03 PM PDT 24 Mar 28 03:11:14 PM PDT 24 128047168 ps
T227 /workspace/coverage/default/39.sram_ctrl_lc_escalation.2929109539 Mar 28 03:12:22 PM PDT 24 Mar 28 03:12:28 PM PDT 24 881934556 ps
T228 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3486290572 Mar 28 03:12:19 PM PDT 24 Mar 28 03:15:57 PM PDT 24 2322595121 ps
T229 /workspace/coverage/default/35.sram_ctrl_multiple_keys.234352603 Mar 28 03:11:38 PM PDT 24 Mar 28 03:26:56 PM PDT 24 5390019409 ps
T230 /workspace/coverage/default/14.sram_ctrl_executable.1308202679 Mar 28 03:09:04 PM PDT 24 Mar 28 03:27:33 PM PDT 24 17604044610 ps
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T232 /workspace/coverage/default/11.sram_ctrl_executable.4116457079 Mar 28 03:08:47 PM PDT 24 Mar 28 03:45:01 PM PDT 24 8223671766 ps
T233 /workspace/coverage/default/27.sram_ctrl_bijection.2105083271 Mar 28 03:10:28 PM PDT 24 Mar 28 03:11:21 PM PDT 24 2829455201 ps
T234 /workspace/coverage/default/42.sram_ctrl_bijection.3990143788 Mar 28 03:12:36 PM PDT 24 Mar 28 03:13:37 PM PDT 24 5405760195 ps
T235 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3886152055 Mar 28 03:10:05 PM PDT 24 Mar 28 03:10:08 PM PDT 24 44622314 ps
T236 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2901678612 Mar 28 03:11:21 PM PDT 24 Mar 28 03:11:22 PM PDT 24 26744728 ps
T132 /workspace/coverage/default/6.sram_ctrl_stress_all.1920500439 Mar 28 03:08:10 PM PDT 24 Mar 28 03:58:18 PM PDT 24 31280486755 ps
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T239 /workspace/coverage/default/28.sram_ctrl_mem_walk.1727288743 Mar 28 03:10:46 PM PDT 24 Mar 28 03:10:57 PM PDT 24 1177857211 ps
T240 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3127082240 Mar 28 03:09:54 PM PDT 24 Mar 28 03:10:20 PM PDT 24 371462790 ps
T241 /workspace/coverage/default/13.sram_ctrl_ram_cfg.152079785 Mar 28 03:09:02 PM PDT 24 Mar 28 03:09:04 PM PDT 24 32749131 ps
T242 /workspace/coverage/default/45.sram_ctrl_regwen.1057044935 Mar 28 03:13:24 PM PDT 24 Mar 28 03:26:42 PM PDT 24 2951275390 ps
T243 /workspace/coverage/default/35.sram_ctrl_ram_cfg.3007318794 Mar 28 03:12:00 PM PDT 24 Mar 28 03:12:01 PM PDT 24 43484458 ps
T244 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2314727405 Mar 28 03:10:06 PM PDT 24 Mar 28 03:29:25 PM PDT 24 11382019720 ps
T245 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1442278320 Mar 28 03:11:07 PM PDT 24 Mar 28 03:16:26 PM PDT 24 14943743742 ps
T246 /workspace/coverage/default/48.sram_ctrl_regwen.3127408968 Mar 28 03:13:42 PM PDT 24 Mar 28 03:25:02 PM PDT 24 13018399778 ps
T247 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1287019304 Mar 28 03:09:57 PM PDT 24 Mar 28 03:26:19 PM PDT 24 17656469489 ps
T248 /workspace/coverage/default/48.sram_ctrl_smoke.913814094 Mar 28 03:13:47 PM PDT 24 Mar 28 03:14:39 PM PDT 24 873682825 ps
T249 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1008564811 Mar 28 03:07:08 PM PDT 24 Mar 28 03:11:11 PM PDT 24 5260899143 ps
T250 /workspace/coverage/default/15.sram_ctrl_partial_access.2689356243 Mar 28 03:09:01 PM PDT 24 Mar 28 03:09:03 PM PDT 24 354518260 ps
T251 /workspace/coverage/default/2.sram_ctrl_executable.4049621260 Mar 28 03:07:46 PM PDT 24 Mar 28 03:22:56 PM PDT 24 10346297245 ps
T252 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1429221501 Mar 28 03:12:36 PM PDT 24 Mar 28 03:14:18 PM PDT 24 410837791 ps
T253 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3196798469 Mar 28 03:10:25 PM PDT 24 Mar 28 03:15:42 PM PDT 24 12768230233 ps
T254 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.376652458 Mar 28 03:11:19 PM PDT 24 Mar 28 03:16:46 PM PDT 24 14529780651 ps
T255 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.68236866 Mar 28 03:08:05 PM PDT 24 Mar 28 03:11:18 PM PDT 24 34618057463 ps
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T257 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1107468166 Mar 28 03:11:05 PM PDT 24 Mar 28 03:12:42 PM PDT 24 843952557 ps
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