Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44084019	1			T1	223		T2	52212		T3	238655
triple_byte_access	2561426	1			T1	2		T2	46468		T3	4800
halfword_access	3844794	1			T1	10		T2	69678		T3	7032
byte_access	5129848	1			T1	7		T2	93267		T3	9750
zero_access	1292171	1			T1	1		T2	23312		T3	2458

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28412287

1

T1

121

T2

142857

T3

130834

auto[1]

28499971

1

T1

122

T2

142080

T3

131861

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22001358	1			T1	113		T2	26181		T3	118960
auto[0]	triple_byte_access	1277379	1			T1	1		T2	23246		T3	2365
auto[0]	halfword_access	1919265	1			T1	3		T2	35054		T3	3461
auto[0]	byte_access	2564473	1			T1	3		T2	46678		T3	4881
auto[0]	zero_access	649812	1			T1	1		T2	11698		T3	1167
auto[1]	word_access	22082661	1			T1	110		T2	26031		T3	119695
auto[1]	triple_byte_access	1284047	1			T1	1		T2	23222		T3	2435
auto[1]	halfword_access	1925529	1			T1	7		T2	34624		T3	3571
auto[1]	byte_access	2565375	1			T1	4		T2	46589		T3	4869
auto[1]	zero_access	642359	1			T2	11614		T3	1291		T6	771