Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13839753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59707964

1

T1

113

T3

112686

T4

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36664635	1			T1	879		T3	62345		T4	366
values[0x0]	17060578	1			T1	365		T3	29670		T4	192
values[0x1]	19822504	1			T1	784		T3	32014		T4	408

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6901752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66645965

1

T1

905

T3

118391

T4

441

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	273920	1			T1	12		T3	525		T4	5
valid_sources[0x01]	279064	1			T1	8		T3	502		T9	692
valid_sources[0x02]	259133	1			T1	9		T3	481		T4	10
valid_sources[0x03]	371000	1			T1	4		T3	492		T4	4
valid_sources[0x04]	307403	1			T1	16		T3	473		T4	4
valid_sources[0x05]	251073	1			T1	15		T3	526		T4	4
valid_sources[0x06]	244121	1			T1	5		T3	467		T4	7
valid_sources[0x07]	267046	1			T1	13		T3	464		T4	9
valid_sources[0x08]	246067	1			T1	6		T3	509		T4	4
valid_sources[0x09]	265816	1			T1	1		T3	512		T9	716
valid_sources[0x0a]	304067	1			T1	6		T3	492		T4	4
valid_sources[0x0b]	309343	1			T1	7		T3	460		T4	7
valid_sources[0x0c]	328567	1			T1	8		T3	531		T4	10
valid_sources[0x0d]	291774	1			T1	4		T3	519		T4	2
valid_sources[0x0e]	253650	1			T1	4		T3	469		T4	2
valid_sources[0x0f]	297895	1			T1	11		T3	461		T4	2
valid_sources[0x10]	264947	1			T1	9		T3	443		T4	9
valid_sources[0x11]	287404	1			T1	9		T3	470		T4	7
valid_sources[0x12]	271656	1			T1	18		T3	497		T4	3
valid_sources[0x13]	358789	1			T1	3		T3	511		T4	3
valid_sources[0x14]	273529	1			T1	9		T3	478		T9	722
valid_sources[0x15]	262547	1			T1	10		T3	492		T4	4
valid_sources[0x16]	315703	1			T1	11		T3	462		T4	3
valid_sources[0x17]	256879	1			T1	5		T3	492		T9	686
valid_sources[0x18]	264898	1			T1	8		T3	497		T9	728
valid_sources[0x19]	353321	1			T1	3		T3	460		T4	3
valid_sources[0x1a]	283432	1			T1	7		T3	500		T4	5
valid_sources[0x1b]	314956	1			T1	5		T3	494		T4	5
valid_sources[0x1c]	319183	1			T1	6		T3	538		T4	1
valid_sources[0x1d]	257333	1			T1	12		T3	472		T4	3
valid_sources[0x1e]	249847	1			T1	7		T3	476		T4	3
valid_sources[0x1f]	250607	1			T1	11		T3	482		T4	3
valid_sources[0x20]	284683	1			T1	11		T3	484		T4	12
valid_sources[0x21]	246364	1			T1	6		T3	432		T4	5
valid_sources[0x22]	252326	1			T1	7		T3	516		T4	5
valid_sources[0x23]	272294	1			T1	16		T3	475		T4	3
valid_sources[0x24]	255212	1			T1	5		T3	461		T4	5
valid_sources[0x25]	292936	1			T1	8		T3	454		T4	7
valid_sources[0x26]	251435	1			T1	7		T3	513		T4	6
valid_sources[0x27]	270358	1			T1	11		T3	478		T4	1
valid_sources[0x28]	306824	1			T1	7		T3	511		T4	2
valid_sources[0x29]	248743	1			T1	7		T3	476		T4	5
valid_sources[0x2a]	280041	1			T1	8		T3	515		T4	3
valid_sources[0x2b]	289750	1			T1	7		T3	527		T4	5
valid_sources[0x2c]	256006	1			T1	9		T3	460		T4	7
valid_sources[0x2d]	409928	1			T1	11		T3	487		T4	11
valid_sources[0x2e]	265996	1			T1	6		T3	468		T4	2
valid_sources[0x2f]	242751	1			T1	10		T3	485		T4	4
valid_sources[0x30]	288393	1			T1	7		T3	462		T4	6
valid_sources[0x31]	261292	1			T1	8		T3	467		T4	3
valid_sources[0x32]	339748	1			T1	5		T3	448		T4	6
valid_sources[0x33]	274484	1			T1	9		T3	522		T9	706
valid_sources[0x34]	281649	1			T1	10		T3	455		T4	2
valid_sources[0x35]	259694	1			T1	7		T3	482		T4	2
valid_sources[0x36]	276113	1			T1	13		T3	452		T4	4
valid_sources[0x37]	322492	1			T1	5		T3	502		T4	9
valid_sources[0x38]	302495	1			T1	8		T3	477		T4	5
valid_sources[0x39]	309884	1			T1	5		T3	481		T4	9
valid_sources[0x3a]	287072	1			T1	5		T3	464		T4	3
valid_sources[0x3b]	291935	1			T1	3		T3	533		T4	4
valid_sources[0x3c]	269015	1			T1	12		T3	494		T4	1
valid_sources[0x3d]	263331	1			T1	8		T3	509		T4	3
valid_sources[0x3e]	287734	1			T1	4		T3	467		T9	731
valid_sources[0x3f]	261694	1			T1	17		T3	481		T4	3
valid_sources[0x40]	268294	1			T1	3		T3	386		T4	3
valid_sources[0x41]	369750	1			T1	7		T3	462		T4	4
valid_sources[0x42]	265637	1			T1	8		T3	521		T4	3
valid_sources[0x43]	250909	1			T1	8		T3	480		T4	8
valid_sources[0x44]	251646	1			T1	5		T3	501		T4	3
valid_sources[0x45]	333795	1			T1	9		T3	453		T4	6
valid_sources[0x46]	247686	1			T1	9		T3	465		T4	13
valid_sources[0x47]	253163	1			T1	8		T3	496		T4	2
valid_sources[0x48]	260326	1			T1	5		T3	494		T4	1
valid_sources[0x49]	276664	1			T1	10		T3	488		T9	701
valid_sources[0x4a]	274612	1			T1	18		T3	539		T4	9
valid_sources[0x4b]	278180	1			T1	13		T3	465		T4	1
valid_sources[0x4c]	285118	1			T1	6		T3	477		T9	723
valid_sources[0x4d]	258749	1			T1	6		T3	461		T4	5
valid_sources[0x4e]	261899	1			T1	7		T3	462		T9	699
valid_sources[0x4f]	282779	1			T1	14		T3	455		T4	4
valid_sources[0x50]	360333	1			T1	5		T3	435		T4	2
valid_sources[0x51]	309897	1			T1	8		T3	523		T4	2
valid_sources[0x52]	306694	1			T1	5		T3	460		T4	1
valid_sources[0x53]	254430	1			T1	12		T3	472		T4	4
valid_sources[0x54]	259664	1			T1	5		T3	492		T4	1
valid_sources[0x55]	285794	1			T1	8		T3	549		T9	702
valid_sources[0x56]	309076	1			T1	13		T3	488		T4	3
valid_sources[0x57]	347475	1			T1	15		T3	516		T4	2
valid_sources[0x58]	285675	1			T1	3		T3	420		T4	2
valid_sources[0x59]	315021	1			T1	13		T3	522		T4	1
valid_sources[0x5a]	269768	1			T1	9		T3	510		T4	4
valid_sources[0x5b]	288398	1			T1	7		T3	543		T9	697
valid_sources[0x5c]	247609	1			T1	8		T3	493		T4	1
valid_sources[0x5d]	287887	1			T1	6		T3	533		T4	7
valid_sources[0x5e]	255463	1			T1	9		T3	476		T4	4
valid_sources[0x5f]	292547	1			T1	2		T3	401		T4	8
valid_sources[0x60]	283749	1			T1	15		T3	472		T9	666
valid_sources[0x61]	270037	1			T1	1		T3	503		T4	2
valid_sources[0x62]	313150	1			T1	10		T3	508		T4	4
valid_sources[0x63]	253735	1			T1	10		T3	471		T4	1
valid_sources[0x64]	272499	1			T1	10		T3	573		T4	1
valid_sources[0x65]	302960	1			T1	6		T3	442		T4	3
valid_sources[0x66]	255220	1			T1	3		T3	417		T4	8
valid_sources[0x67]	269028	1			T1	6		T3	518		T4	1
valid_sources[0x68]	292325	1			T1	9		T3	487		T4	5
valid_sources[0x69]	294393	1			T1	8		T3	527		T4	1
valid_sources[0x6a]	247796	1			T1	8		T3	448		T4	1
valid_sources[0x6b]	301274	1			T1	11		T3	497		T4	6
valid_sources[0x6c]	257716	1			T1	10		T3	433		T4	3
valid_sources[0x6d]	363316	1			T1	10		T3	503		T4	5
valid_sources[0x6e]	324374	1			T1	9		T3	515		T4	5
valid_sources[0x6f]	262441	1			T1	16		T3	475		T4	8
valid_sources[0x70]	301452	1			T1	9		T3	465		T4	2
valid_sources[0x71]	253664	1			T1	8		T3	514		T9	721
valid_sources[0x72]	329047	1			T1	6		T3	496		T4	2
valid_sources[0x73]	338200	1			T1	5		T3	522		T4	3
valid_sources[0x74]	292322	1			T1	6		T3	497		T4	1
valid_sources[0x75]	278586	1			T1	11		T3	471		T4	3
valid_sources[0x76]	271092	1			T1	9		T3	532		T4	5
valid_sources[0x77]	380385	1			T1	8		T3	472		T4	3
valid_sources[0x78]	248483	1			T1	8		T3	492		T4	1
valid_sources[0x79]	261427	1			T1	4		T3	548		T4	3
valid_sources[0x7a]	284355	1			T1	9		T3	447		T4	7
valid_sources[0x7b]	253912	1			T1	12		T3	456		T4	2
valid_sources[0x7c]	282377	1			T1	8		T3	459		T4	2
valid_sources[0x7d]	262916	1			T1	7		T3	498		T4	5
valid_sources[0x7e]	260004	1			T1	11		T3	438		T4	7
valid_sources[0x7f]	302304	1			T1	4		T3	472		T4	2
valid_sources[0x80]	241912	1			T1	7		T3	507		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29748541

1

T1

5

T3

56656

T4

6

values[0x0]

all_enables

biggest_size

14981829

1

T1

53

T3

27949

T4

31

values[0x1]

all_enables

biggest_size

14977594

1

T1

55

T3

28081

T4

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

128355

1

T3

20

T9

23

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47910	1			T3	14		T9	17		T17	476
values[0x0]	55764	1			T3	22		T9	27		T5	10
values[0x1]	59149	1			T1	1		T2	1		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136183

1

T3

27

T9

34

T10

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	740	1			T6	1		T63	4		T31	15
valid_sources[0x01]	592	1			T17	7		T26	58		T6	2
valid_sources[0x02]	646	1			T17	1		T26	10		T7	3
valid_sources[0x03]	650	1			T13	1		T31	13		T52	39
valid_sources[0x04]	673	1			T3	1		T129	1		T31	10
valid_sources[0x05]	658	1			T26	1		T31	11		T52	33
valid_sources[0x06]	863	1			T13	1		T17	3		T130	1
valid_sources[0x07]	547	1			T3	1		T26	21		T31	10
valid_sources[0x08]	785	1			T31	11		T52	20		T27	1
valid_sources[0x09]	529	1			T17	2		T26	9		T6	5
valid_sources[0x0a]	929	1			T46	1		T18	1		T31	7
valid_sources[0x0b]	538	1			T6	1		T62	1		T31	6
valid_sources[0x0c]	530	1			T17	2		T62	9		T31	13
valid_sources[0x0d]	929	1			T26	2		T31	15		T52	27
valid_sources[0x0e]	689	1			T3	1		T31	12		T52	36
valid_sources[0x0f]	548	1			T26	12		T31	12		T52	34
valid_sources[0x10]	682	1			T17	164		T31	12		T52	23
valid_sources[0x11]	837	1			T26	42		T31	12		T52	26
valid_sources[0x12]	743	1			T131	3		T31	6		T52	39
valid_sources[0x13]	565	1			T26	5		T8	45		T31	17
valid_sources[0x14]	448	1			T130	1		T31	19		T52	29
valid_sources[0x15]	420	1			T17	1		T26	2		T78	3
valid_sources[0x16]	623	1			T3	1		T17	10		T26	2
valid_sources[0x17]	720	1			T17	2		T78	1		T21	1
valid_sources[0x18]	586	1			T26	3		T31	11		T52	46
valid_sources[0x19]	661	1			T11	1		T130	1		T31	9
valid_sources[0x1a]	789	1			T31	10		T52	39		T64	2
valid_sources[0x1b]	562	1			T31	17		T52	48		T27	1
valid_sources[0x1c]	469	1			T13	1		T26	1		T20	1
valid_sources[0x1d]	500	1			T31	12		T52	46		T132	1
valid_sources[0x1e]	757	1			T26	47		T31	26		T52	31
valid_sources[0x1f]	489	1			T17	2		T6	3		T31	12
valid_sources[0x20]	798	1			T3	2		T130	1		T31	10
valid_sources[0x21]	542	1			T26	1		T130	2		T31	11
valid_sources[0x22]	540	1			T3	1		T31	16		T52	47
valid_sources[0x23]	504	1			T11	1		T18	2		T60	1
valid_sources[0x24]	526	1			T17	3		T26	1		T6	1
valid_sources[0x25]	510	1			T26	2		T31	18		T52	33
valid_sources[0x26]	732	1			T26	2		T6	3		T31	14
valid_sources[0x27]	752	1			T3	2		T26	7		T6	2
valid_sources[0x28]	565	1			T26	7		T63	15		T31	13
valid_sources[0x29]	515	1			T31	11		T52	55		T27	1
valid_sources[0x2a]	601	1			T11	1		T21	4		T31	16
valid_sources[0x2b]	1003	1			T17	1		T60	1		T26	16
valid_sources[0x2c]	765	1			T18	1		T31	12		T52	27
valid_sources[0x2d]	704	1			T26	13		T31	20		T52	40
valid_sources[0x2e]	582	1			T18	2		T31	14		T52	38
valid_sources[0x2f]	623	1			T57	1		T18	1		T31	21
valid_sources[0x30]	654	1			T17	24		T31	7		T52	25
valid_sources[0x31]	660	1			T17	177		T6	2		T31	14
valid_sources[0x32]	876	1			T17	1		T31	13		T52	38
valid_sources[0x33]	585	1			T26	3		T7	1		T31	14
valid_sources[0x34]	644	1			T17	79		T31	8		T52	27
valid_sources[0x35]	531	1			T31	6		T52	29		T54	15
valid_sources[0x36]	627	1			T17	10		T26	2		T130	1
valid_sources[0x37]	510	1			T3	1		T31	6		T52	28
valid_sources[0x38]	1056	1			T17	143		T31	9		T52	30
valid_sources[0x39]	844	1			T26	4		T63	4		T31	11
valid_sources[0x3a]	666	1			T131	3		T31	15		T52	40
valid_sources[0x3b]	579	1			T31	8		T52	28		T27	1
valid_sources[0x3c]	633	1			T31	9		T52	45		T27	1
valid_sources[0x3d]	495	1			T3	2		T10	2		T17	1
valid_sources[0x3e]	480	1			T130	1		T31	13		T52	38
valid_sources[0x3f]	553	1			T31	7		T52	23		T27	2
valid_sources[0x40]	449	1			T31	9		T52	36		T27	1
valid_sources[0x41]	660	1			T3	2		T30	1		T17	3
valid_sources[0x42]	757	1			T11	1		T46	1		T31	16
valid_sources[0x43]	638	1			T31	13		T52	38		T126	1
valid_sources[0x44]	614	1			T63	3		T31	7		T52	33
valid_sources[0x45]	509	1			T26	10		T78	2		T31	10
valid_sources[0x46]	418	1			T13	1		T26	3		T63	7
valid_sources[0x47]	501	1			T31	7		T52	27		T27	1
valid_sources[0x48]	511	1			T17	20		T18	1		T26	1
valid_sources[0x49]	645	1			T17	126		T31	12		T52	38
valid_sources[0x4a]	619	1			T96	2		T60	2		T26	24
valid_sources[0x4b]	895	1			T26	1		T31	12		T52	33
valid_sources[0x4c]	733	1			T9	24		T17	1		T7	1
valid_sources[0x4d]	584	1			T17	2		T26	2		T31	9
valid_sources[0x4e]	574	1			T63	3		T31	13		T52	32
valid_sources[0x4f]	478	1			T3	1		T26	6		T31	15
valid_sources[0x50]	746	1			T17	163		T130	1		T131	2
valid_sources[0x51]	475	1			T26	1		T31	18		T52	30
valid_sources[0x52]	668	1			T31	8		T52	23		T27	2
valid_sources[0x53]	633	1			T31	15		T52	44		T27	1
valid_sources[0x54]	877	1			T26	11		T31	4		T52	25
valid_sources[0x55]	736	1			T3	1		T31	12		T52	27
valid_sources[0x56]	789	1			T3	3		T31	9		T52	26
valid_sources[0x57]	608	1			T31	7		T52	30		T27	1
valid_sources[0x58]	657	1			T3	1		T63	5		T31	15
valid_sources[0x59]	994	1			T17	1		T31	10		T52	35
valid_sources[0x5a]	637	1			T13	1		T131	2		T31	10
valid_sources[0x5b]	849	1			T17	132		T26	8		T63	7
valid_sources[0x5c]	670	1			T17	4		T26	31		T31	9
valid_sources[0x5d]	543	1			T26	5		T31	16		T52	34
valid_sources[0x5e]	467	1			T17	6		T31	15		T52	25
valid_sources[0x5f]	803	1			T3	1		T11	1		T13	2
valid_sources[0x60]	541	1			T31	16		T52	38		T27	1
valid_sources[0x61]	984	1			T13	1		T133	2		T31	15
valid_sources[0x62]	597	1			T3	3		T17	4		T6	3
valid_sources[0x63]	484	1			T3	1		T26	1		T7	2
valid_sources[0x64]	512	1			T26	6		T130	1		T31	17
valid_sources[0x65]	818	1			T26	5		T31	14		T52	33
valid_sources[0x66]	710	1			T20	1		T31	10		T52	28
valid_sources[0x67]	632	1			T13	1		T6	1		T31	14
valid_sources[0x68]	459	1			T17	5		T31	10		T52	23
valid_sources[0x69]	735	1			T17	285		T26	9		T131	4
valid_sources[0x6a]	633	1			T9	19		T17	1		T26	1
valid_sources[0x6b]	496	1			T3	1		T26	17		T31	3
valid_sources[0x6c]	852	1			T31	14		T52	26		T64	4
valid_sources[0x6d]	676	1			T17	5		T134	1		T31	8
valid_sources[0x6e]	547	1			T18	1		T130	1		T31	9
valid_sources[0x6f]	599	1			T17	26		T26	6		T135	2
valid_sources[0x70]	671	1			T17	15		T18	1		T26	5
valid_sources[0x71]	846	1			T17	10		T6	3		T31	11
valid_sources[0x72]	551	1			T7	2		T31	12		T52	30
valid_sources[0x73]	497	1			T13	1		T26	13		T31	16
valid_sources[0x74]	663	1			T17	2		T26	14		T63	4
valid_sources[0x75]	501	1			T26	2		T31	19		T52	44
valid_sources[0x76]	716	1			T1	1		T3	1		T31	17
valid_sources[0x77]	555	1			T31	9		T52	38		T126	1
valid_sources[0x78]	655	1			T6	1		T31	9		T52	52
valid_sources[0x79]	799	1			T3	3		T17	88		T6	2
valid_sources[0x7a]	780	1			T17	3		T61	1		T31	13
valid_sources[0x7b]	524	1			T3	1		T26	2		T31	11
valid_sources[0x7c]	612	1			T62	6		T20	1		T31	10
valid_sources[0x7d]	508	1			T26	1		T131	1		T31	11
valid_sources[0x7e]	736	1			T26	10		T31	9		T52	28
valid_sources[0x7f]	498	1			T31	11		T52	35		T27	2
valid_sources[0x80]	734	1			T17	3		T18	2		T26	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35739

1

T3

5

T9

9

T17

435

values[0x0]

all_enables

biggest_size

47516

1

T3

10

T9

8

T5

1

values[0x1]

all_enables

biggest_size

45100

1

T3

5

T9

6

T11

1