Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13515589

1

T1

1915

T3

9067

T4

903

full_word

54684859

1

T1

113

T3

90178

T4

63

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68200148	1			T1	2028		T3	99245		T4	966
auto[TlIntgErrCmd]	99	1			T97	7		T98	6		T99	2
auto[TlIntgErrData]	101	1			T97	6		T98	2		T99	5
auto[TlIntgErrBoth]	100	1			T97	7		T98	2		T99	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31263032

1

T1

879

T3

37561

T4

366

auto[1]

36937416

1

T1

1149

T3

61684

T4

600

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6457129	1			T1	874		T3	3413		T4	360
auto[TlIntgErrNone]	partial	auto[1]	7058180	1			T1	1041		T3	5654		T4	543
auto[TlIntgErrNone]	full_word	auto[0]	24805783	1			T1	5		T3	34148		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	29879056	1			T1	108		T3	56030		T4	57
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T97	4		T98	3		T99	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T97	3		T98	3		T99	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T115	1		T117	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T97	2		T98	2		T99	3
auto[TlIntgErrData]	partial	auto[1]	55	1			T97	4		T99	2		T113	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T111	1		T118	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T113	1		T119	1		T120	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T97	2		T99	2		T114	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T97	4		T98	1		T113	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T99	1		T116	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T97	1		T98	1		T110	1