Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	617716	1			T13	10326		T14	108		T15	11762
auto[1]	10329821	1			T1	122		T3	3559		T4	318
auto[2]	519119	1			T13	9374		T14	78		T15	10596
auto[3]	10249207	1			T1	151		T3	3457		T4	531

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14467331	1			T1	1		T3	5786		T4	2
auto[1]	2047919	1			T1	3		T3	562		T4	57
auto[2]	2040020	1			T1	18		T3	613		T4	86
auto[3]	3160593	1			T1	251		T3	55		T4	704

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8559108

1

T1

272

T3

7009

T4

849

auto[1]

13156755

1

T1

1

T3

7

T9

13

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	215483	1			T13	8550		T8	18		T126	9030
auto[0]	auto[0]	auto[1]	22647	1			T13	804		T61	2		T8	2
auto[0]	auto[0]	auto[2]	22486	1			T13	887		T61	4		T8	2
auto[0]	auto[0]	auto[3]	9729	1			T13	75		T14	107		T61	231
auto[0]	auto[1]	auto[0]	3280158	1			T3	2933		T9	5143		T10	4990
auto[0]	auto[1]	auto[1]	345426	1			T3	273		T4	2		T9	485
auto[0]	auto[1]	auto[2]	335685	1			T1	4		T3	323		T4	34
auto[0]	auto[1]	auto[3]	75274	1			T1	118		T3	26		T4	282
auto[0]	auto[2]	auto[0]	191109	1			T13	7941		T8	15		T126	8235
auto[0]	auto[2]	auto[1]	20150	1			T13	775		T14	2		T61	14
auto[0]	auto[2]	auto[2]	18030	1			T13	582		T8	1		T126	776
auto[0]	auto[2]	auto[3]	7236	1			T13	65		T14	76		T61	152
auto[0]	auto[3]	auto[0]	3262339	1			T1	1		T3	2850		T4	2
auto[0]	auto[3]	auto[1]	332235	1			T1	3		T3	287		T4	55
auto[0]	auto[3]	auto[2]	343592	1			T1	14		T3	288		T4	52
auto[0]	auto[3]	auto[3]	77529	1			T1	132		T3	29		T4	422
auto[1]	auto[0]	auto[0]	11759	1			T13	8		T15	397		T126	6
auto[1]	auto[0]	auto[1]	51869	1			T13	2		T15	1746		T125	3586
auto[1]	auto[0]	auto[2]	51934	1			T15	1754		T126	1		T125	3661
auto[1]	auto[0]	auto[3]	231809	1			T14	1		T15	7865		T61	1
auto[1]	auto[1]	auto[0]	3747886	1			T3	2		T9	7		T10	6
auto[1]	auto[1]	auto[1]	636133	1			T3	2		T9	1		T5	1
auto[1]	auto[1]	auto[2]	601123	1			T5	1		T75	6996		T51	805
auto[1]	auto[1]	auto[3]	1308136	1			T14	1		T29	1		T75	606
auto[1]	auto[2]	auto[0]	9979	1			T13	9		T15	213		T126	5
auto[1]	auto[2]	auto[1]	43617	1			T15	1070		T126	1		T125	3289
auto[1]	auto[2]	auto[2]	41808	1			T13	2		T15	1685		T125	2419
auto[1]	auto[2]	auto[3]	187190	1			T15	7628		T125	10890		T127	12036
auto[1]	auto[3]	auto[0]	3748618	1			T3	1		T9	5		T10	2
auto[1]	auto[3]	auto[1]	595842	1			T5	3		T11	4		T75	7020
auto[1]	auto[3]	auto[2]	625362	1			T3	2		T12	2		T13	1
auto[1]	auto[3]	auto[3]	1263690	1			T1	1		T5	2		T11	1