Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	302930770	123627	0	0
ctrl_regwen_rd_A	302930770	6150	0	0
exec_rd_A	302930770	5777	0	0
exec_regwen_rd_A	302930770	6236	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302930770	123627	0	0
T15	140151	0	0	0
T17	108100	2517	0	0
T18	365866	0	0	0
T26	36499	1369	0	0
T31	0	3163	0	0
T33	2912	0	0	0
T38	0	1937	0	0
T47	0	3633	0	0
T52	0	9072	0	0
T53	0	640	0	0
T54	0	3817	0	0
T55	0	3060	0	0
T56	0	7074	0	0
T57	36377	0	0	0
T58	211069	0	0	0
T59	4345	0	0	0
T60	486980	0	0	0
T61	18272	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302930770	6150	0	0
T15	140151	0	0	0
T17	108100	271	0	0
T18	365866	0	0	0
T26	36499	0	0	0
T33	2912	0	0	0
T38	0	345	0	0
T57	36377	0	0	0
T58	211069	0	0	0
T59	4345	0	0	0
T60	486980	0	0	0
T61	18272	0	0	0
T100	0	234	0	0
T101	0	562	0	0
T102	0	167	0	0
T103	0	329	0	0
T104	0	279	0	0
T105	0	175	0	0
T106	0	772	0	0
T107	0	195	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302930770	5777	0	0
T15	140151	0	0	0
T17	108100	157	0	0
T18	365866	0	0	0
T26	36499	0	0	0
T33	2912	0	0	0
T38	0	296	0	0
T57	36377	0	0	0
T58	211069	0	0	0
T59	4345	0	0	0
T60	486980	0	0	0
T61	18272	0	0	0
T100	0	247	0	0
T101	0	610	0	0
T102	0	229	0	0
T103	0	242	0	0
T104	0	256	0	0
T105	0	106	0	0
T106	0	644	0	0
T107	0	139	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302930770	6236	0	0
T15	140151	0	0	0
T17	108100	243	0	0
T18	365866	0	0	0
T26	36499	0	0	0
T33	2912	0	0	0
T38	0	295	0	0
T57	36377	0	0	0
T58	211069	0	0	0
T59	4345	0	0	0
T60	486980	0	0	0
T61	18272	0	0	0
T100	0	273	0	0
T101	0	638	0	0
T102	0	203	0	0
T103	0	295	0	0
T104	0	304	0	0
T105	0	152	0	0
T106	0	686	0	0
T107	0	158	0	0