Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15337984	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60768862

1

T1

50126

T2

140944

T3

81643

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37952005	1			T1	27820		T2	77267		T3	45233
values[0x0]	17542547	1			T1	13244		T2	37533		T3	21492
values[0x1]	20612294	1			T1	14123		T2	40178		T3	23160

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7642566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68464280

1

T1

52610

T2

148128

T3

85745

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	258152	1			T1	186		T2	603		T3	319
valid_sources[0x01]	268768	1			T1	257		T2	577		T3	361
valid_sources[0x02]	272882	1			T1	212		T2	614		T3	467
valid_sources[0x03]	279522	1			T1	148		T2	644		T3	261
valid_sources[0x04]	267512	1			T1	176		T2	602		T3	433
valid_sources[0x05]	339302	1			T1	227		T2	599		T3	464
valid_sources[0x06]	277023	1			T1	168		T2	633		T3	382
valid_sources[0x07]	296282	1			T1	168		T2	594		T3	324
valid_sources[0x08]	288368	1			T1	156		T2	599		T3	386
valid_sources[0x09]	283678	1			T1	188		T2	621		T3	294
valid_sources[0x0a]	271070	1			T1	198		T2	596		T3	403
valid_sources[0x0b]	255215	1			T1	197		T2	567		T3	404
valid_sources[0x0c]	259165	1			T1	250		T2	612		T3	341
valid_sources[0x0d]	296002	1			T1	190		T2	612		T3	322
valid_sources[0x0e]	279575	1			T1	185		T2	605		T3	300
valid_sources[0x0f]	292391	1			T1	182		T2	611		T3	333
valid_sources[0x10]	317688	1			T1	209		T2	618		T3	339
valid_sources[0x11]	292121	1			T1	217		T2	659		T3	454
valid_sources[0x12]	298520	1			T1	220		T2	605		T3	473
valid_sources[0x13]	300779	1			T1	163		T2	641		T3	387
valid_sources[0x14]	251053	1			T1	147		T2	629		T3	239
valid_sources[0x15]	271215	1			T1	205		T2	602		T3	302
valid_sources[0x16]	288593	1			T1	184		T2	572		T3	327
valid_sources[0x17]	336198	1			T1	303		T2	599		T3	346
valid_sources[0x18]	292226	1			T1	166		T2	559		T3	398
valid_sources[0x19]	293577	1			T1	311		T2	685		T3	291
valid_sources[0x1a]	278572	1			T1	254		T2	629		T3	306
valid_sources[0x1b]	276147	1			T1	267		T2	571		T3	183
valid_sources[0x1c]	340208	1			T1	211		T2	561		T3	444
valid_sources[0x1d]	285757	1			T1	182		T2	579		T3	549
valid_sources[0x1e]	324651	1			T1	199		T2	627		T3	265
valid_sources[0x1f]	257551	1			T1	140		T2	602		T3	261
valid_sources[0x20]	279399	1			T1	247		T2	583		T3	473
valid_sources[0x21]	282404	1			T1	272		T2	611		T3	267
valid_sources[0x22]	269065	1			T1	227		T2	606		T3	309
valid_sources[0x23]	281533	1			T1	161		T2	623		T3	286
valid_sources[0x24]	284033	1			T1	317		T2	616		T3	263
valid_sources[0x25]	297623	1			T1	213		T2	642		T3	248
valid_sources[0x26]	388846	1			T1	184		T2	605		T3	266
valid_sources[0x27]	329129	1			T1	274		T2	599		T3	386
valid_sources[0x28]	263546	1			T1	267		T2	594		T3	387
valid_sources[0x29]	294218	1			T1	190		T2	611		T3	308
valid_sources[0x2a]	267529	1			T1	255		T2	593		T3	394
valid_sources[0x2b]	293227	1			T1	259		T2	613		T3	281
valid_sources[0x2c]	255284	1			T1	277		T2	570		T3	302
valid_sources[0x2d]	268408	1			T1	197		T2	611		T3	347
valid_sources[0x2e]	333197	1			T1	203		T2	611		T3	294
valid_sources[0x2f]	303264	1			T1	179		T2	568		T3	432
valid_sources[0x30]	263784	1			T1	197		T2	660		T3	328
valid_sources[0x31]	354253	1			T1	159		T2	574		T3	352
valid_sources[0x32]	255859	1			T1	206		T2	615		T3	502
valid_sources[0x33]	308783	1			T1	291		T2	592		T3	392
valid_sources[0x34]	365820	1			T1	161		T2	592		T3	452
valid_sources[0x35]	315280	1			T1	252		T2	597		T3	256
valid_sources[0x36]	293418	1			T1	322		T2	589		T3	317
valid_sources[0x37]	277981	1			T1	231		T2	619		T3	406
valid_sources[0x38]	250936	1			T1	132		T2	551		T3	341
valid_sources[0x39]	343987	1			T1	193		T2	634		T3	303
valid_sources[0x3a]	326424	1			T1	213		T2	617		T3	294
valid_sources[0x3b]	355226	1			T1	243		T2	583		T3	397
valid_sources[0x3c]	269607	1			T1	199		T2	637		T3	314
valid_sources[0x3d]	276116	1			T1	307		T2	616		T3	511
valid_sources[0x3e]	338631	1			T1	191		T2	611		T3	259
valid_sources[0x3f]	315782	1			T1	270		T2	566		T3	210
valid_sources[0x40]	277215	1			T1	187		T2	621		T3	399
valid_sources[0x41]	297675	1			T1	163		T2	598		T3	384
valid_sources[0x42]	263720	1			T1	162		T2	577		T3	408
valid_sources[0x43]	293389	1			T1	247		T2	595		T3	311
valid_sources[0x44]	275420	1			T1	140		T2	608		T3	285
valid_sources[0x45]	327770	1			T1	168		T2	609		T3	348
valid_sources[0x46]	337632	1			T1	172		T2	553		T3	448
valid_sources[0x47]	322499	1			T1	222		T2	594		T3	301
valid_sources[0x48]	284891	1			T1	203		T2	584		T3	466
valid_sources[0x49]	292379	1			T1	214		T2	596		T3	392
valid_sources[0x4a]	270843	1			T1	208		T2	639		T3	273
valid_sources[0x4b]	303640	1			T1	226		T2	610		T3	532
valid_sources[0x4c]	292829	1			T1	276		T2	627		T3	428
valid_sources[0x4d]	265942	1			T1	200		T2	625		T3	479
valid_sources[0x4e]	289704	1			T1	194		T2	554		T3	219
valid_sources[0x4f]	300798	1			T1	173		T2	622		T3	339
valid_sources[0x50]	271211	1			T1	229		T2	573		T3	443
valid_sources[0x51]	307110	1			T1	186		T2	581		T3	413
valid_sources[0x52]	261721	1			T1	293		T2	650		T3	485
valid_sources[0x53]	310570	1			T1	86		T2	612		T3	410
valid_sources[0x54]	373886	1			T1	208		T2	575		T3	266
valid_sources[0x55]	287497	1			T1	270		T2	594		T3	257
valid_sources[0x56]	308787	1			T1	242		T2	611		T3	294
valid_sources[0x57]	332397	1			T1	140		T2	625		T3	382
valid_sources[0x58]	258114	1			T1	135		T2	624		T3	496
valid_sources[0x59]	323073	1			T1	142		T2	580		T3	326
valid_sources[0x5a]	280762	1			T1	225		T2	612		T3	261
valid_sources[0x5b]	261510	1			T1	199		T2	623		T3	205
valid_sources[0x5c]	343555	1			T1	220		T2	557		T3	432
valid_sources[0x5d]	256622	1			T1	186		T2	656		T3	216
valid_sources[0x5e]	355149	1			T1	155		T2	658		T3	428
valid_sources[0x5f]	293258	1			T1	296		T2	608		T3	352
valid_sources[0x60]	284264	1			T1	162		T2	596		T3	339
valid_sources[0x61]	331470	1			T1	202		T2	611		T3	312
valid_sources[0x62]	294143	1			T1	310		T2	609		T3	463
valid_sources[0x63]	262657	1			T1	266		T2	630		T3	290
valid_sources[0x64]	289869	1			T1	147		T2	598		T3	375
valid_sources[0x65]	283905	1			T1	233		T2	578		T3	343
valid_sources[0x66]	309354	1			T1	138		T2	594		T3	400
valid_sources[0x67]	254377	1			T1	222		T2	605		T3	275
valid_sources[0x68]	383410	1			T1	260		T2	596		T3	418
valid_sources[0x69]	271714	1			T1	232		T2	627		T3	391
valid_sources[0x6a]	287357	1			T1	193		T2	591		T3	493
valid_sources[0x6b]	349759	1			T1	269		T2	585		T3	365
valid_sources[0x6c]	285445	1			T1	258		T2	599		T3	409
valid_sources[0x6d]	251310	1			T1	210		T2	629		T3	286
valid_sources[0x6e]	289116	1			T1	175		T2	600		T3	218
valid_sources[0x6f]	314432	1			T1	160		T2	583		T3	237
valid_sources[0x70]	292716	1			T1	189		T2	620		T3	270
valid_sources[0x71]	260738	1			T1	246		T2	614		T3	223
valid_sources[0x72]	258361	1			T1	216		T2	608		T3	348
valid_sources[0x73]	299625	1			T1	192		T2	582		T3	379
valid_sources[0x74]	404426	1			T1	250		T2	586		T3	236
valid_sources[0x75]	323684	1			T1	225		T2	582		T3	353
valid_sources[0x76]	270867	1			T1	145		T2	654		T3	434
valid_sources[0x77]	267585	1			T1	131		T2	587		T3	376
valid_sources[0x78]	301388	1			T1	186		T2	609		T3	402
valid_sources[0x79]	267594	1			T1	280		T2	593		T3	351
valid_sources[0x7a]	327438	1			T1	259		T2	615		T3	317
valid_sources[0x7b]	315203	1			T1	253		T2	635		T3	412
valid_sources[0x7c]	293793	1			T1	149		T2	617		T3	404
valid_sources[0x7d]	283795	1			T1	227		T2	574		T3	553
valid_sources[0x7e]	338928	1			T1	231		T2	572		T3	288
valid_sources[0x7f]	264012	1			T1	260		T2	561		T3	371
valid_sources[0x80]	277427	1			T1	201		T2	616		T3	499

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30289908

1

T1

25252

T2

70240

T3

41114

values[0x0]

all_enables

biggest_size

15238663

1

T1

12437

T2

35388

T3

20276

values[0x1]

all_enables

biggest_size

15240291

1

T1

12437

T2

35316

T3

20253

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113020

1

T1

2

T2

9

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42780	1			T11	7		T12	502		T14	746
values[0x0]	49598	1			T1	4		T2	17		T3	3
values[0x1]	52807	1			T1	1		T2	13		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

120256

1

T1

2

T2

11

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	471	1			T9	1		T12	12		T39	2
valid_sources[0x01]	606	1			T2	1		T11	1		T12	7
valid_sources[0x02]	465	1			T12	1		T5	1		T40	5
valid_sources[0x03]	521	1			T1	1		T12	4		T14	6
valid_sources[0x04]	594	1			T12	5		T39	1		T106	4
valid_sources[0x05]	536	1			T4	2		T12	4		T5	3
valid_sources[0x06]	512	1			T12	6		T71	1		T130	2
valid_sources[0x07]	531	1			T12	12		T131	2		T24	10
valid_sources[0x08]	485	1			T12	10		T5	2		T48	4
valid_sources[0x09]	661	1			T12	6		T14	136		T50	3
valid_sources[0x0a]	740	1			T12	6		T5	3		T47	10
valid_sources[0x0b]	501	1			T12	8		T24	3		T40	1
valid_sources[0x0c]	454	1			T9	1		T11	1		T12	7
valid_sources[0x0d]	466	1			T1	4		T12	2		T132	1
valid_sources[0x0e]	506	1			T12	10		T39	5		T24	1
valid_sources[0x0f]	660	1			T10	2		T12	7		T16	1
valid_sources[0x10]	391	1			T12	1		T5	1		T48	2
valid_sources[0x11]	649	1			T10	1		T12	21		T39	1
valid_sources[0x12]	632	1			T12	8		T14	161		T25	1
valid_sources[0x13]	562	1			T4	1		T12	7		T39	1
valid_sources[0x14]	489	1			T4	3		T11	1		T12	11
valid_sources[0x15]	796	1			T12	11		T39	10		T133	1
valid_sources[0x16]	685	1			T5	3		T50	7		T130	2
valid_sources[0x17]	585	1			T12	18		T7	1		T129	1
valid_sources[0x18]	556	1			T11	2		T12	13		T5	2
valid_sources[0x19]	494	1			T12	12		T86	4		T105	1
valid_sources[0x1a]	592	1			T12	6		T134	1		T130	2
valid_sources[0x1b]	531	1			T12	2		T5	3		T39	3
valid_sources[0x1c]	502	1			T12	8		T14	3		T83	1
valid_sources[0x1d]	569	1			T12	10		T14	133		T5	1
valid_sources[0x1e]	486	1			T12	16		T7	1		T24	5
valid_sources[0x1f]	514	1			T12	10		T39	4		T135	1
valid_sources[0x20]	498	1			T10	2		T11	1		T12	4
valid_sources[0x21]	640	1			T12	4		T7	1		T72	2
valid_sources[0x22]	610	1			T10	1		T12	14		T5	3
valid_sources[0x23]	446	1			T4	2		T12	2		T104	1
valid_sources[0x24]	411	1			T9	1		T12	14		T5	2
valid_sources[0x25]	435	1			T12	2		T5	2		T7	1
valid_sources[0x26]	481	1			T11	1		T12	13		T108	1
valid_sources[0x27]	787	1			T12	8		T14	3		T39	1
valid_sources[0x28]	678	1			T10	2		T12	12		T15	1
valid_sources[0x29]	527	1			T12	5		T5	1		T136	1
valid_sources[0x2a]	427	1			T12	2		T14	1		T5	1
valid_sources[0x2b]	640	1			T12	3		T137	1		T106	1
valid_sources[0x2c]	560	1			T12	3		T50	1		T108	1
valid_sources[0x2d]	551	1			T9	1		T12	10		T5	1
valid_sources[0x2e]	564	1			T12	6		T5	1		T72	1
valid_sources[0x2f]	585	1			T2	3		T12	4		T5	2
valid_sources[0x30]	529	1			T12	7		T14	7		T5	1
valid_sources[0x31]	449	1			T12	1		T129	1		T138	1
valid_sources[0x32]	452	1			T12	7		T14	57		T7	1
valid_sources[0x33]	570	1			T4	1		T12	10		T14	53
valid_sources[0x34]	714	1			T12	4		T69	1		T7	1
valid_sources[0x35]	408	1			T12	8		T129	2		T50	1
valid_sources[0x36]	424	1			T12	5		T105	1		T130	2
valid_sources[0x37]	577	1			T2	2		T12	9		T5	1
valid_sources[0x38]	547	1			T11	7		T12	4		T91	3
valid_sources[0x39]	501	1			T12	13		T5	1		T132	1
valid_sources[0x3a]	573	1			T12	10		T5	2		T7	1
valid_sources[0x3b]	573	1			T12	6		T40	6		T41	2
valid_sources[0x3c]	600	1			T12	7		T14	1		T5	1
valid_sources[0x3d]	574	1			T12	5		T129	3		T139	1
valid_sources[0x3e]	551	1			T12	4		T14	132		T39	1
valid_sources[0x3f]	1095	1			T2	1		T12	4		T51	37
valid_sources[0x40]	592	1			T12	3		T14	189		T39	2
valid_sources[0x41]	500	1			T11	2		T12	1		T13	1
valid_sources[0x42]	505	1			T12	9		T129	2		T140	1
valid_sources[0x43]	488	1			T12	5		T40	6		T41	6
valid_sources[0x44]	1205	1			T12	20		T49	8		T24	128
valid_sources[0x45]	567	1			T12	6		T7	1		T141	1
valid_sources[0x46]	675	1			T12	5		T16	1		T46	1
valid_sources[0x47]	567	1			T12	6		T142	1		T140	3
valid_sources[0x48]	995	1			T12	6		T24	14		T143	1
valid_sources[0x49]	797	1			T10	2		T12	13		T140	1
valid_sources[0x4a]	540	1			T12	2		T144	1		T40	8
valid_sources[0x4b]	473	1			T12	5		T5	2		T39	1
valid_sources[0x4c]	581	1			T10	2		T12	2		T141	2
valid_sources[0x4d]	603	1			T2	1		T12	15		T24	1
valid_sources[0x4e]	485	1			T12	4		T5	5		T15	1
valid_sources[0x4f]	584	1			T9	2		T11	1		T12	15
valid_sources[0x50]	427	1			T12	9		T23	1		T39	1
valid_sources[0x51]	768	1			T5	1		T50	1		T72	1
valid_sources[0x52]	692	1			T11	5		T12	3		T7	1
valid_sources[0x53]	435	1			T12	7		T5	3		T39	2
valid_sources[0x54]	600	1			T12	10		T106	1		T40	3
valid_sources[0x55]	736	1			T12	17		T39	3		T7	2
valid_sources[0x56]	479	1			T12	12		T17	1		T129	2
valid_sources[0x57]	872	1			T12	4		T108	1		T130	1
valid_sources[0x58]	505	1			T12	13		T14	78		T130	2
valid_sources[0x59]	528	1			T12	12		T7	1		T137	1
valid_sources[0x5a]	654	1			T9	1		T12	4		T5	2
valid_sources[0x5b]	738	1			T10	3		T12	11		T132	2
valid_sources[0x5c]	406	1			T12	10		T129	1		T134	1
valid_sources[0x5d]	627	1			T12	9		T5	5		T49	12
valid_sources[0x5e]	468	1			T9	1		T12	8		T72	1
valid_sources[0x5f]	402	1			T4	1		T12	5		T39	1
valid_sources[0x60]	532	1			T2	1		T12	7		T5	3
valid_sources[0x61]	494	1			T12	8		T5	2		T24	1
valid_sources[0x62]	494	1			T12	5		T132	1		T145	1
valid_sources[0x63]	545	1			T129	1		T50	5		T146	11
valid_sources[0x64]	513	1			T12	12		T50	3		T53	1
valid_sources[0x65]	633	1			T9	1		T12	4		T5	2
valid_sources[0x66]	629	1			T12	10		T24	197		T22	1
valid_sources[0x67]	536	1			T12	7		T5	6		T39	1
valid_sources[0x68]	500	1			T9	1		T12	18		T147	1
valid_sources[0x69]	575	1			T2	1		T12	9		T14	3
valid_sources[0x6a]	855	1			T12	5		T5	1		T39	3
valid_sources[0x6b]	576	1			T12	11		T106	1		T130	1
valid_sources[0x6c]	670	1			T12	7		T39	2		T129	1
valid_sources[0x6d]	466	1			T12	2		T85	1		T129	1
valid_sources[0x6e]	557	1			T12	3		T7	1		T53	2
valid_sources[0x6f]	404	1			T4	2		T12	9		T14	3
valid_sources[0x70]	444	1			T12	2		T48	10		T146	1
valid_sources[0x71]	528	1			T12	3		T14	3		T40	3
valid_sources[0x72]	419	1			T12	18		T5	1		T72	1
valid_sources[0x73]	438	1			T12	10		T14	2		T40	6
valid_sources[0x74]	585	1			T9	1		T12	3		T24	15
valid_sources[0x75]	565	1			T9	2		T12	6		T137	1
valid_sources[0x76]	496	1			T12	6		T5	2		T24	1
valid_sources[0x77]	474	1			T12	5		T72	1		T145	1
valid_sources[0x78]	424	1			T9	1		T12	5		T16	3
valid_sources[0x79]	559	1			T2	3		T12	17		T14	90
valid_sources[0x7a]	638	1			T12	8		T39	1		T53	7
valid_sources[0x7b]	447	1			T12	12		T5	3		T50	1
valid_sources[0x7c]	545	1			T12	17		T14	6		T5	2
valid_sources[0x7d]	768	1			T12	6		T127	2		T137	1
valid_sources[0x7e]	467	1			T12	11		T130	2		T40	2
valid_sources[0x7f]	449	1			T12	3		T16	1		T24	4
valid_sources[0x80]	480	1			T12	4		T14	1		T141	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31483

1

T11

3

T12

462

T14

671

values[0x0]

all_enables

biggest_size

41642

1

T1

2

T2

6

T3

1

values[0x1]

all_enables

biggest_size

39895

1

T2

3

T4

1

T9

1