Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14953491

1

T1

5061

T2

14034

T3

8242

full_word

55388470

1

T1

50126

T2

140944

T3

81643

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70341691	1			T1	55187		T2	154978		T3	89885
auto[TlIntgErrCmd]	91	1			T93	3		T94	6		T95	7
auto[TlIntgErrData]	92	1			T93	3		T94	3		T95	8
auto[TlIntgErrBoth]	87	1			T93	4		T94	1		T95	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32151541

1

T1

27820

T2

77267

T3

45233

auto[1]

38190420

1

T1

27367

T2

77711

T3

44652

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7162878	1			T1	2568		T2	7027		T3	4119
auto[TlIntgErrNone]	partial	auto[1]	7790366	1			T1	2493		T2	7007		T3	4123
auto[TlIntgErrNone]	full_word	auto[0]	24988551	1			T1	25252		T2	70240		T3	41114
auto[TlIntgErrNone]	full_word	auto[1]	30399896	1			T1	24874		T2	70704		T3	40529
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T93	1		T94	4		T95	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T93	1		T95	3		T115	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T95	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T93	1		T94	2		T115	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T93	2		T94	2		T95	5
auto[TlIntgErrData]	partial	auto[1]	40	1			T93	1		T94	1		T95	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T113	2		T117	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T95	2		T120	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	24	1			T94	1		T95	2		T116	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T93	3		T95	3		T115	9
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T93	1		T112	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T122	1		-	-		-	-