Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	780931	1			T1	2695		T14	182		T6	7606
auto[1]	10753769	1			T1	640		T2	47260		T3	37931
auto[2]	651113	1			T1	2516		T14	105		T6	6972
auto[3]	10631186	1			T1	388		T2	47380		T3	37172

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14054144	1			T1	4793		T2	78216		T3	62490
auto[1]	2250881	1			T1	701		T2	7906		T3	6066
auto[2]	2242743	1			T1	662		T2	7732		T3	5989
auto[3]	4269231	1			T1	83		T2	786		T3	558

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8743734

1

T1

6232

T2

94560

T3

36

auto[1]

14073265

1

T1

7

T2

80

T3

75067

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	247825	1			T1	2222		T14	153		T6	6290
auto[0]	auto[0]	auto[1]	25700	1			T1	215		T14	10		T6	626
auto[0]	auto[0]	auto[2]	25769	1			T1	229		T14	19		T6	622
auto[0]	auto[0]	auto[3]	8309	1			T1	27		T6	56		T39	198
auto[0]	auto[1]	auto[0]	3348016	1			T1	343		T2	38954		T3	10
auto[0]	auto[1]	auto[1]	351173	1			T1	251		T2	4029		T3	5
auto[0]	auto[1]	auto[2]	337139	1			T1	20		T2	3861		T3	1
auto[0]	auto[1]	auto[3]	67929	1			T1	23		T2	375		T4	287
auto[0]	auto[2]	auto[0]	214871	1			T1	2075		T14	78		T6	5897
auto[0]	auto[2]	auto[1]	22062	1			T1	219		T14	11		T6	600
auto[0]	auto[2]	auto[2]	21073	1			T1	204		T14	15		T6	435
auto[0]	auto[2]	auto[3]	6356	1			T1	16		T14	1		T6	32
auto[0]	auto[3]	auto[0]	3316514	1			T1	147		T2	39199		T3	14
auto[0]	auto[3]	auto[1]	333115	1			T1	15		T2	3866		T3	2
auto[0]	auto[3]	auto[2]	347067	1			T1	209		T2	3865		T3	2
auto[0]	auto[3]	auto[3]	70816	1			T1	17		T2	411		T3	2
auto[1]	auto[0]	auto[0]	15920	1			T1	2		T6	11		T39	21
auto[1]	auto[0]	auto[1]	70457	1			T6	1		T39	1		T125	1
auto[1]	auto[0]	auto[2]	70479	1			T86	2042		T105	4508		T107	1552
auto[1]	auto[0]	auto[3]	316472	1			T126	1		T86	9131		T105	20432
auto[1]	auto[1]	auto[0]	3451263	1			T1	2		T2	33		T3	31587
auto[1]	auto[1]	auto[1]	720684	1			T1	1		T2	5		T3	2900
auto[1]	auto[1]	auto[2]	676082	1			T2	3		T3	3151		T4	1
auto[1]	auto[1]	auto[3]	1801483	1			T3	277		T127	3		T83	313
auto[1]	auto[2]	auto[0]	13765	1			T1	2		T6	7		T39	17
auto[1]	auto[2]	auto[1]	60627	1			T39	1		T125	1		T86	1209
auto[1]	auto[2]	auto[2]	56855	1			T6	1		T39	2		T126	1
auto[1]	auto[2]	auto[3]	255504	1			T86	8847		T105	13717		T107	6906
auto[1]	auto[3]	auto[0]	3445970	1			T2	30		T3	30879		T4	31
auto[1]	auto[3]	auto[1]	667063	1			T2	6		T3	3159		T4	6
auto[1]	auto[3]	auto[2]	708279	1			T2	3		T3	2835		T4	1
auto[1]	auto[3]	auto[3]	1742362	1			T3	279		T13	1		T127	9