Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13599076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56553680

1

T1

140645

T2

55

T3

187695

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34963902	1			T1	77375		T2	366		T3	103316
values[0x0]	16234015	1			T1	37373		T2	188		T3	49745
values[0x1]	18954839	1			T1	40014		T2	415		T3	53375

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6773491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63379265

1

T1

147769

T2

453

T3

197179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	237709	1			T1	624		T2	1		T3	811
valid_sources[0x01]	326665	1			T1	607		T2	5		T3	825
valid_sources[0x02]	242464	1			T1	582		T2	3		T3	785
valid_sources[0x03]	248542	1			T1	652		T2	8		T3	794
valid_sources[0x04]	225327	1			T1	622		T3	805		T10	395
valid_sources[0x05]	238540	1			T1	572		T2	10		T3	797
valid_sources[0x06]	272920	1			T1	610		T3	834		T10	414
valid_sources[0x07]	244683	1			T1	590		T2	2		T3	789
valid_sources[0x08]	284834	1			T1	591		T3	831		T10	412
valid_sources[0x09]	249739	1			T1	557		T3	833		T10	441
valid_sources[0x0a]	234917	1			T1	563		T2	14		T3	791
valid_sources[0x0b]	231805	1			T1	631		T2	7		T3	810
valid_sources[0x0c]	245721	1			T1	583		T3	755		T10	392
valid_sources[0x0d]	289049	1			T1	599		T3	777		T10	413
valid_sources[0x0e]	225525	1			T1	572		T2	2		T3	828
valid_sources[0x0f]	264762	1			T1	600		T3	746		T10	363
valid_sources[0x10]	219402	1			T1	610		T2	2		T3	787
valid_sources[0x11]	281669	1			T1	611		T2	3		T3	819
valid_sources[0x12]	302128	1			T1	560		T2	9		T3	800
valid_sources[0x13]	280496	1			T1	512		T3	792		T10	350
valid_sources[0x14]	259339	1			T1	630		T3	841		T10	377
valid_sources[0x15]	278361	1			T1	518		T2	1		T3	802
valid_sources[0x16]	285903	1			T1	672		T2	1		T3	848
valid_sources[0x17]	353620	1			T1	643		T2	9		T3	795
valid_sources[0x18]	222917	1			T1	538		T2	11		T3	741
valid_sources[0x19]	245040	1			T1	635		T2	1		T3	761
valid_sources[0x1a]	247268	1			T1	552		T2	5		T3	769
valid_sources[0x1b]	292213	1			T1	596		T2	3		T3	809
valid_sources[0x1c]	254398	1			T1	696		T3	811		T10	393
valid_sources[0x1d]	256847	1			T1	544		T2	8		T3	805
valid_sources[0x1e]	317949	1			T1	572		T3	796		T10	404
valid_sources[0x1f]	301324	1			T1	617		T3	843		T10	431
valid_sources[0x20]	247585	1			T1	546		T2	1		T3	796
valid_sources[0x21]	265280	1			T1	629		T2	10		T3	746
valid_sources[0x22]	339442	1			T1	569		T2	5		T3	791
valid_sources[0x23]	287839	1			T1	589		T3	798		T10	376
valid_sources[0x24]	261461	1			T1	600		T2	2		T3	818
valid_sources[0x25]	298954	1			T1	620		T2	4		T3	811
valid_sources[0x26]	252549	1			T1	598		T2	6		T3	817
valid_sources[0x27]	241467	1			T1	620		T3	780		T10	386
valid_sources[0x28]	286434	1			T1	607		T3	741		T10	381
valid_sources[0x29]	248046	1			T1	661		T2	6		T3	775
valid_sources[0x2a]	239672	1			T1	582		T2	1		T3	787
valid_sources[0x2b]	279421	1			T1	593		T2	5		T3	803
valid_sources[0x2c]	290041	1			T1	629		T2	11		T3	759
valid_sources[0x2d]	293536	1			T1	640		T2	1		T3	799
valid_sources[0x2e]	263943	1			T1	565		T2	2		T3	793
valid_sources[0x2f]	233294	1			T1	595		T2	9		T3	815
valid_sources[0x30]	289231	1			T1	608		T2	3		T3	831
valid_sources[0x31]	233494	1			T1	614		T2	3		T3	807
valid_sources[0x32]	243259	1			T1	571		T2	3		T3	801
valid_sources[0x33]	312443	1			T1	615		T2	1		T3	811
valid_sources[0x34]	301747	1			T1	634		T3	845		T10	352
valid_sources[0x35]	325207	1			T1	529		T2	1		T3	796
valid_sources[0x36]	295885	1			T1	590		T2	5		T3	840
valid_sources[0x37]	239483	1			T1	637		T2	8		T3	834
valid_sources[0x38]	237963	1			T1	619		T2	3		T3	834
valid_sources[0x39]	330932	1			T1	608		T2	13		T3	823
valid_sources[0x3a]	288106	1			T1	523		T3	772		T10	413
valid_sources[0x3b]	301767	1			T1	699		T2	3		T3	811
valid_sources[0x3c]	309146	1			T1	594		T2	5		T3	791
valid_sources[0x3d]	267489	1			T1	642		T2	2		T3	801
valid_sources[0x3e]	304798	1			T1	681		T2	4		T3	836
valid_sources[0x3f]	281613	1			T1	603		T2	7		T3	835
valid_sources[0x40]	293418	1			T1	676		T2	1		T3	815
valid_sources[0x41]	362203	1			T1	581		T2	4		T3	792
valid_sources[0x42]	292555	1			T1	612		T3	827		T10	395
valid_sources[0x43]	262830	1			T1	562		T2	3		T3	756
valid_sources[0x44]	299185	1			T1	604		T2	4		T3	803
valid_sources[0x45]	251004	1			T1	587		T2	6		T3	774
valid_sources[0x46]	308933	1			T1	582		T2	8		T3	858
valid_sources[0x47]	305390	1			T1	615		T3	748		T10	392
valid_sources[0x48]	304129	1			T1	573		T2	25		T3	778
valid_sources[0x49]	251253	1			T1	669		T2	2		T3	788
valid_sources[0x4a]	338867	1			T1	549		T2	4		T3	787
valid_sources[0x4b]	315204	1			T1	655		T3	837		T10	424
valid_sources[0x4c]	273582	1			T1	667		T3	784		T10	402
valid_sources[0x4d]	336623	1			T1	596		T2	4		T3	793
valid_sources[0x4e]	311935	1			T1	514		T2	9		T3	842
valid_sources[0x4f]	223037	1			T1	562		T2	2		T3	852
valid_sources[0x50]	244002	1			T1	719		T3	803		T10	403
valid_sources[0x51]	242823	1			T1	531		T2	4		T3	831
valid_sources[0x52]	257797	1			T1	634		T2	2		T3	788
valid_sources[0x53]	260503	1			T1	603		T2	4		T3	814
valid_sources[0x54]	266981	1			T1	565		T2	7		T3	818
valid_sources[0x55]	340259	1			T1	610		T2	14		T3	789
valid_sources[0x56]	314816	1			T1	623		T2	6		T3	886
valid_sources[0x57]	290300	1			T1	641		T3	768		T10	369
valid_sources[0x58]	258618	1			T1	611		T2	2		T3	797
valid_sources[0x59]	311832	1			T1	606		T2	1		T3	787
valid_sources[0x5a]	302077	1			T1	588		T2	12		T3	871
valid_sources[0x5b]	272068	1			T1	550		T2	4		T3	777
valid_sources[0x5c]	282744	1			T1	572		T2	7		T3	860
valid_sources[0x5d]	247345	1			T1	589		T2	10		T3	839
valid_sources[0x5e]	237677	1			T1	610		T2	1		T3	818
valid_sources[0x5f]	452481	1			T1	605		T3	784		T10	395
valid_sources[0x60]	264087	1			T1	627		T2	4		T3	785
valid_sources[0x61]	294111	1			T1	631		T2	2		T3	820
valid_sources[0x62]	242413	1			T1	591		T3	813		T10	391
valid_sources[0x63]	406669	1			T1	627		T2	4		T3	800
valid_sources[0x64]	225979	1			T1	612		T3	801		T10	421
valid_sources[0x65]	246029	1			T1	711		T3	780		T10	409
valid_sources[0x66]	251043	1			T1	659		T2	12		T3	821
valid_sources[0x67]	284935	1			T1	581		T3	935		T10	385
valid_sources[0x68]	290844	1			T1	643		T2	9		T3	769
valid_sources[0x69]	272061	1			T1	607		T3	803		T10	434
valid_sources[0x6a]	292608	1			T1	559		T2	14		T3	798
valid_sources[0x6b]	249932	1			T1	612		T2	3		T3	794
valid_sources[0x6c]	282563	1			T1	608		T2	1		T3	819
valid_sources[0x6d]	323952	1			T1	606		T2	1		T3	806
valid_sources[0x6e]	284121	1			T1	638		T3	786		T10	438
valid_sources[0x6f]	311164	1			T1	644		T3	787		T10	426
valid_sources[0x70]	263294	1			T1	571		T2	16		T3	812
valid_sources[0x71]	246648	1			T1	535		T2	4		T3	759
valid_sources[0x72]	297737	1			T1	652		T2	1		T3	828
valid_sources[0x73]	272949	1			T1	543		T2	13		T3	796
valid_sources[0x74]	215437	1			T1	567		T2	10		T3	759
valid_sources[0x75]	243620	1			T1	581		T3	798		T10	385
valid_sources[0x76]	285218	1			T1	594		T2	1		T3	787
valid_sources[0x77]	257591	1			T1	595		T3	791		T10	418
valid_sources[0x78]	224923	1			T1	580		T2	3		T3	853
valid_sources[0x79]	258434	1			T1	631		T2	14		T3	786
valid_sources[0x7a]	246451	1			T1	576		T3	825		T10	389
valid_sources[0x7b]	229768	1			T1	623		T3	811		T10	405
valid_sources[0x7c]	241827	1			T1	641		T2	8		T3	802
valid_sources[0x7d]	236477	1			T1	591		T2	14		T3	846
valid_sources[0x7e]	293749	1			T1	657		T2	6		T3	825
valid_sources[0x7f]	283317	1			T1	568		T2	2		T3	809
valid_sources[0x80]	237602	1			T1	558		T3	807		T10	395

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28166751

1

T1

70304

T3

93993

T9

22528

values[0x0]

all_enables

biggest_size

14192743

1

T1

35282

T2

32

T3

46933

values[0x1]

all_enables

biggest_size

14194186

1

T1

35059

T2

23

T3

46769

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140890

1

T3

8

T9

6

T10

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50118	1			T5	21		T8	80		T6	20
values[0x0]	60022	1			T1	1		T2	1		T3	16
values[0x1]	63859	1			T1	2		T3	14		T9	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148909

1

T1

1

T3

10

T9

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	606	1			T14	7		T46	1		T25	22
valid_sources[0x01]	675	1			T3	10		T54	1		T14	2
valid_sources[0x02]	717	1			T7	1		T54	1		T14	3
valid_sources[0x03]	591	1			T7	1		T25	19		T55	1
valid_sources[0x04]	673	1			T54	1		T14	5		T25	24
valid_sources[0x05]	735	1			T7	2		T14	11		T75	2
valid_sources[0x06]	656	1			T5	1		T8	1		T7	1
valid_sources[0x07]	495	1			T19	13		T36	1		T14	8
valid_sources[0x08]	795	1			T10	1		T7	1		T14	2
valid_sources[0x09]	866	1			T14	6		T16	2		T25	18
valid_sources[0x0a]	748	1			T8	2		T7	1		T128	1
valid_sources[0x0b]	1250	1			T54	1		T92	1		T14	7
valid_sources[0x0c]	672	1			T54	1		T92	1		T25	17
valid_sources[0x0d]	491	1			T7	1		T36	2		T92	1
valid_sources[0x0e]	724	1			T16	6		T25	21		T129	1
valid_sources[0x0f]	592	1			T8	2		T7	1		T25	19
valid_sources[0x10]	546	1			T14	11		T16	1		T25	19
valid_sources[0x11]	628	1			T8	1		T7	1		T92	1
valid_sources[0x12]	673	1			T10	1		T7	1		T14	3
valid_sources[0x13]	708	1			T8	2		T54	1		T14	1
valid_sources[0x14]	1025	1			T10	2		T14	5		T25	22
valid_sources[0x15]	550	1			T5	5		T54	2		T14	20
valid_sources[0x16]	599	1			T10	1		T7	1		T14	11
valid_sources[0x17]	822	1			T14	5		T16	3		T25	15
valid_sources[0x18]	628	1			T5	1		T25	17		T28	5
valid_sources[0x19]	821	1			T14	1		T52	4		T25	25
valid_sources[0x1a]	596	1			T7	1		T14	3		T16	4
valid_sources[0x1b]	903	1			T16	1		T75	5		T25	28
valid_sources[0x1c]	851	1			T46	2		T16	3		T25	15
valid_sources[0x1d]	617	1			T13	2		T8	4		T7	1
valid_sources[0x1e]	789	1			T14	3		T16	1		T25	15
valid_sources[0x1f]	509	1			T7	3		T25	22		T28	13
valid_sources[0x20]	895	1			T54	1		T14	1		T25	21
valid_sources[0x21]	515	1			T7	1		T54	1		T25	27
valid_sources[0x22]	519	1			T14	8		T25	18		T28	6
valid_sources[0x23]	643	1			T8	1		T25	21		T119	1
valid_sources[0x24]	467	1			T25	22		T28	14		T38	5
valid_sources[0x25]	588	1			T15	1		T7	1		T16	2
valid_sources[0x26]	776	1			T10	1		T25	25		T28	31
valid_sources[0x27]	843	1			T10	1		T14	6		T16	3
valid_sources[0x28]	623	1			T14	1		T25	20		T28	2
valid_sources[0x29]	486	1			T14	26		T16	2		T25	24
valid_sources[0x2a]	528	1			T7	1		T14	3		T16	1
valid_sources[0x2b]	719	1			T14	1		T16	3		T25	16
valid_sources[0x2c]	648	1			T14	6		T25	20		T28	2
valid_sources[0x2d]	682	1			T54	1		T25	17		T28	21
valid_sources[0x2e]	640	1			T50	2		T25	14		T28	9
valid_sources[0x2f]	891	1			T16	3		T25	30		T55	9
valid_sources[0x30]	564	1			T25	18		T28	14		T38	5
valid_sources[0x31]	582	1			T14	1		T25	22		T130	1
valid_sources[0x32]	824	1			T7	1		T14	4		T25	28
valid_sources[0x33]	657	1			T8	1		T14	1		T25	21
valid_sources[0x34]	838	1			T19	3		T14	19		T16	2
valid_sources[0x35]	622	1			T7	1		T14	3		T25	26
valid_sources[0x36]	581	1			T36	1		T14	1		T16	4
valid_sources[0x37]	662	1			T7	1		T36	1		T54	2
valid_sources[0x38]	974	1			T8	7		T14	1		T16	1
valid_sources[0x39]	543	1			T14	1		T25	18		T131	1
valid_sources[0x3a]	832	1			T36	1		T14	9		T25	15
valid_sources[0x3b]	630	1			T5	4		T37	1		T14	5
valid_sources[0x3c]	571	1			T50	1		T25	24		T119	1
valid_sources[0x3d]	641	1			T14	1		T25	21		T28	24
valid_sources[0x3e]	822	1			T10	1		T7	1		T54	1
valid_sources[0x3f]	927	1			T5	1		T14	5		T25	19
valid_sources[0x40]	782	1			T36	2		T14	3		T16	1
valid_sources[0x41]	908	1			T5	1		T54	2		T14	9
valid_sources[0x42]	754	1			T14	3		T16	1		T25	17
valid_sources[0x43]	684	1			T54	2		T14	6		T25	17
valid_sources[0x44]	526	1			T6	8		T46	2		T25	21
valid_sources[0x45]	685	1			T36	1		T54	3		T14	9
valid_sources[0x46]	700	1			T54	1		T25	20		T28	5
valid_sources[0x47]	865	1			T14	6		T25	16		T56	7
valid_sources[0x48]	685	1			T14	3		T25	25		T28	8
valid_sources[0x49]	587	1			T36	1		T14	1		T46	2
valid_sources[0x4a]	619	1			T10	1		T54	1		T14	3
valid_sources[0x4b]	549	1			T7	1		T14	4		T25	20
valid_sources[0x4c]	594	1			T14	3		T25	19		T28	20
valid_sources[0x4d]	1074	1			T14	1		T25	22		T28	8
valid_sources[0x4e]	673	1			T7	1		T14	2		T25	19
valid_sources[0x4f]	885	1			T14	6		T51	3		T16	1
valid_sources[0x50]	533	1			T54	1		T14	1		T25	29
valid_sources[0x51]	532	1			T54	1		T14	9		T25	16
valid_sources[0x52]	713	1			T8	1		T54	2		T14	5
valid_sources[0x53]	676	1			T14	5		T25	20		T28	31
valid_sources[0x54]	757	1			T14	10		T25	17		T28	9
valid_sources[0x55]	632	1			T5	3		T7	1		T54	1
valid_sources[0x56]	837	1			T7	1		T14	9		T25	18
valid_sources[0x57]	556	1			T12	11		T8	2		T25	10
valid_sources[0x58]	672	1			T7	1		T36	1		T67	1
valid_sources[0x59]	719	1			T14	4		T25	21		T129	1
valid_sources[0x5a]	626	1			T5	2		T8	3		T14	15
valid_sources[0x5b]	973	1			T8	4		T7	1		T14	15
valid_sources[0x5c]	534	1			T14	8		T16	1		T25	27
valid_sources[0x5d]	521	1			T8	1		T14	9		T21	11
valid_sources[0x5e]	842	1			T7	1		T25	29		T28	21
valid_sources[0x5f]	542	1			T7	1		T14	4		T132	2
valid_sources[0x60]	642	1			T8	1		T36	1		T14	2
valid_sources[0x61]	570	1			T25	19		T28	11		T76	1
valid_sources[0x62]	700	1			T36	1		T25	20		T55	6
valid_sources[0x63]	452	1			T14	16		T25	17		T28	6
valid_sources[0x64]	524	1			T36	1		T37	3		T14	4
valid_sources[0x65]	696	1			T14	1		T16	1		T25	26
valid_sources[0x66]	648	1			T14	16		T75	2		T25	23
valid_sources[0x67]	500	1			T54	1		T14	8		T25	26
valid_sources[0x68]	533	1			T14	1		T16	3		T25	20
valid_sources[0x69]	755	1			T92	1		T14	2		T25	22
valid_sources[0x6a]	546	1			T14	9		T25	25		T55	3
valid_sources[0x6b]	780	1			T6	2		T14	8		T25	19
valid_sources[0x6c]	501	1			T10	1		T14	1		T16	2
valid_sources[0x6d]	642	1			T19	3		T7	1		T14	15
valid_sources[0x6e]	647	1			T14	5		T16	6		T25	20
valid_sources[0x6f]	858	1			T25	28		T119	1		T28	1
valid_sources[0x70]	732	1			T7	1		T14	1		T25	23
valid_sources[0x71]	618	1			T54	1		T14	10		T25	22
valid_sources[0x72]	606	1			T5	2		T14	2		T16	7
valid_sources[0x73]	911	1			T5	1		T8	2		T54	4
valid_sources[0x74]	941	1			T14	3		T50	3		T25	28
valid_sources[0x75]	657	1			T8	3		T6	7		T25	25
valid_sources[0x76]	827	1			T14	2		T16	1		T75	2
valid_sources[0x77]	1157	1			T25	13		T55	20		T28	12
valid_sources[0x78]	710	1			T10	1		T8	1		T14	3
valid_sources[0x79]	559	1			T5	2		T14	13		T16	2
valid_sources[0x7a]	556	1			T3	3		T19	1		T17	1
valid_sources[0x7b]	626	1			T10	1		T6	2		T14	10
valid_sources[0x7c]	629	1			T7	2		T14	17		T25	18
valid_sources[0x7d]	607	1			T46	1		T25	16		T28	13
valid_sources[0x7e]	534	1			T3	9		T54	1		T14	7
valid_sources[0x7f]	734	1			T54	1		T14	10		T25	17
valid_sources[0x80]	685	1			T14	7		T25	21		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38395

1

T5

6

T6

8

T7

22

values[0x0]

all_enables

biggest_size

52320

1

T3

7

T9

3

T10

7

values[0x1]

all_enables

biggest_size

50175

1

T3

1

T9

3

T10

1