Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13336411

1

T1

14117

T2

914

T3

15010

full_word

51859664

1

T1

140645

T2

55

T3

149954

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65195815	1			T1	154762		T2	969		T3	164964
auto[TlIntgErrCmd]	85	1			T95	5		T96	4		T97	3
auto[TlIntgErrData]	84	1			T95	3		T96	2		T97	3
auto[TlIntgErrBoth]	91	1			T95	2		T96	4		T97	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29931306

1

T1

77375

T2

366

T3

61844

auto[1]

35264769

1

T1

77387

T2

603

T3

103120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6378389	1			T1	7071		T2	366		T3	5592
auto[TlIntgErrNone]	partial	auto[1]	6957777	1			T1	7046		T2	548		T3	9418
auto[TlIntgErrNone]	full_word	auto[0]	23552795	1			T1	70304		T3	56252		T9	22528
auto[TlIntgErrNone]	full_word	auto[1]	28306854	1			T1	70341		T2	55		T3	93702
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T95	3		T96	1		T97	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T95	1		T96	2		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T96	1		T106	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T95	1		T110	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T95	2		T96	1		T97	1
auto[TlIntgErrData]	partial	auto[1]	33	1			T95	1		T97	2		T112	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T96	1		T111	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T95	1		T96	1		T97	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T95	1		T96	3		T97	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T110	1		T116	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T115	1		T118	1		T114	1