Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	614117	1			T3	2578		T14	2529		T16	9333
auto[1]	10047428	1			T1	65080		T2	319		T3	673
auto[2]	499350	1			T3	2429		T5	1		T14	2469
auto[3]	9937375	1			T1	65076		T2	541		T3	389

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14033366	1			T1	107640		T2	7		T3	4716
auto[1]	1991461	1			T1	10645		T2	48		T3	703
auto[2]	1973936	1			T1	10818		T2	101		T3	565
auto[3]	3099507	1			T1	1053		T2	704		T3	85

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8741396

1

T2

859

T3

6065

T10

6435

auto[1]

12356874

1

T1

130156

T2

1

T3

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	143226	1			T3	2124		T14	2055		T16	7682
auto[0]	auto[0]	auto[1]	15341	1			T3	217		T14	239		T16	829
auto[0]	auto[0]	auto[2]	15041	1			T3	207		T14	214		T16	735
auto[0]	auto[0]	auto[3]	6540	1			T3	27		T14	13		T16	83
auto[0]	auto[1]	auto[0]	3432233	1			T3	368		T10	2640		T4	1026
auto[0]	auto[1]	auto[1]	356813	1			T3	238		T10	266		T4	295
auto[0]	auto[1]	auto[2]	348244	1			T2	56		T3	40		T10	249
auto[0]	auto[1]	auto[3]	74555	1			T2	262		T3	27		T10	26
auto[0]	auto[2]	auto[0]	126780	1			T3	2044		T5	1		T14	2030
auto[0]	auto[2]	auto[1]	13415	1			T3	223		T14	215		T16	687
auto[0]	auto[2]	auto[2]	11708	1			T3	154		T14	198		T16	604
auto[0]	auto[2]	auto[3]	4938	1			T3	7		T14	23		T16	61
auto[0]	auto[3]	auto[0]	3414904	1			T2	7		T3	176		T10	2660
auto[0]	auto[3]	auto[1]	346265	1			T2	48		T3	25		T10	289
auto[0]	auto[3]	auto[2]	353940	1			T2	44		T3	164		T10	260
auto[0]	auto[3]	auto[3]	77453	1			T2	442		T3	24		T10	45
auto[1]	auto[0]	auto[0]	14419	1			T3	3		T14	7		T16	4
auto[1]	auto[0]	auto[1]	64716	1			T14	1		T126	1		T94	4033
auto[1]	auto[0]	auto[2]	64848	1			T94	3956		T124	2262		T125	1799
auto[1]	auto[0]	auto[3]	289986	1			T94	17512		T124	10075		T127	1
auto[1]	auto[1]	auto[0]	3444436	1			T1	53827		T10	2		T4	1
auto[1]	auto[1]	auto[1]	594298	1			T1	5289		T4	1		T18	3
auto[1]	auto[1]	auto[2]	552537	1			T1	5451		T2	1		T10	1
auto[1]	auto[1]	auto[3]	1244312	1			T1	513		T15	1		T19	1
auto[1]	auto[2]	auto[0]	12610	1			T3	1		T14	2		T16	5
auto[1]	auto[2]	auto[1]	56777	1			T16	1		T94	3536		T124	2037
auto[1]	auto[2]	auto[2]	49506	1			T14	1		T16	2		T94	3352
auto[1]	auto[2]	auto[3]	223616	1			T94	14618		T124	8587		T125	7376
auto[1]	auto[3]	auto[0]	3444758	1			T1	53813		T10	3		T4	2
auto[1]	auto[3]	auto[1]	543836	1			T1	5356		T18	1		T19	4
auto[1]	auto[3]	auto[2]	578112	1			T1	5367		T4	1		T15	1
auto[1]	auto[3]	auto[3]	1178107	1			T1	540		T19	1		T68	11282