Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	291490218	139346	0	0
ctrl_regwen_rd_A	291490218	6331	0	0
exec_rd_A	291490218	5181	0	0
exec_regwen_rd_A	291490218	5893	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291490218	139346	0	0
T14	152590	1207	0	0
T25	0	6790	0	0
T28	0	3261	0	0
T38	0	1261	0	0
T39	0	2427	0	0
T40	0	1883	0	0
T41	0	5464	0	0
T42	0	2094	0	0
T43	0	922	0	0
T44	0	2873	0	0
T45	190612	0	0	0
T46	86128	0	0	0
T47	20143	0	0	0
T48	12766	0	0	0
T49	54621	0	0	0
T50	194411	0	0	0
T51	307306	0	0	0
T52	223180	0	0	0
T53	324209	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291490218	6331	0	0
T14	152590	175	0	0
T39	0	657	0	0
T42	0	417	0	0
T44	0	753	0	0
T45	190612	0	0	0
T46	86128	0	0	0
T47	20143	0	0	0
T48	12766	0	0	0
T49	54621	0	0	0
T50	194411	0	0	0
T51	307306	0	0	0
T52	223180	0	0	0
T53	324209	0	0	0
T98	0	194	0	0
T99	0	217	0	0
T100	0	692	0	0
T101	0	116	0	0
T102	0	99	0	0
T103	0	190	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291490218	5181	0	0
T14	152590	90	0	0
T39	0	536	0	0
T42	0	351	0	0
T44	0	557	0	0
T45	190612	0	0	0
T46	86128	0	0	0
T47	20143	0	0	0
T48	12766	0	0	0
T49	54621	0	0	0
T50	194411	0	0	0
T51	307306	0	0	0
T52	223180	0	0	0
T53	324209	0	0	0
T98	0	165	0	0
T99	0	180	0	0
T100	0	583	0	0
T101	0	98	0	0
T102	0	108	0	0
T103	0	113	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	291490218	5893	0	0
T14	152590	170	0	0
T39	0	675	0	0
T42	0	429	0	0
T44	0	674	0	0
T45	190612	0	0	0
T46	86128	0	0	0
T47	20143	0	0	0
T48	12766	0	0	0
T49	54621	0	0	0
T50	194411	0	0	0
T51	307306	0	0	0
T52	223180	0	0	0
T53	324209	0	0	0
T98	0	143	0	0
T99	0	194	0	0
T100	0	734	0	0
T101	0	125	0	0
T102	0	106	0	0
T103	0	125	0	0