Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14229056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60363798

1

T2

186712

T3

139163

T4

1753

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37186744	1			T2	102899		T3	76317		T4	966
values[0x0]	17276567	1			T2	49421		T3	36834		T4	464
values[0x1]	20129543	1			T2	52975		T3	40019		T4	509

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7086806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67506048

1

T2

196060

T3

146190

T4

1847

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	251898	1			T5	5		T6	601		T8	35
valid_sources[0x01]	339572	1			T4	72		T5	36		T6	581
valid_sources[0x02]	348260	1			T6	598		T8	42		T9	128
valid_sources[0x03]	298002	1			T4	6		T5	1		T6	547
valid_sources[0x04]	290929	1			T6	613		T8	37		T9	74
valid_sources[0x05]	319107	1			T3	3060		T6	612		T8	32
valid_sources[0x06]	276674	1			T6	565		T8	35		T9	103
valid_sources[0x07]	272073	1			T6	656		T8	19		T9	86
valid_sources[0x08]	271015	1			T4	74		T6	585		T8	48
valid_sources[0x09]	281874	1			T5	23		T6	564		T8	35
valid_sources[0x0a]	273184	1			T4	135		T5	2		T6	552
valid_sources[0x0b]	330617	1			T6	526		T8	38		T9	72
valid_sources[0x0c]	253893	1			T5	1		T6	549		T8	45
valid_sources[0x0d]	258181	1			T5	41		T6	552		T8	39
valid_sources[0x0e]	326857	1			T6	632		T8	32		T9	145
valid_sources[0x0f]	315666	1			T4	9		T6	624		T8	37
valid_sources[0x10]	307413	1			T4	49		T6	560		T8	42
valid_sources[0x11]	367505	1			T6	676		T8	41		T9	94
valid_sources[0x12]	277666	1			T6	590		T8	34		T9	125
valid_sources[0x13]	262793	1			T4	41		T5	21		T6	599
valid_sources[0x14]	311689	1			T2	3901		T5	44		T6	605
valid_sources[0x15]	294599	1			T6	605		T8	35		T9	106
valid_sources[0x16]	312446	1			T2	24		T3	4217		T4	68
valid_sources[0x17]	274450	1			T6	624		T8	38		T9	68
valid_sources[0x18]	267418	1			T6	632		T8	42		T9	106
valid_sources[0x19]	373834	1			T2	5139		T5	65		T6	605
valid_sources[0x1a]	312837	1			T6	592		T8	39		T9	92
valid_sources[0x1b]	276575	1			T5	17		T6	588		T8	46
valid_sources[0x1c]	271602	1			T6	603		T8	42		T9	95
valid_sources[0x1d]	264875	1			T2	139		T4	30		T6	566
valid_sources[0x1e]	261130	1			T5	6		T6	584		T8	36
valid_sources[0x1f]	298910	1			T6	590		T8	37		T9	95
valid_sources[0x20]	276648	1			T2	3254		T6	622		T8	41
valid_sources[0x21]	274208	1			T5	19		T6	533		T8	35
valid_sources[0x22]	306184	1			T6	597		T8	54		T9	76
valid_sources[0x23]	269887	1			T6	618		T8	44		T9	132
valid_sources[0x24]	249375	1			T2	2997		T5	85		T6	543
valid_sources[0x25]	285713	1			T6	612		T8	31		T9	131
valid_sources[0x26]	265711	1			T5	128		T6	640		T8	34
valid_sources[0x27]	258729	1			T4	40		T6	564		T8	34
valid_sources[0x28]	374713	1			T6	613		T8	53		T9	104
valid_sources[0x29]	243820	1			T6	560		T8	36		T9	198
valid_sources[0x2a]	269150	1			T6	622		T8	29		T9	59
valid_sources[0x2b]	246865	1			T5	81		T6	596		T8	27
valid_sources[0x2c]	354741	1			T6	568		T8	45		T9	111
valid_sources[0x2d]	275937	1			T2	11600		T6	608		T8	28
valid_sources[0x2e]	241974	1			T6	662		T8	26		T9	121
valid_sources[0x2f]	298058	1			T6	587		T8	44		T9	90
valid_sources[0x30]	258332	1			T6	594		T8	34		T9	148
valid_sources[0x31]	294973	1			T6	608		T8	35		T9	135
valid_sources[0x32]	268143	1			T4	23		T6	632		T8	30
valid_sources[0x33]	352955	1			T4	8		T6	632		T8	52
valid_sources[0x34]	322323	1			T2	18238		T6	579		T8	27
valid_sources[0x35]	292306	1			T2	7326		T3	4925		T6	634
valid_sources[0x36]	255243	1			T6	496		T8	26		T9	66
valid_sources[0x37]	272238	1			T4	58		T5	50		T6	572
valid_sources[0x38]	245286	1			T6	595		T8	39		T9	69
valid_sources[0x39]	284661	1			T6	590		T8	46		T9	92
valid_sources[0x3a]	275411	1			T5	43		T6	641		T8	43
valid_sources[0x3b]	250341	1			T6	617		T8	32		T9	114
valid_sources[0x3c]	275099	1			T2	5402		T6	555		T8	43
valid_sources[0x3d]	302553	1			T6	610		T8	37		T9	85
valid_sources[0x3e]	291441	1			T6	542		T8	31		T9	96
valid_sources[0x3f]	292204	1			T6	561		T8	24		T9	110
valid_sources[0x40]	284108	1			T6	607		T8	47		T9	102
valid_sources[0x41]	350477	1			T5	15		T6	597		T8	36
valid_sources[0x42]	264542	1			T6	611		T8	39		T9	94
valid_sources[0x43]	300431	1			T6	571		T8	36		T9	114
valid_sources[0x44]	298514	1			T2	130		T6	575		T8	33
valid_sources[0x45]	330795	1			T6	590		T8	49		T9	105
valid_sources[0x46]	340357	1			T6	588		T8	43		T9	60
valid_sources[0x47]	308048	1			T3	6294		T6	595		T8	50
valid_sources[0x48]	253290	1			T6	630		T8	33		T9	155
valid_sources[0x49]	278878	1			T2	3868		T6	604		T8	38
valid_sources[0x4a]	320975	1			T5	4		T6	584		T8	47
valid_sources[0x4b]	298992	1			T6	520		T8	42		T9	59
valid_sources[0x4c]	305806	1			T6	561		T8	40		T9	101
valid_sources[0x4d]	310494	1			T6	605		T8	39		T9	126
valid_sources[0x4e]	247221	1			T4	22		T6	594		T8	36
valid_sources[0x4f]	297686	1			T6	611		T8	45		T9	81
valid_sources[0x50]	272988	1			T6	609		T8	33		T9	60
valid_sources[0x51]	325844	1			T2	23225		T6	604		T8	27
valid_sources[0x52]	253392	1			T3	5837		T6	609		T8	32
valid_sources[0x53]	323078	1			T6	581		T8	34		T9	74
valid_sources[0x54]	310751	1			T6	689		T8	37		T9	79
valid_sources[0x55]	265360	1			T6	645		T8	35		T9	104
valid_sources[0x56]	351322	1			T6	533		T8	39		T9	132
valid_sources[0x57]	285345	1			T6	661		T8	40		T9	106
valid_sources[0x58]	245392	1			T6	537		T8	45		T9	90
valid_sources[0x59]	260656	1			T2	1287		T5	1		T6	574
valid_sources[0x5a]	345945	1			T5	50		T6	532		T8	49
valid_sources[0x5b]	248568	1			T2	6499		T5	1		T6	607
valid_sources[0x5c]	278745	1			T5	3		T6	594		T8	31
valid_sources[0x5d]	281749	1			T5	3		T6	597		T8	32
valid_sources[0x5e]	267655	1			T5	10		T6	563		T8	40
valid_sources[0x5f]	286461	1			T6	601		T8	34		T9	146
valid_sources[0x60]	327293	1			T3	19167		T5	4		T6	582
valid_sources[0x61]	251909	1			T5	2		T6	591		T8	43
valid_sources[0x62]	288258	1			T2	44		T4	38		T6	591
valid_sources[0x63]	322627	1			T6	626		T8	40		T9	58
valid_sources[0x64]	336409	1			T5	8		T6	598		T8	46
valid_sources[0x65]	298736	1			T5	44		T6	643		T8	37
valid_sources[0x66]	261680	1			T6	608		T8	29		T9	150
valid_sources[0x67]	287280	1			T2	26		T6	560		T8	32
valid_sources[0x68]	253215	1			T5	84		T6	613		T8	37
valid_sources[0x69]	307247	1			T6	559		T8	35		T9	82
valid_sources[0x6a]	319673	1			T5	43		T6	588		T8	33
valid_sources[0x6b]	293629	1			T6	566		T8	43		T9	107
valid_sources[0x6c]	296265	1			T6	575		T8	27		T9	139
valid_sources[0x6d]	292986	1			T5	40		T6	604		T8	51
valid_sources[0x6e]	291786	1			T2	13718		T3	11267		T6	556
valid_sources[0x6f]	269309	1			T6	536		T8	31		T9	64
valid_sources[0x70]	344745	1			T6	599		T8	38		T9	114
valid_sources[0x71]	257690	1			T4	46		T5	1		T6	584
valid_sources[0x72]	284150	1			T6	601		T8	35		T9	110
valid_sources[0x73]	266927	1			T2	65		T6	619		T8	40
valid_sources[0x74]	276716	1			T5	128		T6	581		T8	33
valid_sources[0x75]	304695	1			T6	618		T8	37		T9	143
valid_sources[0x76]	358342	1			T4	93		T6	584		T8	32
valid_sources[0x77]	309751	1			T6	604		T8	33		T9	69
valid_sources[0x78]	254312	1			T2	536		T6	568		T8	33
valid_sources[0x79]	242536	1			T6	597		T8	39		T9	122
valid_sources[0x7a]	287915	1			T3	4232		T6	623		T8	38
valid_sources[0x7b]	351021	1			T6	560		T8	39		T9	107
valid_sources[0x7c]	247787	1			T3	2921		T6	575		T8	36
valid_sources[0x7d]	293372	1			T5	1		T6	612		T8	39
valid_sources[0x7e]	269021	1			T2	2		T5	55		T6	617
valid_sources[0x7f]	274970	1			T6	596		T8	36		T9	134
valid_sources[0x80]	292112	1			T6	562		T8	38		T9	107

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30077371

1

T2

93667

T3

69328

T4

876

values[0x0]

all_enables

biggest_size

15141810

1

T2

46573

T3

34723

T4

443

values[0x1]

all_enables

biggest_size

15144617

1

T2

46472

T3

35112

T4

434

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

136947

1

T2

6

T3

4

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49986	1			T4	19		T5	27		T9	3
values[0x0]	58571	1			T1	1		T2	22		T3	11
values[0x1]	62967	1			T2	17		T3	6		T4	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144992

1

T2

10

T3

6

T4

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	750	1			T4	1		T143	2		T28	2
valid_sources[0x01]	627	1			T24	2		T16	1		T144	1
valid_sources[0x02]	548	1			T16	2		T28	15		T29	5
valid_sources[0x03]	622	1			T4	1		T14	1		T25	1
valid_sources[0x04]	683	1			T143	1		T145	3		T28	10
valid_sources[0x05]	648	1			T5	2		T6	1		T14	5
valid_sources[0x06]	700	1			T5	1		T123	8		T96	1
valid_sources[0x07]	902	1			T5	1		T6	1		T14	1
valid_sources[0x08]	787	1			T143	1		T28	19		T29	10
valid_sources[0x09]	603	1			T24	1		T123	1		T28	31
valid_sources[0x0a]	661	1			T5	1		T28	46		T59	2
valid_sources[0x0b]	607	1			T4	1		T17	3		T16	1
valid_sources[0x0c]	650	1			T139	3		T28	15		T53	6
valid_sources[0x0d]	995	1			T25	1		T123	3		T140	1
valid_sources[0x0e]	567	1			T4	1		T6	1		T139	4
valid_sources[0x0f]	562	1			T4	1		T143	2		T146	1
valid_sources[0x10]	633	1			T4	1		T61	1		T16	4
valid_sources[0x11]	564	1			T123	1		T139	1		T96	1
valid_sources[0x12]	433	1			T143	1		T28	6		T29	6
valid_sources[0x13]	532	1			T142	1		T139	1		T140	1
valid_sources[0x14]	753	1			T26	1		T143	1		T144	1
valid_sources[0x15]	663	1			T5	2		T14	6		T28	12
valid_sources[0x16]	911	1			T4	2		T61	1		T143	1
valid_sources[0x17]	598	1			T143	2		T81	1		T28	11
valid_sources[0x18]	676	1			T24	1		T146	1		T147	4
valid_sources[0x19]	593	1			T143	2		T28	7		T53	2
valid_sources[0x1a]	599	1			T91	2		T123	8		T143	1
valid_sources[0x1b]	502	1			T45	6		T28	1		T29	8
valid_sources[0x1c]	668	1			T24	1		T123	4		T143	1
valid_sources[0x1d]	592	1			T139	1		T28	18		T29	10
valid_sources[0x1e]	492	1			T5	1		T143	1		T28	11
valid_sources[0x1f]	539	1			T6	1		T143	1		T140	1
valid_sources[0x20]	810	1			T26	2		T24	1		T28	31
valid_sources[0x21]	739	1			T14	2		T90	1		T24	1
valid_sources[0x22]	748	1			T26	1		T143	2		T146	1
valid_sources[0x23]	463	1			T143	1		T28	2		T29	9
valid_sources[0x24]	651	1			T14	3		T24	1		T144	1
valid_sources[0x25]	605	1			T24	1		T143	1		T28	9
valid_sources[0x26]	510	1			T6	1		T16	1		T18	1
valid_sources[0x27]	673	1			T32	1		T140	1		T28	9
valid_sources[0x28]	728	1			T5	2		T24	1		T123	2
valid_sources[0x29]	732	1			T143	1		T148	5		T28	13
valid_sources[0x2a]	583	1			T31	30		T24	5		T123	1
valid_sources[0x2b]	656	1			T143	1		T144	1		T146	1
valid_sources[0x2c]	786	1			T28	23		T29	10		T30	9
valid_sources[0x2d]	554	1			T4	2		T143	2		T28	18
valid_sources[0x2e]	545	1			T6	1		T14	4		T61	1
valid_sources[0x2f]	643	1			T140	2		T28	13		T29	7
valid_sources[0x30]	766	1			T46	24		T28	9		T29	5
valid_sources[0x31]	593	1			T5	1		T6	1		T7	8
valid_sources[0x32]	1032	1			T90	1		T28	22		T29	9
valid_sources[0x33]	493	1			T145	1		T28	8		T53	1
valid_sources[0x34]	700	1			T145	6		T28	12		T29	10
valid_sources[0x35]	679	1			T5	1		T24	1		T25	1
valid_sources[0x36]	574	1			T5	1		T143	1		T146	1
valid_sources[0x37]	487	1			T26	1		T25	1		T123	1
valid_sources[0x38]	499	1			T123	1		T18	1		T143	1
valid_sources[0x39]	553	1			T16	2		T28	14		T29	6
valid_sources[0x3a]	625	1			T24	1		T25	1		T144	1
valid_sources[0x3b]	522	1			T123	6		T143	1		T28	10
valid_sources[0x3c]	806	1			T14	4		T24	1		T144	1
valid_sources[0x3d]	974	1			T12	1		T143	1		T28	14
valid_sources[0x3e]	679	1			T143	1		T28	9		T29	8
valid_sources[0x3f]	591	1			T5	2		T25	1		T142	1
valid_sources[0x40]	595	1			T24	2		T28	20		T29	7
valid_sources[0x41]	743	1			T25	1		T28	22		T29	7
valid_sources[0x42]	1059	1			T4	1		T28	22		T29	9
valid_sources[0x43]	591	1			T4	1		T16	1		T28	31
valid_sources[0x44]	564	1			T28	6		T29	5		T30	7
valid_sources[0x45]	549	1			T25	1		T143	1		T140	1
valid_sources[0x46]	943	1			T4	1		T143	2		T80	1
valid_sources[0x47]	802	1			T28	26		T53	3		T29	5
valid_sources[0x48]	541	1			T24	1		T28	10		T29	8
valid_sources[0x49]	623	1			T25	1		T143	2		T28	13
valid_sources[0x4a]	576	1			T5	2		T28	19		T29	7
valid_sources[0x4b]	464	1			T14	1		T25	1		T143	1
valid_sources[0x4c]	647	1			T14	1		T143	3		T28	15
valid_sources[0x4d]	578	1			T6	1		T26	1		T146	1
valid_sources[0x4e]	1006	1			T5	1		T26	2		T28	17
valid_sources[0x4f]	874	1			T4	2		T5	1		T123	3
valid_sources[0x50]	897	1			T142	1		T143	1		T146	1
valid_sources[0x51]	564	1			T27	1		T149	11		T28	14
valid_sources[0x52]	692	1			T90	1		T150	28		T145	1
valid_sources[0x53]	499	1			T5	3		T140	2		T145	5
valid_sources[0x54]	746	1			T28	25		T29	7		T30	9
valid_sources[0x55]	469	1			T29	13		T30	5		T120	1
valid_sources[0x56]	744	1			T28	13		T60	2		T29	13
valid_sources[0x57]	614	1			T24	1		T143	2		T146	1
valid_sources[0x58]	562	1			T26	1		T61	1		T25	1
valid_sources[0x59]	531	1			T4	1		T14	2		T24	1
valid_sources[0x5a]	741	1			T2	39		T10	2		T123	6
valid_sources[0x5b]	568	1			T24	1		T25	1		T28	29
valid_sources[0x5c]	519	1			T25	1		T28	20		T29	9
valid_sources[0x5d]	710	1			T16	2		T28	14		T29	6
valid_sources[0x5e]	663	1			T7	20		T25	1		T123	4
valid_sources[0x5f]	789	1			T5	2		T90	1		T24	2
valid_sources[0x60]	662	1			T14	3		T17	3		T62	51
valid_sources[0x61]	815	1			T143	5		T144	1		T28	18
valid_sources[0x62]	991	1			T6	1		T142	2		T145	5
valid_sources[0x63]	606	1			T14	4		T7	3		T25	1
valid_sources[0x64]	857	1			T5	2		T25	4		T143	1
valid_sources[0x65]	679	1			T26	1		T25	1		T143	2
valid_sources[0x66]	569	1			T4	1		T143	1		T140	4
valid_sources[0x67]	599	1			T28	5		T29	7		T30	4
valid_sources[0x68]	647	1			T4	1		T90	1		T26	2
valid_sources[0x69]	463	1			T28	15		T53	1		T29	4
valid_sources[0x6a]	860	1			T143	1		T28	14		T29	6
valid_sources[0x6b]	676	1			T5	1		T6	2		T28	16
valid_sources[0x6c]	521	1			T8	1		T24	1		T28	14
valid_sources[0x6d]	792	1			T151	2		T28	33		T29	8
valid_sources[0x6e]	631	1			T14	2		T123	3		T28	29
valid_sources[0x6f]	718	1			T92	3		T61	1		T24	1
valid_sources[0x70]	1028	1			T4	1		T6	1		T31	1
valid_sources[0x71]	702	1			T24	1		T28	9		T29	8
valid_sources[0x72]	827	1			T4	1		T6	1		T61	2
valid_sources[0x73]	706	1			T4	1		T28	13		T57	1
valid_sources[0x74]	756	1			T143	1		T28	1		T29	6
valid_sources[0x75]	824	1			T6	1		T143	2		T152	7
valid_sources[0x76]	518	1			T90	1		T24	1		T28	21
valid_sources[0x77]	704	1			T5	1		T6	1		T26	4
valid_sources[0x78]	549	1			T14	2		T90	1		T15	10
valid_sources[0x79]	615	1			T6	1		T25	2		T139	3
valid_sources[0x7a]	596	1			T5	1		T11	1		T16	2
valid_sources[0x7b]	795	1			T5	1		T153	1		T28	10
valid_sources[0x7c]	929	1			T90	1		T61	1		T28	14
valid_sources[0x7d]	575	1			T24	1		T143	1		T28	9
valid_sources[0x7e]	476	1			T4	1		T123	1		T143	1
valid_sources[0x7f]	541	1			T5	3		T24	1		T28	11
valid_sources[0x80]	806	1			T14	1		T123	2		T139	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37846

1

T4

11

T5

15

T9

2

values[0x0]

all_enables

biggest_size

50325

1

T2

3

T3

4

T4

3

values[0x1]

all_enables

biggest_size

48776

1

T2

3

T5

2

T6

4